diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-09-16 09:14:31 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-09-16 09:14:31 +0100 |
| commit | ada0e2f02fb3a30d01f62eb124a1d374be0b8ed5 (patch) | |
| tree | 82c5b4db42b6ade0e4eeed758be629c57e2f5f60 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | |
| parent | 1ecc3628a8fe24d8ed189ee23ca41f2b385b3d8e (diff) | |
| download | gem5-ada0e2f02fb3a30d01f62eb124a1d374be0b8ed5.tar.xz | |
tests, arm: Make switcheroo and checkpoint tests functional
Switcheroo and checkpoint tests should generally be considered to be
successful if they run to completion. Remove all reference output
files from the switcheroo and checkopint tests to make them purely
functional.
Change-Id: I70b47853bd662b7a33716d9e0d2154b16077f9dc
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | 2704 |
1 files changed, 0 insertions, 2704 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt deleted file mode 100644 index 21f94071a..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ /dev/null @@ -1,2704 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.804492 # Number of seconds simulated -sim_ticks 2804492191000 # Number of ticks simulated -final_tick 2804492191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104736 # Simulator instruction rate (inst/s) -host_op_rate 127120 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2512420654 # Simulator tick rate (ticks/s) -host_mem_usage 592468 # Number of bytes of host memory used -host_seconds 1116.25 # Real time elapsed on the host -sim_insts 116911529 # Number of instructions simulated -sim_ops 141898255 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 4032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 689856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4962016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 685888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4855432 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11202536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 689856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 685888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1375744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8427008 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8444532 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 63 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 78050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 67 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10717 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75868 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175560 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131672 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136053 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 245982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1769310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 244568 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1731305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3994497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 245982 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 244568 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 490550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3004825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3011073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3004825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 245982 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1775556 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 244568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1731308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7005571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175561 # Number of read requests accepted -system.physmem.writeReqs 136053 # Number of write requests accepted -system.physmem.readBursts 175561 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 136053 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11226560 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue -system.physmem.bytesWritten 8456704 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11202600 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8444532 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11215 # Per bank write bursts -system.physmem.perBankRdBursts::1 11147 # Per bank write bursts -system.physmem.perBankRdBursts::2 11273 # Per bank write bursts -system.physmem.perBankRdBursts::3 10737 # Per bank write bursts -system.physmem.perBankRdBursts::4 11860 # Per bank write bursts -system.physmem.perBankRdBursts::5 11441 # Per bank write bursts -system.physmem.perBankRdBursts::6 12346 # Per bank write bursts -system.physmem.perBankRdBursts::7 11875 # Per bank write bursts -system.physmem.perBankRdBursts::8 10047 # Per bank write bursts -system.physmem.perBankRdBursts::9 10348 # Per bank write bursts -system.physmem.perBankRdBursts::10 10556 # Per bank write bursts -system.physmem.perBankRdBursts::11 9541 # Per bank write bursts -system.physmem.perBankRdBursts::12 10610 # Per bank write bursts -system.physmem.perBankRdBursts::13 11371 # Per bank write bursts -system.physmem.perBankRdBursts::14 10552 # Per bank write bursts -system.physmem.perBankRdBursts::15 10496 # Per bank write bursts -system.physmem.perBankWrBursts::0 8375 # Per bank write bursts -system.physmem.perBankWrBursts::1 8461 # Per bank write bursts -system.physmem.perBankWrBursts::2 8703 # Per bank write bursts -system.physmem.perBankWrBursts::3 8182 # Per bank write bursts -system.physmem.perBankWrBursts::4 8713 # Per bank write bursts -system.physmem.perBankWrBursts::5 8565 # Per bank write bursts -system.physmem.perBankWrBursts::6 9253 # Per bank write bursts -system.physmem.perBankWrBursts::7 8873 # Per bank write bursts -system.physmem.perBankWrBursts::8 7587 # Per bank write bursts -system.physmem.perBankWrBursts::9 7750 # Per bank write bursts -system.physmem.perBankWrBursts::10 7865 # Per bank write bursts -system.physmem.perBankWrBursts::11 7197 # Per bank write bursts -system.physmem.perBankWrBursts::12 8117 # Per bank write bursts -system.physmem.perBankWrBursts::13 8726 # Per bank write bursts -system.physmem.perBankWrBursts::14 7969 # Per bank write bursts -system.physmem.perBankWrBursts::15 7800 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 2804492012500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 542 # Read request sizes (log2) -system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 175005 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 4381 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131672 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 103754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1717 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64611 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.641624 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.481113 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.031220 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24202 37.46% 37.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15601 24.15% 61.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6722 10.40% 72.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3765 5.83% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2815 4.36% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.44% 84.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1095 1.69% 86.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1044 1.62% 87.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7791 12.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64611 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6681 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.254154 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 478.043046 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6679 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6681 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6681 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.777878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.220598 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.301236 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 12 0.18% 0.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 6 0.09% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 6 0.09% 0.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.07% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5747 86.02% 86.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 151 2.26% 88.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 95 1.42% 90.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 50 0.75% 90.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 278 4.16% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 50 0.75% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 23 0.34% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.22% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 16 0.24% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.07% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.13% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 158 2.36% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.01% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.04% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.06% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.06% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 8 0.12% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.15% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6681 # Writes before turning the bus around for reads -system.physmem.totQLat 2656456250 # Total ticks spent queuing -system.physmem.totMemAccLat 5945487500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 877075000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15143.84 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33893.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.99 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.27 # Average write queue length when enqueuing -system.physmem.readRowHits 144956 # Number of row buffer hits during reads -system.physmem.writeRowHits 97983 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.14 # Row buffer hit rate for writes -system.physmem.avgGap 8999890.93 # Average gap between requests -system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 256646880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140035500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 716765400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 447930000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 183175683600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 77871232575 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1614386322750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1876994616705 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.281811 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2685576144250 # Time in different power states -system.physmem_0.memoryStateTime::REF 93648100000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 25267936250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 231812280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 126484875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 651463800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 408311280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 183175683600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 76860878220 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1615272598500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1876727232555 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.186470 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2687058026250 # Time in different power states -system.physmem_1.memoryStateTime::REF 93648100000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23784590000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 768 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 768 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 12 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 274 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 274 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 274 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 274 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 274 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 274 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 26597024 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13781156 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 500525 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 15548162 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8034631 # Number of BTB hits -system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 51.675761 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6612410 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28559 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4512781 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 4401242 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 111539 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 32310 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 58420 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 58420 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17812 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14989 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 25619 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 32801 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 529.800921 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3188.709692 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 31978 97.49% 97.49% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 569 1.73% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 144 0.44% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 64 0.20% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 17 0.05% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 11 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-73727 7 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 32801 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 12297 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10850.939253 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9044.162625 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7100.469115 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-8191 4812 39.13% 39.13% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::8192-16383 6113 49.71% 88.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-24575 1067 8.68% 97.52% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::24576-32767 142 1.15% 98.67% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-40959 98 0.80% 99.47% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::40960-49151 40 0.33% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-57343 6 0.05% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::57344-65535 3 0.02% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::73728-81919 1 0.01% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-90111 7 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::90112-98303 3 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-106495 4 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::106496-114687 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 12297 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 80893915836 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.682843 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.485602 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 80818881836 99.91% 99.91% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 52303000 0.06% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 11277500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4307500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2702500 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1677000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 813500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1083500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 273500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 145500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-21 137500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::22-23 22500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-25 149000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::26-27 15000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-29 8000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::30-31 118500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 80893915836 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3573 69.87% 69.87% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1541 30.13% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5114 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 58420 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 58420 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5114 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5114 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 63534 # Table walker requests started/completed, data/inst -system.cpu0.dtb.inst_hits 0 # ITB inst hits -system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 13811519 # DTB read hits -system.cpu0.dtb.read_misses 49680 # DTB read misses -system.cpu0.dtb.write_hits 10255920 # DTB write hits -system.cpu0.dtb.write_misses 8740 # DTB write misses -system.cpu0.dtb.flush_tlb 180 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3407 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 831 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1345 # Number of TLB faults due to prefetch -system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 681 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 13861199 # DTB read accesses -system.cpu0.dtb.write_accesses 10264660 # DTB write accesses -system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24067439 # DTB hits -system.cpu0.dtb.misses 58420 # DTB misses -system.cpu0.dtb.accesses 24125859 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 7709 # Table walker walks requested -system.cpu0.itb.walker.walksShort 7709 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2350 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4518 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 841 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 6868 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1028.028538 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 4446.105505 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-8191 6539 95.21% 95.21% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-16383 228 3.32% 98.53% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-24575 54 0.79% 99.32% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-32767 25 0.36% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-40959 8 0.12% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-49151 8 0.12% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::57344-65535 3 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::73728-81919 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-106495 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 6868 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3155 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10383.835182 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8379.659125 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7218.357480 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1697 53.79% 53.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 897 28.43% 82.22% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 526 16.67% 98.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 22 0.70% 99.59% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 6 0.19% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 4 0.13% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 2 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3155 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 33631218080 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.664997 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.472178 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 11268855428 33.51% 33.51% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 22360574652 66.49% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 1449000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 215000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 92500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 31500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 33631218080 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1735 74.98% 74.98% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 579 25.02% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2314 # Table walker page sizes translated -system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7709 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7709 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2314 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2314 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 10023 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 19932883 # ITB inst hits -system.cpu0.itb.inst_misses 7709 # ITB inst misses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 180 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2198 # Number of entries that have been flushed from TLB -system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1360 # Number of TLB faults due to permissions restrictions -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 19940592 # ITB inst accesses -system.cpu0.itb.hits 19932883 # DTB hits -system.cpu0.itb.misses 7709 # DTB misses -system.cpu0.itb.accesses 19940592 # DTB accesses -system.cpu0.numPwrStateTransitions 3142 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1571 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 940850098.166136 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 18809432155.510696 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1535 97.71% 97.71% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 33 2.10% 99.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.06% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.13% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499976941836 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1571 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 1326416686781 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478075504219 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 106432025 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 39943206 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 102521046 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 26597024 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19048283 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 61908935 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3115038 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 100477 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 4639 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 343 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 145025 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 124692 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 417 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 19931005 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 352594 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3944 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 103785216 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.188198 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.291827 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 75467525 72.72% 72.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3816070 3.68% 76.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2355731 2.27% 78.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 7980688 7.69% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1585704 1.53% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 994797 0.96% 88.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6063354 5.84% 94.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1019951 0.98% 95.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4501396 4.34% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 103785216 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.249897 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.963254 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27593672 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58026004 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15320051 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1430610 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1414570 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1827863 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 144800 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 84662278 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 478152 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1414570 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28401012 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6705964 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 43841646 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 15935208 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7486513 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 81019638 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 3792 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1047421 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 274733 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 5461326 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 83455149 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 373514562 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 90323598 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 7046 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 70490289 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12964860 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1525331 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1431631 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8308638 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 14616199 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11309054 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1973588 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2673938 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 78051120 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1056498 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 74882378 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 90977 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10675596 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 23316802 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 112757 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 103785216 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.721513 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.414764 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 73772912 71.08% 71.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10078271 9.71% 80.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7660438 7.38% 88.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6348835 6.12% 94.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2285768 2.20% 96.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1455335 1.40% 97.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1487712 1.43% 99.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 476853 0.46% 99.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 219092 0.21% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 103785216 # Number of insts issued each cycle -system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 97071 8.87% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 526414 48.10% 56.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 471010 43.03% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2186 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 49813565 66.52% 66.53% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57268 0.08% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4356 0.01% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14194612 18.96% 85.56% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10810388 14.44% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 74882378 # Type of FU issued -system.cpu0.iq.rate 0.703570 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1094496 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014616 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 254720610 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 89827638 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 72651171 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 14835 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 9007 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 6569 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 75966729 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7959 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 355417 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2067343 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2157 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 54598 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1028774 # Number of stores squashed -system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 204196 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 85944 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1414570 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5871401 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 626694 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 79236238 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107112 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 14616199 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11309054 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 550325 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44645 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 570692 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 54598 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 206831 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 220981 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 427812 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 74329730 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 13972872 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 494338 # Number of squashed instructions skipped in execute -system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 128620 # number of nop insts executed -system.cpu0.iew.exec_refs 24687619 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14050828 # Number of branches executed -system.cpu0.iew.exec_stores 10714747 # Number of stores executed -system.cpu0.iew.exec_rate 0.698377 # Inst execution rate -system.cpu0.iew.wb_sent 73810336 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 72657740 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 37782988 # num instructions producing a value -system.cpu0.iew.wb_consumers 65726436 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.682668 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.574852 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10630509 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 943741 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 357539 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 101347140 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.676054 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.564689 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 74567913 73.58% 73.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12119278 11.96% 85.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6061489 5.98% 91.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2574374 2.54% 94.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1279376 1.26% 95.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 838406 0.83% 96.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1806795 1.78% 97.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 395599 0.39% 98.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1703910 1.68% 100.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 101347140 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 56273825 # Number of instructions committed -system.cpu0.commit.committedOps 68516155 # Number of ops (including micro ops) committed -system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 22829136 # Number of memory references committed -system.cpu0.commit.loads 12548856 # Number of loads committed -system.cpu0.commit.membars 380096 # Number of memory barriers committed -system.cpu0.commit.branches 13320608 # Number of branches committed -system.cpu0.commit.fp_insts 6081 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 59986977 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2613752 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 45626966 66.59% 66.59% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55700 0.08% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4353 0.01% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12548856 18.32% 85.00% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10280280 15.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 68516155 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1703910 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 166404387 # The number of ROB reads -system.cpu0.rob.rob_writes 160730663 # The number of ROB writes -system.cpu0.timesIdled 403591 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2646809 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2956150979 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 56189692 # Number of Instructions Simulated -system.cpu0.committedOps 68432022 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.894156 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.894156 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.527940 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.527940 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 80895945 # number of integer regfile reads -system.cpu0.int_regfile_writes 46256017 # number of integer regfile writes -system.cpu0.fp_regfile_reads 17128 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13236 # number of floating regfile writes -system.cpu0.cc_regfile_reads 262969083 # number of cc regfile reads -system.cpu0.cc_regfile_writes 27284448 # number of cc regfile writes -system.cpu0.misc_regfile_reads 188741772 # number of misc regfile reads -system.cpu0.misc_regfile_writes 723817 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 851102 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.984391 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42341917 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 851614 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.719611 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 92671500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.368893 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.615499 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360095 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.639874 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189170266 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189170266 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 12276993 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12891400 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25168393 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7660658 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 8240277 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15900935 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178519 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 185010 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 363529 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 209836 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 236717 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 446553 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216124 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 243253 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459377 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 19937651 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21131677 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41069328 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20116170 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21316687 # number of overall hits -system.cpu0.dcache.overall_hits::total 41432857 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 401226 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 429872 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 831098 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1944439 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1754085 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3698524 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 79996 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 103567 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 183563 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13679 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 13937 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27616 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 39 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 31 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 70 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2345665 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2183957 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4529622 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2425661 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2287524 # number of overall misses -system.cpu0.dcache.overall_misses::total 4713185 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6001869000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6540022000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 12541891000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85882896000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 79793795696 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 165676691696 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 178954000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 206024000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 384978000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 605500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 494000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 1099500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 91884765000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 86333817696 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 178218582696 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 91884765000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 86333817696 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 178218582696 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 12678219 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 13321272 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 25999491 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9605097 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9994362 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19599459 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 258515 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 288577 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 547092 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223515 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 250654 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 474169 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216163 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 243284 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 459447 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 22283316 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 23315634 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 45598950 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 22541831 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 23604211 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 46146042 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031647 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032270 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.031966 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.202438 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.175507 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.188705 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.309444 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.358889 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.335525 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061199 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.055603 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058241 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000180 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000127 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000152 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.105266 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.093669 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.099336 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107607 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.096912 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.102136 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14958.823705 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15213.882272 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15090.748624 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44168.470186 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45490.267402 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44795.353956 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13082.389064 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14782.521346 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13940.396871 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15525.641026 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15935.483871 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15707.142857 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39172.160134 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39530.914618 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39345.133589 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37880.299432 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37741.163676 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37812.770493 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1147990 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 183848 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 53098 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 2861 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.620212 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 64.260049 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 702238 # number of writebacks -system.cpu0.dcache.writebacks::total 702238 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 190024 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 217945 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 407969 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1788584 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1610518 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3399102 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9563 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8886 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18449 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1978608 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1828463 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3807071 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1978608 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1828463 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3807071 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 211202 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 211927 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 423129 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 155855 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 143567 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 299422 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 55758 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 66999 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 122757 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4116 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5051 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9167 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 39 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 31 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 70 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 367057 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 355494 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 722551 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 422815 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 422493 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 845308 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16331 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 14796 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15929 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11655 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32260 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 26451 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3008616500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3065906000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6074522500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7160903385 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6753725936 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13914629321 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 778587000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 955209000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1733796000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 53300000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84160500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137460500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 566500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 463000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1029500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10169519885 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9819631936 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 19989151821 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10948106885 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10774840936 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 21722947821 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3301571000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3002627500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6304198500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3301571000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3002627500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6304198500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016659 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015909 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016275 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016226 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014365 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015277 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.215686 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.232170 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224381 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018415 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020151 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019333 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000180 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000127 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000152 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016472 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015247 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015846 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018757 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017899 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018318 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14245.208379 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14466.802248 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14356.195156 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45945.932983 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47042.328223 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46471.633083 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13963.682342 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14257.063538 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14123.805567 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12949.465500 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16662.146110 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14995.145631 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14525.641026 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14935.483871 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14707.142857 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27705.560403 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27622.496965 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27664.693317 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25893.373899 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25503.004632 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25698.263616 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202165.880840 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202935.083806 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202531.516047 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102342.560446 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113516.596726 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107376.786292 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1935798 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.566475 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 38706343 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1936310 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 19.989745 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9778864500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 232.011267 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 279.555207 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.453147 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.546006 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999153 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 153 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42727106 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42727106 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 18888703 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19817640 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 38706343 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 18888703 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19817640 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 38706343 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 18888703 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19817640 # number of overall hits -system.cpu0.icache.overall_hits::total 38706343 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1041631 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1042707 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2084338 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1041631 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 1042707 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2084338 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1041631 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 1042707 # number of overall misses -system.cpu0.icache.overall_misses::total 2084338 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14123286486 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14169720487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28293006973 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14123286486 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 14169720487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28293006973 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14123286486 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 14169720487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28293006973 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 19930334 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 20860347 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 40790681 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 19930334 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 20860347 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 40790681 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 19930334 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 20860347 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 40790681 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.052264 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.049985 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.051098 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.052264 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.049985 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.051098 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.052264 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.049985 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.051098 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13558.819281 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13589.359702 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13574.097374 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13558.819281 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13589.359702 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13574.097374 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13558.819281 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13589.359702 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13574.097374 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 11799 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 615 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.185366 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1935798 # number of writebacks -system.cpu0.icache.writebacks::total 1935798 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 72135 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 75777 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 147912 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 72135 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 75777 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 147912 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 72135 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 75777 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 147912 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 969496 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 966930 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1936426 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 969496 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 966930 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1936426 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 969496 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 966930 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1936426 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 667 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 667 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 667 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 667 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12493413990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12512123492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 25005537482 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12493413990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12512123492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 25005537482 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12493413990 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12512123492 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 25005537482 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 53482500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 53482500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 53482500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 53482500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.048644 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046353 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047472 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.048644 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046353 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047472 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.048644 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046353 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047472 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12886.503905 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12940.050978 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12913.241963 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12886.503905 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12940.050978 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12913.241963 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12886.503905 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12940.050978 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12913.241963 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 80183.658171 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 80183.658171 # average overall mshr uncacheable latency -system.cpu1.branchPred.lookups 27768467 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14444745 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 516645 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 16732156 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 8530484 # Number of BTB hits -system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 50.982575 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6847641 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 29585 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4618056 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 4506231 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 111825 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 32588 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 59138 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 59138 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19056 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14153 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 25929 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 33209 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 492.833268 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3043.837220 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-8191 32423 97.63% 97.63% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-16383 540 1.63% 99.26% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-24575 149 0.45% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-32767 52 0.16% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-40959 16 0.05% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-49151 18 0.05% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-57343 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-73727 5 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 33209 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 12964 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10951.828139 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9214.622989 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6533.603209 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 4889 37.71% 37.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 6655 51.33% 89.05% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1022 7.88% 96.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 238 1.84% 98.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 117 0.90% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 38 0.29% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 2 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 12964 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 90072330428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.721128 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.470247 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 89999642928 99.92% 99.92% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 51122000 0.06% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 10756000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 3956500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 2349000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 1202000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 700500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 1277500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 267000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 187000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 117000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 117500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-25 238000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::26-27 36000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-29 19500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::30-31 342000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 90072330428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3730 69.60% 69.60% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1629 30.40% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5359 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 59138 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 59138 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5359 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5359 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 64497 # Table walker requests started/completed, data/inst -system.cpu1.dtb.inst_hits 0 # ITB inst hits -system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14518023 # DTB read hits -system.cpu1.dtb.read_misses 50239 # DTB read misses -system.cpu1.dtb.write_hits 10641437 # DTB write hits -system.cpu1.dtb.write_misses 8899 # DTB write misses -system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3373 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 787 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1128 # Number of TLB faults due to prefetch -system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 610 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14568262 # DTB read accesses -system.cpu1.dtb.write_accesses 10650336 # DTB write accesses -system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25159460 # DTB hits -system.cpu1.dtb.misses 59138 # DTB misses -system.cpu1.dtb.accesses 25218598 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 7663 # Table walker walks requested -system.cpu1.itb.walker.walksShort 7663 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2322 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4510 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 831 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6832 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 994.072014 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 4194.954654 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-8191 6528 95.55% 95.55% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-16383 212 3.10% 98.65% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-24575 44 0.64% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-32767 27 0.40% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-40959 9 0.13% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::40960-49151 4 0.06% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-57343 5 0.07% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6832 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 3180 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10355.188679 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8393.071987 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7092.645451 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 28 0.88% 0.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 1663 52.30% 53.18% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 542 17.04% 70.22% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 404 12.70% 82.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 34 1.07% 83.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 470 14.78% 98.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 0.47% 99.25% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.22% 99.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 6 0.19% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.09% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 5 0.16% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 3 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 3180 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 25646768488 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.764516 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.424553 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 6041654948 23.56% 23.56% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 19603312040 76.44% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 1413500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 335000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 53000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 25646768488 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1773 75.48% 75.48% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 576 24.52% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2349 # Table walker page sizes translated -system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7663 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7663 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2349 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2349 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 10012 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 20862819 # ITB inst hits -system.cpu1.itb.inst_misses 7663 # ITB inst misses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2217 # Number of entries that have been flushed from TLB -system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1301 # Number of TLB faults due to permissions restrictions -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20870482 # ITB inst accesses -system.cpu1.itb.hits 20862819 # DTB hits -system.cpu1.itb.misses 7663 # DTB misses -system.cpu1.itb.accesses 20870482 # DTB accesses -system.cpu1.numPwrStateTransitions 2936 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 1468 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 829956972.596730 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 15801466276.187872 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1432 97.55% 97.55% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 33 2.25% 99.80% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.07% 99.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.07% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 499953982692 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 1468 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 1586115355228 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218376835772 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 109612747 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40790032 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 108316651 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27768467 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19884356 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 64224291 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3206570 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 101756 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 7200 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 365 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 143510 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 122842 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 226 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20860348 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 361284 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3826 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 106993471 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.215539 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.315939 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 77281815 72.23% 72.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3963095 3.70% 75.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2488318 2.33% 78.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8243119 7.70% 85.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1612889 1.51% 87.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1184021 1.11% 88.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6282411 5.87% 94.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1182908 1.11% 95.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4754895 4.44% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 106993471 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.253332 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.988176 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27827531 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 60076040 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15861302 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1770624 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1457723 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1995842 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 147467 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 90138607 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 489536 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1457723 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28780463 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 5201978 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 47127740 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16672085 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 7753197 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 86299553 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2624 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1735423 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 210199 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 5005527 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 89489706 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 397397955 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 96183965 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6079 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 76183985 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13305705 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1606232 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1504962 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10217330 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15336831 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11768795 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2172366 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2803589 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 83184481 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1153102 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 79902588 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 90974 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10871346 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24449389 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 102910 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 106993471 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.746799 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.430875 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 74936839 70.04% 70.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10763085 10.06% 80.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8157485 7.62% 87.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6811202 6.37% 94.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2499268 2.34% 96.42% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1551620 1.45% 97.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1531718 1.43% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 492585 0.46% 99.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 249669 0.23% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 106993471 # Number of insts issued each cycle -system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 113986 9.89% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 7 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 526393 45.65% 55.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 512676 44.46% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 151 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 53671519 67.17% 67.17% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59014 0.07% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 3 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4219 0.01% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14905160 18.65% 85.90% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11262520 14.10% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 79902588 # Type of FU issued -system.cpu1.iq.rate 0.728953 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1153062 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014431 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 268029337 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 95251361 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 77606677 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 13346 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7483 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5728 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 81048267 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7232 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 350880 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2084815 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2040 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 50958 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1010162 # Number of stores squashed -system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 192812 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 110845 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1457723 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4213427 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 739361 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 84450588 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 107924 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15336831 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11768795 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 583687 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 43916 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 682784 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 50958 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 221001 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 225315 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 446316 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 79342272 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14681206 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 501344 # Number of squashed instructions skipped in execute -system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 113005 # number of nop insts executed -system.cpu1.iew.exec_refs 25846099 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14786732 # Number of branches executed -system.cpu1.iew.exec_stores 11164893 # Number of stores executed -system.cpu1.iew.exec_rate 0.723842 # Inst execution rate -system.cpu1.iew.wb_sent 78781509 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 77612405 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 40957824 # num instructions producing a value -system.cpu1.iew.wb_consumers 71653116 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.708060 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.571613 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 10899776 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1050192 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 371047 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 104491444 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.703761 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.593714 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 75982461 72.72% 72.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12681627 12.14% 84.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6552474 6.27% 91.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2740841 2.62% 93.75% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1432894 1.37% 95.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 937550 0.90% 96.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1880638 1.80% 97.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 438919 0.42% 98.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1844040 1.76% 100.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 104491444 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 60792609 # Number of instructions committed -system.cpu1.commit.committedOps 73537005 # Number of ops (including micro ops) committed -system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 24010649 # Number of memory references committed -system.cpu1.commit.loads 13252016 # Number of loads committed -system.cpu1.commit.membars 434207 # Number of memory barriers committed -system.cpu1.commit.branches 14055285 # Number of branches committed -system.cpu1.commit.fp_insts 5347 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 64446138 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2722289 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 49464791 67.27% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57349 0.08% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4216 0.01% 67.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.35% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 13252016 18.02% 85.37% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10758633 14.63% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 73537005 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1844040 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 174349530 # The number of ROB reads -system.cpu1.rob.rob_writes 171375071 # The number of ROB writes -system.cpu1.timesIdled 393969 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2619276 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2436753643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 60721837 # Number of Instructions Simulated -system.cpu1.committedOps 73466233 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.805162 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.805162 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.553967 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.553967 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 86273419 # number of integer regfile reads -system.cpu1.int_regfile_writes 49465455 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16586 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13020 # number of floating regfile writes -system.cpu1.cc_regfile_reads 280148251 # number of cc regfile reads -system.cpu1.cc_regfile_writes 29662918 # number of cc regfile writes -system.cpu1.misc_regfile_reads 196736132 # number of misc regfile reads -system.cpu1.misc_regfile_writes 795813 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30198 # Transaction distribution -system.iobus.trans_dist::ReadResp 30198 # Transaction distribution -system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 59014 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 49487000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 335000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 12500 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 87500 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 619500 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6425500 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38207500 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187822672 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36409 # number of replacements -system.iocache.tags.tagsinuse 0.981311 # Cycle average of tags in use -system.iocache.tags.total_refs 30 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 234301648000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.981311 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.061332 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.061332 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328227 # Number of tag accesses -system.iocache.tags.data_accesses 328227 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits -system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits -system.iocache.demand_hits::realview.ide 29 # number of demand (read+write) hits -system.iocache.demand_hits::total 29 # number of demand (read+write) hits -system.iocache.overall_hits::realview.ide 29 # number of overall hits -system.iocache.overall_hits::total 29 # number of overall hits -system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses -system.iocache.ReadReq_misses::total 249 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36444 # number of demand (read+write) misses -system.iocache.demand_misses::total 36444 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36444 # number of overall misses -system.iocache.overall_misses::total 36444 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31226877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31226877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4279492795 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4279492795 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4310719672 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4310719672 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4310719672 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4310719672 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36473 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36473 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36473 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36473 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ide 0.999205 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 0.999205 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 0.999205 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 0.999205 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 125409.144578 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125409.144578 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118234.363724 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118234.363724 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118283.384700 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118283.384700 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118283.384700 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118283.384700 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36160 # number of writebacks -system.iocache.writebacks::total 36160 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 36195 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 36195 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36444 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36444 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36444 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36444 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18776877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18776877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2467614128 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2467614128 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2486391005 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2486391005 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2486391005 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2486391005 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.999205 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.999205 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.999205 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.999205 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75409.144578 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75409.144578 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68175.552645 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68175.552645 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68224.975442 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68224.975442 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68224.975442 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68224.975442 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 104452 # number of replacements -system.l2c.tags.tagsinuse 65213.501449 # Cycle average of tags in use -system.l2c.tags.total_refs 5432730 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169859 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 31.983763 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 79304011000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::cpu0.dtb.walker 47.675626 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999974 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4819.813719 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 29687.680351 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 45.444052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5864.770891 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 24747.116836 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000727 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073545 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.452998 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000693 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.089489 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.377611 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995079 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65326 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 81 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7443 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 57733 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.001236 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.996796 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45059004 # Number of tag accesses -system.l2c.tags.data_accesses 45059004 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 34072 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5784 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 34667 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5734 # number of ReadReq hits -system.l2c.ReadReq_hits::total 80257 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 702238 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 702238 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1896138 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1896138 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 1486 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1347 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2833 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 83730 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 74268 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 157998 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 959179 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 956058 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1915237 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 263950 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 275779 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 539729 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 34072 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5784 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 959179 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 347680 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 34667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5734 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 956058 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 350047 # number of demand (read+write) hits -system.l2c.demand_hits::total 2693221 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 34072 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5784 # number of overall hits -system.l2c.overall_hits::cpu0.inst 959179 # number of overall hits -system.l2c.overall_hits::cpu0.data 347680 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 34667 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5734 # number of overall hits -system.l2c.overall_hits::cpu1.inst 956058 # number of overall hits -system.l2c.overall_hits::cpu1.data 350047 # number of overall hits -system.l2c.overall_hits::total 2693221 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 63 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 67 # number of ReadReq misses -system.l2c.ReadReq_misses::total 131 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 70652 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 67960 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 138612 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 10133 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 10722 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 20855 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 7109 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 8186 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 15295 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 63 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10133 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 77761 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 67 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 10722 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 76146 # number of demand (read+write) misses -system.l2c.demand_misses::total 174893 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 63 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10133 # number of overall misses -system.l2c.overall_misses::cpu0.data 77761 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 67 # number of overall misses -system.l2c.overall_misses::cpu1.inst 10722 # number of overall misses -system.l2c.overall_misses::cpu1.data 76146 # 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number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 789414500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5699798500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 13091660998 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 4789500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 73500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 739815498 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 5852767500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 5002000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 789414500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5699798500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 13091660998 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 43103498 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3097371000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2817626000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5958100498 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 43103498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3097371000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2817626000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5958100498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001846 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000173 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001929 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.001630 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002685 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.002961 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.002816 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.025641 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.032258 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.028571 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.457644 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.477824 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.467321 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010447 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011086 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010766 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.025946 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.028599 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027303 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001846 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000173 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010447 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.182599 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001929 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011086 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.178513 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.060925 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001846 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000173 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010447 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.182599 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001929 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011086 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.178513 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.060925 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76023.809524 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74656.716418 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 75305.343511 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19250 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19250 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19250 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 70500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 72000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71250 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75191.303856 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74351.449382 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 74779.532075 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 73060.981434 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73653.153573 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73365.476780 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76830.868762 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79654.476050 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78344.034578 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76023.809524 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73060.981434 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75339.737401 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74656.716418 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73653.153573 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74917.502399 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 74920.373570 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76023.809524 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73060.981434 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75339.737401 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74656.716418 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73653.153573 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74917.502399 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 74920.373570 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189662.053763 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190431.603136 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187397.008807 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96012.740236 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106522.475521 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 100341.885850 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 352067 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 145781 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 504 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 31794 # Transaction distribution -system.membus.trans_dist::ReadResp 68171 # Transaction distribution -system.membus.trans_dist::WriteReq 27584 # Transaction distribution -system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 131672 # Transaction distribution -system.membus.trans_dist::CleanEvict 9189 # Transaction distribution -system.membus.trans_dist::UpgradeReq 129 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 138492 # Transaction distribution -system.membus.trans_dist::ReadExResp 138492 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36378 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 24 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464721 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 572293 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645161 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17331868 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17495901 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19811101 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 522 # Total snoops (count) -system.membus.snoopTraffic 33280 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 270575 # Request fanout histogram -system.membus.snoop_fanout::mean 0.019532 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.138387 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 265290 98.05% 98.05% # Request fanout histogram -system.membus.snoop_fanout::1 5285 1.95% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 270575 # Request fanout histogram -system.membus.reqLayer0.occupancy 95437500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 18156 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1702998 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 917027178 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1009264500 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1323623 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks -system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks -system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks -system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks -system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks -system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks -system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks -system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5615366 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2827339 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 47526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 188 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 188 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 149674 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2641289 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 797750 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1935798 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 157804 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2842 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 70 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2911 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296610 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296610 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1936426 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 555260 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4760 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5809649 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2677780 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 34247 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 164021 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8685697 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247843584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99641501 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 46076 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 275476 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 347806637 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 147441 # Total snoops (count) -system.toL2Bus.snoopTraffic 6294736 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 3081797 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.027693 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.164091 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2996454 97.23% 97.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 85343 2.77% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3081797 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5533506883 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 309877 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2907318131 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1324202245 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 22762929 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 95604083 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed - ----------- End Simulation Statistics ---------- |