diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
| commit | cb9e208a4c1b564556275d9b6ee0257da4208a88 (patch) | |
| tree | 6d1e5d4393ae0758da69261a11c37374c2a47a88 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | |
| parent | 0facc8e1acb9b5261ac49f87ca489ba823c8e9f3 (diff) | |
| download | gem5-cb9e208a4c1b564556275d9b6ee0257da4208a88.tar.xz | |
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | 2709 |
1 files changed, 1347 insertions, 1362 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 1af17ec8e..73a40b4c9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,162 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.542296 # Number of seconds simulated -sim_ticks 2542295570500 # Number of ticks simulated -final_tick 2542295570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.541289 # Number of seconds simulated +sim_ticks 2541288973500 # Number of ticks simulated +final_tick 2541288973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70655 # Simulator instruction rate (inst/s) -host_op_rate 90914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2978397497 # Simulator tick rate (ticks/s) -host_mem_usage 409668 # Number of bytes of host memory used -host_seconds 853.58 # Real time elapsed on the host -sim_insts 60309877 # Number of instructions simulated -sim_ops 77602149 # Number of ops (including micro ops) simulated +host_inst_rate 61532 # Simulator instruction rate (inst/s) +host_op_rate 79175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2592785663 # Simulator tick rate (ticks/s) +host_mem_usage 411940 # Number of bytes of host memory used +host_seconds 980.14 # Real time elapsed on the host +sim_insts 60309889 # Number of instructions simulated +sim_ops 77602313 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 504448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4169680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 296128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4925148 # Number of bytes read from this memory -system.physmem.bytes_read::total 131008300 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 504448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 296128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3787072 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1346312 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1669800 # Number of bytes written to this memory -system.physmem.bytes_written::total 6803184 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 501184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4156432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 298496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4937244 # Number of bytes read from this memory +system.physmem.bytes_read::total 131006380 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 501184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 298496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784960 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1345340 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1670772 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801072 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 65185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4627 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 76962 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293509 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59173 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336578 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417450 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813201 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47638256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7831 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 64978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4664 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77151 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293479 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59140 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 336335 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 417693 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813168 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47657126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 630 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 198422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1640124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 116481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1937284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51531498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 198422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 116481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489627 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 529565 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 656808 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2676000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47638256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 197216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1635561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 117459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1942811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51551154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 197216 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 117459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314675 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489386 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529393 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 657451 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2676229 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47657126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 630 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 198422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2169689 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 116481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2594092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54207499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293509 # Total number of read requests seen -system.physmem.writeReqs 813201 # Total number of write requests seen -system.physmem.cpureqs 218507 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978784576 # Total number of bytes read from memory -system.physmem.bytesWritten 52044864 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131008300 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6803184 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955738 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955673 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956489 # Track reads on a per bank basis +system.physmem.bw_total::cpu0.inst 197216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2164953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 117459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2600262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54227384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293479 # Total number of read requests seen +system.physmem.writeReqs 813168 # Total number of write requests seen +system.physmem.cpureqs 218447 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978782656 # Total number of bytes read from memory +system.physmem.bytesWritten 52042752 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131006380 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6801072 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956234 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955730 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956486 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 956267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955445 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955564 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956162 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956093 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955563 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956167 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956088 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955526 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956035 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955984 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50833 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis +system.physmem.perBankRdReqs::12 956037 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955427 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955317 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955983 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50411 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50432 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 51159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50911 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50191 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50281 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50906 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50808 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51188 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51253 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50731 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50630 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50913 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50185 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50857 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50806 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51249 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50729 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51233 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1856479 # Number of times wr buffer was full causing retry -system.physmem.totGap 2542294418500 # Total gap between requests +system.physmem.numWrRetry 1856346 # Number of times wr buffer was full causing retry +system.physmem.totGap 2541287786000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154650 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2610507 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59173 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1054657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3604952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2700242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11014 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.readPktSize::6 154620 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 754028 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 59140 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1054883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 992061 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3604876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2698984 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 109990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109908 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -169,61 +156,59 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35370 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 32761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 346840685210 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 440008538960 # Sum of mem lat for all requests -system.physmem.totBusLat 76467475000 # Total cycles spent in databus access -system.physmem.totBankLat 16700378750 # Total cycles spent in bank access -system.physmem.avgQLat 22678.97 # Average queueing delay per request -system.physmem.avgBankLat 1091.99 # Average bank access latency per request +system.physmem.wrQLenPdf::24 32641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32476 # What write queue length does an incoming req see +system.physmem.totQLat 346721486500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 439895947750 # Sum of mem lat for all requests +system.physmem.totBusLat 76467345000 # Total cycles spent in databus access +system.physmem.totBankLat 16707116250 # Total cycles spent in bank access +system.physmem.avgQLat 22671.21 # Average queueing delay per request +system.physmem.avgBankLat 1092.43 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28770.96 # Average memory access latency -system.physmem.avgRdBW 385.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.47 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.53 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 28763.65 # Average memory access latency +system.physmem.avgRdBW 385.15 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.55 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.14 # Average write queue length over time -system.physmem.readRowHits 15218397 # Number of row buffer hits during reads -system.physmem.writeRowHits 794710 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.13 # Average write queue length over time +system.physmem.readRowHits 15218362 # Number of row buffer hits during reads +system.physmem.writeRowHits 794635 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.73 # Row buffer hit rate for writes -system.physmem.avgGap 157840.70 # Average gap between requests +system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes +system.physmem.avgGap 157778.82 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -236,225 +221,225 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64418 # number of replacements -system.l2c.tagsinuse 51401.261729 # Cycle average of tags in use -system.l2c.total_refs 1905310 # Total number of references to valid blocks. -system.l2c.sampled_refs 129810 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.677683 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2531415043500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36947.323889 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 9.916328 # Average occupied blocks per requestor +system.l2c.replacements 64388 # number of replacements +system.l2c.tagsinuse 51386.157207 # Cycle average of tags in use +system.l2c.total_refs 1906213 # Total number of references to valid blocks. +system.l2c.sampled_refs 129781 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.687920 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2505304860500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36943.345859 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 11.980136 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5145.662568 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3278.560293 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 13.240870 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3059.988680 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2946.568751 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563771 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000151 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 5122.722111 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3272.415541 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 10.482410 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3080.689127 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2944.521672 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563711 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000183 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078517 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.050027 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000202 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.046692 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044961 # 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number of Writeback hits +system.l2c.Writeback_hits::total 608382 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 20 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 57851 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 55061 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112912 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32856 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7561 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 491369 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 271567 # 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mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000618 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.195296 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.253934 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091573 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000760 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015557 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.195830 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000492 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009544 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.253417 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091642 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44601.319314 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46302.841888 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44663.031012 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10060.224093 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10032.380233 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39775.018281 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37292.993425 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38412.050085 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40217.548424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37825.820219 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39335.413644 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40217.548424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37825.820219 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39335.413644 # average overall mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.195296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.253934 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091573 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44235.683758 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45743.111981 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44273.292281 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10073.116484 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.874398 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39806.414207 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37287.888795 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38419.733648 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -637,38 +622,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7620138 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6076880 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 380507 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4965064 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4053585 # Number of BTB hits +system.cpu0.branchPred.lookups 7614306 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6072650 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 380012 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4955572 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4051897 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.642150 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 731859 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39538 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.764466 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 730604 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39458 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26058653 # DTB read hits -system.cpu0.dtb.read_misses 40101 # DTB read misses -system.cpu0.dtb.write_hits 5895373 # DTB write hits -system.cpu0.dtb.write_misses 9447 # DTB write misses +system.cpu0.dtb.read_hits 26054511 # DTB read hits +system.cpu0.dtb.read_misses 40169 # DTB read misses +system.cpu0.dtb.write_hits 5887052 # DTB write hits +system.cpu0.dtb.write_misses 9355 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5619 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1431 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 273 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5627 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1395 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26098754 # DTB read accesses -system.cpu0.dtb.write_accesses 5904820 # DTB write accesses +system.cpu0.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26094680 # DTB read accesses +system.cpu0.dtb.write_accesses 5896407 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31954026 # DTB hits -system.cpu0.dtb.misses 49548 # DTB misses -system.cpu0.dtb.accesses 32003574 # DTB accesses -system.cpu0.itb.inst_hits 6112115 # ITB inst hits -system.cpu0.itb.inst_misses 7637 # ITB inst misses +system.cpu0.dtb.hits 31941563 # DTB hits +system.cpu0.dtb.misses 49524 # DTB misses +system.cpu0.dtb.accesses 31991087 # DTB accesses +system.cpu0.itb.inst_hits 6108612 # ITB inst hits +system.cpu0.itb.inst_misses 7590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -677,149 +662,149 @@ system.cpu0.itb.flush_tlb 257 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2623 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1579 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1574 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6119752 # ITB inst accesses -system.cpu0.itb.hits 6112115 # DTB hits -system.cpu0.itb.misses 7637 # DTB misses -system.cpu0.itb.accesses 6119752 # DTB accesses -system.cpu0.numCycles 239063312 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6116202 # ITB inst accesses +system.cpu0.itb.hits 6108612 # DTB hits +system.cpu0.itb.misses 7590 # DTB misses +system.cpu0.itb.accesses 6116202 # DTB accesses +system.cpu0.numCycles 239083473 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15490963 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47835555 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7620138 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4785444 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10608217 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2561094 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 89115 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49527666 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1654 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1892 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 49952 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 101088 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 226 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6110008 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 396628 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3581 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77642580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.762278 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.119818 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15485568 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47808985 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7614306 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4782501 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10601732 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2558486 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 88790 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49524477 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1650 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2036 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 49879 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101149 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 238 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6106475 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 397023 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3536 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77625046 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.761902 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.119269 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67041875 86.35% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 689016 0.89% 87.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 885560 1.14% 88.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1228014 1.58% 89.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1141359 1.47% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 577108 0.74% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1324549 1.71% 93.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 398041 0.51% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4357058 5.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67030834 86.35% 86.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 688188 0.89% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 885369 1.14% 88.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1227712 1.58% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1142460 1.47% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 576598 0.74% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1323002 1.70% 93.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 397300 0.51% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4353583 5.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77642580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031875 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.200096 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16540886 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49255967 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9607571 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 552371 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1683667 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1024811 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90579 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56316085 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 302289 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1683667 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17475063 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18984775 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27019953 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9154130 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3322955 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53494037 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13484 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 621738 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2157353 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 548 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55660367 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 243519467 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243471355 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48112 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40417937 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15242430 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 429833 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 381699 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6758508 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10355148 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6782314 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1058612 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1316675 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49644359 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1043369 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63195717 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 96260 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10515144 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26542188 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 266673 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77642580 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.813931 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.519230 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77625046 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031848 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.199968 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16533020 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49254882 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9604301 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 549145 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1681530 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1023916 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90477 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56278023 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 301850 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1681530 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17466172 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18987810 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27019642 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9149380 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3318436 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53462165 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13485 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 622165 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2153440 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 547 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55626962 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 243359254 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 243311426 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 47828 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40393377 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15233585 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 429285 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 381212 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6745205 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10341737 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6773194 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1063883 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1311451 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49606690 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1043899 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63171257 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 95885 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10502922 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26495317 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 267486 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77625046 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.813800 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519198 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54792876 70.57% 70.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7218069 9.30% 79.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3694351 4.76% 84.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3145323 4.05% 88.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6277418 8.09% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1407401 1.81% 98.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 809465 1.04% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 231906 0.30% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 65771 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54791410 70.58% 70.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7205110 9.28% 79.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3690427 4.75% 84.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3148985 4.06% 88.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6276259 8.09% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1405987 1.81% 98.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 810578 1.04% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 230421 0.30% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 65869 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77642580 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77625046 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29563 0.66% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4229523 94.72% 95.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 206294 4.62% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29841 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4229016 94.75% 95.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 204408 4.58% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195578 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29951554 47.39% 47.70% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46938 0.07% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 195533 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29939610 47.39% 47.70% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46892 0.07% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued @@ -832,485 +817,485 @@ system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Ty system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1212 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1207 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26776565 42.37% 90.15% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6223855 9.85% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26772486 42.38% 90.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6215505 9.84% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63195717 # Type of FU issued -system.cpu0.iq.rate 0.264347 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4465384 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070660 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208632682 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61211746 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44166006 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12339 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6563 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5520 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67458994 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6529 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 322005 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63171257 # Type of FU issued +system.cpu0.iq.rate 0.264223 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4463267 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070653 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208563844 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61162491 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44139446 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12207 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6555 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5480 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67432539 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6452 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 322060 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2276398 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3543 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16033 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 889328 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2267012 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3473 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16117 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 886206 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17163737 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367898 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17168110 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367587 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1683667 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14223209 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 234272 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50804503 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105344 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10355148 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6782314 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 742198 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 56887 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3242 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16033 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 187141 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 147345 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 334486 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62025172 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26418520 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1170545 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1681530 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14225625 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 233605 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50767973 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 106118 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10341737 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6773194 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 742853 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56514 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3354 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16117 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186814 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 146956 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 333770 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62000418 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26414197 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1170839 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 116775 # number of nop insts executed -system.cpu0.iew.exec_refs 32585401 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6028949 # Number of branches executed -system.cpu0.iew.exec_stores 6166881 # Number of stores executed -system.cpu0.iew.exec_rate 0.259451 # Inst execution rate -system.cpu0.iew.wb_sent 61495183 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44171526 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24314220 # num instructions producing a value -system.cpu0.iew.wb_consumers 44686636 # num instructions consuming a value +system.cpu0.iew.exec_nop 117384 # number of nop insts executed +system.cpu0.iew.exec_refs 32572588 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6026978 # Number of branches executed +system.cpu0.iew.exec_stores 6158391 # Number of stores executed +system.cpu0.iew.exec_rate 0.259325 # Inst execution rate +system.cpu0.iew.wb_sent 61472286 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44144926 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24307807 # num instructions producing a value +system.cpu0.iew.wb_consumers 44674584 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184769 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544105 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184642 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544108 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10365934 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 776696 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 291216 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75958913 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.525792 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.508136 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10350620 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 776413 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 290797 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75943516 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.525572 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.508217 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61730922 81.27% 81.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6914068 9.10% 90.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2040925 2.69% 93.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1133695 1.49% 94.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1039727 1.37% 95.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 547660 0.72% 96.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 699909 0.92% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 371161 0.49% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1480846 1.95% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61731521 81.29% 81.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6903711 9.09% 90.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2039504 2.69% 93.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1132941 1.49% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1032773 1.36% 95.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 549051 0.72% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 702703 0.93% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 370837 0.49% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1480475 1.95% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75958913 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31284581 # Number of instructions committed -system.cpu0.commit.committedOps 39938560 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75943516 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31268406 # Number of instructions committed +system.cpu0.commit.committedOps 39913766 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13971736 # Number of memory references committed -system.cpu0.commit.loads 8078750 # Number of loads committed -system.cpu0.commit.membars 212403 # Number of memory barriers committed -system.cpu0.commit.branches 5205711 # Number of branches committed -system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35286774 # Number of committed integer instructions. -system.cpu0.commit.function_calls 514203 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1480846 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13961713 # Number of memory references committed +system.cpu0.commit.loads 8074725 # Number of loads committed +system.cpu0.commit.membars 212370 # Number of memory barriers committed +system.cpu0.commit.branches 5203416 # Number of branches committed +system.cpu0.commit.fp_insts 5433 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35263906 # Number of committed integer instructions. +system.cpu0.commit.function_calls 513958 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1480475 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123805555 # The number of ROB reads -system.cpu0.rob.rob_writes 102335061 # The number of ROB writes -system.cpu0.timesIdled 884089 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161420732 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289699870 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31205252 # Number of Instructions Simulated -system.cpu0.committedOps 39859231 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31205252 # Number of Instructions Simulated -system.cpu0.cpi 7.660996 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.660996 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130531 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130531 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 280760557 # number of integer regfile reads -system.cpu0.int_regfile_writes 45445732 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22770 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19806 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15502985 # number of misc regfile reads -system.cpu0.misc_regfile_writes 430013 # number of misc regfile writes -system.cpu0.icache.replacements 984427 # number of replacements -system.cpu0.icache.tagsinuse 510.429233 # Cycle average of tags in use -system.cpu0.icache.total_refs 11039860 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984939 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.208674 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 123750130 # The number of ROB reads +system.cpu0.rob.rob_writes 102252787 # The number of ROB writes +system.cpu0.timesIdled 884124 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161458427 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289647904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31189179 # Number of Instructions Simulated +system.cpu0.committedOps 39834539 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31189179 # Number of Instructions Simulated +system.cpu0.cpi 7.665590 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.665590 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.130453 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.130453 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 280633966 # number of integer regfile reads +system.cpu0.int_regfile_writes 45420954 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22760 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19830 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15480243 # number of misc regfile reads +system.cpu0.misc_regfile_writes 429707 # number of misc regfile writes +system.cpu0.icache.replacements 984233 # number of replacements +system.cpu0.icache.tagsinuse 511.604349 # Cycle average of tags in use +system.cpu0.icache.total_refs 11036411 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984745 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.207380 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 356.685952 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 153.743281 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.696652 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.300280 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996932 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5569328 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5470532 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11039860 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5569328 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5470532 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11039860 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5569328 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5470532 # number of overall hits -system.cpu0.icache.overall_hits::total 11039860 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 540556 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 524651 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065207 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 540556 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 524651 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065207 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 540556 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 524651 # number of overall misses -system.cpu0.icache.overall_misses::total 1065207 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7319258495 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6971682996 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14290941491 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7319258495 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6971682996 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14290941491 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7319258495 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6971682996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14290941491 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6109884 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5995183 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12105067 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6109884 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5995183 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12105067 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6109884 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5995183 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12105067 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088472 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087512 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.087997 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088472 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087512 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.087997 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088472 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087512 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.087997 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13540.240965 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13288.229692 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13416.116765 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13540.240965 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13288.229692 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13416.116765 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13540.240965 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13288.229692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13416.116765 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4720 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 356.507188 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 155.097161 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.696303 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.302924 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5565457 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5470954 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11036411 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5565457 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5470954 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11036411 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5565457 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5470954 # number of overall hits +system.cpu0.icache.overall_hits::total 11036411 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 540893 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 524443 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1065336 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 540893 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 524443 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1065336 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 540893 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 524443 # number of overall misses +system.cpu0.icache.overall_misses::total 1065336 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7322738992 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6974356493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14297095485 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7322738992 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6974356493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14297095485 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7322738992 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6974356493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14297095485 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6106350 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5995397 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12101747 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6106350 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5995397 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12101747 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6106350 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5995397 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12101747 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088579 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087474 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.088032 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088579 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087474 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.088032 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088579 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087474 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.088032 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13538.239526 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13298.597737 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13420.268803 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13538.239526 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13298.597737 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13420.268803 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13538.239526 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13298.597737 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13420.268803 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4718 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 314 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 353 # 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number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 40959 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39286 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80245 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 499597 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 485365 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984962 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 499597 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 485365 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984962 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 499597 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 485365 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11655300986 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5972321992 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5682978994 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11655300986 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7526000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7526000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7526000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7526000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081769 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080959 # 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number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 95497500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 187671000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 52000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 78000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 130000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 59076617864 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 66694838284 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125771456148 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 59076617864 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 66694838284 # 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miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.269093 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.310622 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289658 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051437 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054518 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052929 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000031 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000050 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143514 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.156742 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149950 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143514 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.156742 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149950 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14845.692761 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15427.048074 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15089.927526 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37885.320653 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39319.924972 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38647.128005 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13507.253810 # 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number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635214 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 332938 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 302276 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635214 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2899504500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2321074000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5220578500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3969032491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4493255436 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8462287927 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71687000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73644500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145331500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 55000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 99000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6868536991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6814329436 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13682866427 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6868536991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6814329436 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13682866427 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91958825500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90402409000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182361234500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14888911816 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18625662995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33514574811 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106817962785 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109053072802 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215871035587 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028309 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024707 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026578 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023125 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025599 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024350 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046319 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048895 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047566 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000031 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025082 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025658 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025082 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025658 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13582.422955 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13458.024913 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13526.861580 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33327.834932 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34600.143019 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33990.171362 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.605370 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12310.826351 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11986.183780 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106847737316 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109028071995 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215875809311 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028335 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024693 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026584 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023129 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025606 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046337 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048841 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047549 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000039 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000033 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000036 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025664 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025664 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13567.853199 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13454.175531 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13517.075716 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33287.757611 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34627.697778 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33986.047507 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.009112 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12118.561790 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11890.002454 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20657.035268 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22526.720797 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21546.289839 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20657.035268 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22526.720797 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21546.289839 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1325,38 +1310,38 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7047379 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5653088 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 345044 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4644809 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3819502 # Number of BTB hits +system.cpu1.branchPred.lookups 7038093 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5643597 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 344397 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4629014 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3810883 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 82.231627 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 672042 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34964 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 82.326020 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 671158 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34749 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25308350 # DTB read hits -system.cpu1.dtb.read_misses 36279 # DTB read misses -system.cpu1.dtb.write_hits 5820677 # DTB write hits -system.cpu1.dtb.write_misses 9386 # DTB write misses +system.cpu1.dtb.read_hits 25308103 # DTB read hits +system.cpu1.dtb.read_misses 36468 # DTB read misses +system.cpu1.dtb.write_hits 5825949 # DTB write hits +system.cpu1.dtb.write_misses 9352 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5518 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1305 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 250 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1257 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 236 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25344629 # DTB read accesses -system.cpu1.dtb.write_accesses 5830063 # DTB write accesses +system.cpu1.dtb.perms_faults 652 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25344571 # DTB read accesses +system.cpu1.dtb.write_accesses 5835301 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31129027 # DTB hits -system.cpu1.dtb.misses 45665 # DTB misses -system.cpu1.dtb.accesses 31174692 # DTB accesses -system.cpu1.itb.inst_hits 5997294 # ITB inst hits -system.cpu1.itb.inst_misses 6928 # ITB inst misses +system.cpu1.dtb.hits 31134052 # DTB hits +system.cpu1.dtb.misses 45820 # DTB misses +system.cpu1.dtb.accesses 31179872 # DTB accesses +system.cpu1.itb.inst_hits 5997509 # ITB inst hits +system.cpu1.itb.inst_misses 6989 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1365,284 +1350,284 @@ system.cpu1.itb.flush_tlb 254 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2607 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2597 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1435 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6004222 # ITB inst accesses -system.cpu1.itb.hits 5997294 # DTB hits -system.cpu1.itb.misses 6928 # DTB misses -system.cpu1.itb.accesses 6004222 # DTB accesses -system.cpu1.numCycles 234192897 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6004498 # ITB inst accesses +system.cpu1.itb.hits 5997509 # DTB hits +system.cpu1.itb.misses 6989 # DTB misses +system.cpu1.itb.accesses 6004498 # DTB accesses +system.cpu1.numCycles 234155519 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15145693 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46615728 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7047379 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4491544 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10277592 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2615595 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 81100 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47506260 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2050 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 43629 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 94802 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5995185 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 443145 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3161 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74942742 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.773391 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.139188 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15142136 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46597306 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7038093 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4482041 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10279188 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2613913 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 81086 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47501023 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2061 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 42896 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94668 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 141 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5995399 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 442650 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3270 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74933804 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.773237 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.138568 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64672921 86.30% 86.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 620255 0.83% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 831184 1.11% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1205105 1.61% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1036791 1.38% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 535666 0.71% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1369144 1.83% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 351637 0.47% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4320039 5.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64662280 86.29% 86.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 620375 0.83% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 831799 1.11% 88.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1204715 1.61% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1045196 1.39% 91.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 534648 0.71% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1368616 1.83% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 351624 0.47% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4314551 5.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74942742 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030092 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199048 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16159158 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47296340 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9320957 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 457304 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1706877 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 946060 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86144 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54858013 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286862 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1706877 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17095317 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18544880 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25731919 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8763106 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3098607 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51692102 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7152 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 482288 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2118635 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 58 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53768769 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237295359 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 237252975 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42384 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 37974901 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15793867 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 403461 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 357400 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6244351 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9843526 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6693253 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 891235 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1110531 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47673025 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 943085 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60813772 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 81704 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10584682 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 28040387 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 237278 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74942742 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.811470 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521589 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74933804 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030057 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.199002 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16155094 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47289878 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9321974 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 458622 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1706108 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 946431 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86032 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54867135 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286067 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1706108 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17091509 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18549403 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25716073 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8765190 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3103459 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51703267 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7138 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 482463 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2122538 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 91 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53752733 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237374868 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 237332026 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42842 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 37999603 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15753129 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 403463 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 357307 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6254395 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9847442 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6700780 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 890369 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1126759 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47663057 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 942444 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60816475 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 81421 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10551432 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27971257 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 236318 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74933804 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.811603 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521433 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53203952 70.99% 70.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6663470 8.89% 79.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3519082 4.70% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2892768 3.86% 88.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6218608 8.30% 96.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1439258 1.92% 98.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 735883 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 209954 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59767 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53188932 70.98% 70.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6663266 8.89% 79.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3530113 4.71% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2889463 3.86% 88.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6218055 8.30% 96.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1440706 1.92% 98.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 733706 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 209896 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59667 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74942742 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74933804 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24319 0.56% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4142702 94.84% 95.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 201068 4.60% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24001 0.55% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4142238 94.88% 95.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 199692 4.57% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 168088 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28444166 46.77% 47.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46611 0.08% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 900 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26040619 42.82% 89.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6113365 10.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 168133 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28440656 46.76% 47.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46730 0.08% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 904 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26040768 42.82% 89.94% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6119264 10.06% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60813772 # Type of FU issued -system.cpu1.iq.rate 0.259674 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4368089 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071827 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 201054983 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59209073 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41787342 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10574 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5911 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4752 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65008196 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5577 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 302847 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60816475 # Type of FU issued +system.cpu1.iq.rate 0.259727 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4365932 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.071789 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 201049061 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59165079 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41785793 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10680 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5951 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65008639 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5635 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 303573 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2267035 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3168 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14674 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 853664 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2266828 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3041 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14605 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 855166 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16940133 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 457083 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16935844 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 457097 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1706877 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13961840 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229523 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48721689 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98782 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9843526 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6693253 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 669936 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49642 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3791 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14674 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 166878 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133542 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 300420 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59454145 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25635874 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1359627 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1706108 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 13962333 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 229984 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48711452 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98533 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9847442 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6700780 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 669329 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49837 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3707 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14605 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 166001 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133612 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 299613 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59448141 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25635797 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1368334 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105579 # number of nop insts executed -system.cpu1.iew.exec_refs 31697240 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5530994 # Number of branches executed -system.cpu1.iew.exec_stores 6061366 # Number of stores executed -system.cpu1.iew.exec_rate 0.253868 # Inst execution rate -system.cpu1.iew.wb_sent 58875000 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41792094 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22753184 # num instructions producing a value -system.cpu1.iew.wb_consumers 41716740 # num instructions consuming a value +system.cpu1.iew.exec_nop 105951 # number of nop insts executed +system.cpu1.iew.exec_refs 31702689 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5524822 # Number of branches executed +system.cpu1.iew.exec_stores 6066892 # Number of stores executed +system.cpu1.iew.exec_rate 0.253883 # Inst execution rate +system.cpu1.iew.wb_sent 58868959 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41790607 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22765083 # num instructions producing a value +system.cpu1.iew.wb_consumers 41748877 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178452 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545421 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178474 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.545286 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10509796 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 705807 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260176 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73235865 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.516331 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.496791 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10475750 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 706126 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 259614 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73227696 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.516730 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.497193 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59723279 81.55% 81.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6657456 9.09% 90.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1906988 2.60% 93.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1010218 1.38% 94.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 959564 1.31% 95.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 524950 0.72% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 702340 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 373722 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1377348 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59700930 81.53% 81.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6668134 9.11% 90.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1908648 2.61% 93.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1011673 1.38% 94.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 958934 1.31% 95.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 524760 0.72% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 701730 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 374533 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1378354 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73235865 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29175677 # Number of instructions committed -system.cpu1.commit.committedOps 37813970 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73227696 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29191864 # Number of instructions committed +system.cpu1.commit.committedOps 37838928 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13416080 # Number of memory references committed -system.cpu1.commit.loads 7576491 # Number of loads committed -system.cpu1.commit.membars 191234 # Number of memory barriers committed -system.cpu1.commit.branches 4755917 # Number of branches committed -system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33570741 # Number of committed integer instructions. -system.cpu1.commit.function_calls 477112 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1377348 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13426228 # Number of memory references committed +system.cpu1.commit.loads 7580614 # Number of loads committed +system.cpu1.commit.membars 191280 # Number of memory barriers committed +system.cpu1.commit.branches 4758264 # Number of branches committed +system.cpu1.commit.fp_insts 4779 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33593707 # Number of committed integer instructions. +system.cpu1.commit.function_calls 477362 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1378354 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119309924 # The number of ROB reads -system.cpu1.rob.rob_writes 98406667 # The number of ROB writes -system.cpu1.timesIdled 873323 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159250155 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285809379 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29104625 # Number of Instructions Simulated -system.cpu1.committedOps 37742918 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29104625 # Number of Instructions Simulated -system.cpu1.cpi 8.046587 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.046587 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124276 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124276 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 269354983 # number of integer regfile reads -system.cpu1.int_regfile_writes 42881539 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22070 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19722 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14807942 # number of misc regfile reads -system.cpu1.misc_regfile_writes 402452 # number of misc regfile writes +system.cpu1.rob.rob_reads 119292034 # The number of ROB reads +system.cpu1.rob.rob_writes 98387822 # The number of ROB writes +system.cpu1.timesIdled 873010 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159221715 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285865988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29120710 # Number of Instructions Simulated +system.cpu1.committedOps 37767774 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29120710 # Number of Instructions Simulated +system.cpu1.cpi 8.040859 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.040859 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124365 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124365 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 269346342 # number of integer regfile reads +system.cpu1.int_regfile_writes 42878504 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22102 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14810651 # number of misc regfile reads +system.cpu1.misc_regfile_writes 402789 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1657,17 +1642,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192818443837 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192818443837 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192717579972 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192717579972 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83054 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83049 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |