diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3 | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | 3339 |
1 files changed, 1667 insertions, 1672 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 4b7f3d43e..055919fe9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,154 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.550237 # Number of seconds simulated -sim_ticks 2550237191000 # Number of ticks simulated -final_tick 2550237191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.539697 # Number of seconds simulated +sim_ticks 2539696838000 # Number of ticks simulated +final_tick 2539696838000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66377 # Simulator instruction rate (inst/s) -host_op_rate 85409 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2806608319 # Simulator tick rate (ticks/s) -host_mem_usage 421988 # Number of bytes of host memory used -host_seconds 908.65 # Real time elapsed on the host -sim_insts 60314055 # Number of instructions simulated -sim_ops 77607027 # Number of ops (including micro ops) simulated +host_inst_rate 33216 # Simulator instruction rate (inst/s) +host_op_rate 40018 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1398403355 # Simulator tick rate (ticks/s) +host_mem_usage 411672 # Number of bytes of host memory used +host_seconds 1816.14 # Real time elapsed on the host +sim_insts 60325607 # Number of instructions simulated +sim_ops 72677421 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 507520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5298200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 292352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3795584 # Number of bytes read from this memory -system.physmem.bytes_read::total 131007192 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 507520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 292352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786240 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521400 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494672 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802312 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 469568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3933400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 314240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5155776 # Number of bytes read from this memory +system.physmem.bytes_read::total 130985112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 469568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 314240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 783808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3774400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1328880 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1687192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6790472 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 35 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7930 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 82820 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4568 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 59306 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293487 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59160 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380350 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373668 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813178 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47489907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 878 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 61485 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 80559 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293132 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58975 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 332220 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 421798 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812993 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47687002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 353 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 199009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2077532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 114637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1488326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51370591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 199009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 114637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596572 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586091 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2667325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47489907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 184891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1548768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 123731 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2030075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51575097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 184891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 123731 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 308623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1486162 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 523244 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 664328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2673733 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1486162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47687002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 353 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 199009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2674104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 114637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2074417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54037916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293487 # Number of read requests accepted -system.physmem.writeReqs 813178 # Number of write requests accepted -system.physmem.readBursts 15293487 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813178 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 977052352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1730816 # Total number of bytes read from write queue -system.physmem.bytesWritten 6829312 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131007192 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6802312 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 27044 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706441 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4687 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955866 # Per bank write bursts -system.physmem.perBankRdBursts::1 953274 # Per bank write bursts -system.physmem.perBankRdBursts::2 953247 # Per bank write bursts -system.physmem.perBankRdBursts::3 953514 # Per bank write bursts -system.physmem.perBankRdBursts::4 955750 # Per bank write bursts -system.physmem.perBankRdBursts::5 953800 # Per bank write bursts -system.physmem.perBankRdBursts::6 953588 # Per bank write bursts -system.physmem.perBankRdBursts::7 953504 # Per bank write bursts -system.physmem.perBankRdBursts::8 956261 # Per bank write bursts -system.physmem.perBankRdBursts::9 953859 # Per bank write bursts -system.physmem.perBankRdBursts::10 953506 # Per bank write bursts -system.physmem.perBankRdBursts::11 952990 # Per bank write bursts -system.physmem.perBankRdBursts::12 956201 # Per bank write bursts -system.physmem.perBankRdBursts::13 953861 # Per bank write bursts -system.physmem.perBankRdBursts::14 953718 # Per bank write bursts -system.physmem.perBankRdBursts::15 953504 # Per bank write bursts -system.physmem.perBankWrBursts::0 6593 # Per bank write bursts -system.physmem.perBankWrBursts::1 6395 # Per bank write bursts -system.physmem.perBankWrBursts::2 6535 # Per bank write bursts -system.physmem.perBankWrBursts::3 6562 # Per bank write bursts -system.physmem.perBankWrBursts::4 6485 # Per bank write bursts -system.physmem.perBankWrBursts::5 6754 # Per bank write bursts -system.physmem.perBankWrBursts::6 6752 # Per bank write bursts -system.physmem.perBankWrBursts::7 6692 # Per bank write bursts -system.physmem.perBankWrBursts::8 7013 # Per bank write bursts -system.physmem.perBankWrBursts::9 6813 # Per bank write bursts -system.physmem.perBankWrBursts::10 6467 # Per bank write bursts -system.physmem.perBankWrBursts::11 6119 # Per bank write bursts -system.physmem.perBankWrBursts::12 7057 # Per bank write bursts -system.physmem.perBankWrBursts::13 6685 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 184891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2072011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 123731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2694403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54248831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293132 # Number of read requests accepted +system.physmem.writeReqs 812993 # Number of write requests accepted +system.physmem.readBursts 15293132 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 812993 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 975241856 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3518592 # Total number of bytes read from write queue +system.physmem.bytesWritten 6826496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130985112 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6790472 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 54978 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706304 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4635 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 954958 # Per bank write bursts +system.physmem.perBankRdBursts::1 950647 # Per bank write bursts +system.physmem.perBankRdBursts::2 950811 # Per bank write bursts +system.physmem.perBankRdBursts::3 950999 # Per bank write bursts +system.physmem.perBankRdBursts::4 954856 # Per bank write bursts +system.physmem.perBankRdBursts::5 951881 # Per bank write bursts +system.physmem.perBankRdBursts::6 951736 # Per bank write bursts +system.physmem.perBankRdBursts::7 951699 # Per bank write bursts +system.physmem.perBankRdBursts::8 955454 # Per bank write bursts +system.physmem.perBankRdBursts::9 951840 # Per bank write bursts +system.physmem.perBankRdBursts::10 951452 # Per bank write bursts +system.physmem.perBankRdBursts::11 951010 # Per bank write bursts +system.physmem.perBankRdBursts::12 955349 # Per bank write bursts +system.physmem.perBankRdBursts::13 951888 # Per bank write bursts +system.physmem.perBankRdBursts::14 952124 # Per bank write bursts +system.physmem.perBankRdBursts::15 951450 # Per bank write bursts +system.physmem.perBankWrBursts::0 6588 # Per bank write bursts +system.physmem.perBankWrBursts::1 6390 # Per bank write bursts +system.physmem.perBankWrBursts::2 6534 # Per bank write bursts +system.physmem.perBankWrBursts::3 6563 # Per bank write bursts +system.physmem.perBankWrBursts::4 6471 # Per bank write bursts +system.physmem.perBankWrBursts::5 6764 # Per bank write bursts +system.physmem.perBankWrBursts::6 6747 # Per bank write bursts +system.physmem.perBankWrBursts::7 6681 # Per bank write bursts +system.physmem.perBankWrBursts::8 6996 # Per bank write bursts +system.physmem.perBankWrBursts::9 6810 # Per bank write bursts +system.physmem.perBankWrBursts::10 6454 # Per bank write bursts +system.physmem.perBankWrBursts::11 6114 # Per bank write bursts +system.physmem.perBankWrBursts::12 7081 # Per bank write bursts +system.physmem.perBankWrBursts::13 6669 # Per bank write bursts system.physmem.perBankWrBursts::14 6965 # Per bank write bursts -system.physmem.perBankWrBursts::15 6821 # Per bank write bursts +system.physmem.perBankWrBursts::15 6837 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2550236004000 # Total gap between requests +system.physmem.totGap 2539695718000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 38 # Read request sizes (log2) -system.physmem.readPktSize::3 15138816 # Read request sizes (log2) +system.physmem.readPktSize::2 18 # Read request sizes (log2) +system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154633 # Read request sizes (log2) +system.physmem.readPktSize::6 154288 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59160 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1068642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1003556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 964678 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1068028 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 971433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1034228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2693278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2602966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3400925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 112135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 102170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 95874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 92374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58975 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1062531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1005454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1062790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 969024 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1031345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2691523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2602840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3403260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 99295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 93778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 90278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 18929 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,43 +161,43 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 265 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -225,96 +225,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1011151 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.031391 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 908.214038 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 201.586844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22832 2.26% 2.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19987 1.98% 4.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8899 0.88% 5.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2276 0.23% 5.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2117 0.21% 5.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1805 0.18% 5.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9141 0.90% 6.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 764 0.08% 6.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943330 93.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1011151 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6075 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2512.992263 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 47101.457482 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6047 99.54% 99.54% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.56% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.69% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 7 0.12% 99.80% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1008721 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.577780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 909.477346 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.561203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22290 2.21% 2.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20048 1.99% 4.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8821 0.87% 5.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2154 0.21% 5.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2027 0.20% 5.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1663 0.16% 5.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9185 0.91% 6.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 821 0.08% 6.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 941712 93.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1008721 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2509.988470 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 47472.970867 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6043 99.54% 99.54% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::65536-131071 3 0.05% 99.59% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 5 0.08% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 2 0.03% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.84% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6075 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.565103 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.376946 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.337614 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 6 0.10% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 5 0.08% 0.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.03% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 2 0.03% 0.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 4 0.07% 0.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 5 0.08% 0.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 2 0.03% 0.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 3 0.05% 0.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 3 0.05% 0.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 1 0.02% 0.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 4 0.07% 0.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 11 0.18% 0.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2721 44.79% 45.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 38 0.63% 46.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1583 26.06% 72.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1297 21.35% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 91 1.50% 95.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 44 0.72% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 54 0.89% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 48 0.79% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 29 0.48% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 18 0.30% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 20 0.33% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 17 0.28% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 13 0.21% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 16 0.26% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 12 0.20% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 10 0.16% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 8 0.13% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6075 # Writes before turning the bus around for reads -system.physmem.totQLat 393209260500 # Total ticks spent queuing -system.physmem.totMemAccLat 679455066750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76332215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25756.44 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6071 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6071 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.569428 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.390583 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.344347 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 2 0.03% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 6 0.10% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 3 0.05% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 4 0.07% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 3 0.05% 0.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 1 0.02% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 3 0.05% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 4 0.07% 0.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 3 0.05% 0.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 3 0.05% 0.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 1 0.02% 0.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 3 0.05% 0.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 10 0.16% 0.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2784 45.86% 46.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 49 0.81% 47.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1358 22.37% 69.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1417 23.34% 93.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 155 2.55% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 60 0.99% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 36 0.59% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 21 0.35% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 24 0.40% 98.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 17 0.28% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 23 0.38% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 14 0.23% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 10 0.16% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 12 0.20% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 16 0.26% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 11 0.18% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 14 0.23% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6071 # Writes before turning the bus around for reads +system.physmem.totQLat 392019251500 # Total ticks spent queuing +system.physmem.totMemAccLat 677734639000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76190770000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25726.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44506.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.12 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44476.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 384.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.69 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.01 # Data bus utilization in percentage -system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.02 # Data bus utilization in percentage +system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.37 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.37 # Average write queue length when enqueuing -system.physmem.readRowHits 14270960 # Number of row buffer hits during reads -system.physmem.writeRowHits 91040 # Number of row buffer hits during writes +system.physmem.avgRdQLen 5.74 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.90 # Average write queue length when enqueuing +system.physmem.readRowHits 14244888 # Number of row buffer hits during reads +system.physmem.writeRowHits 91209 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.29 # Row buffer hit rate for writes -system.physmem.avgGap 158334.21 # Average gap between requests -system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2202305646000 # Time in different power states -system.physmem.memoryStateTime::REF 85157800000 # Time in different power states +system.physmem.writeRowHitRate 85.49 # Row buffer hit rate for writes +system.physmem.avgGap 157685.09 # Average gap between requests +system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2193828681000 # Time in different power states +system.physmem.memoryStateTime::REF 84806020000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 262767276500 # Time in different power states +system.physmem.memoryStateTime::ACT 261061225250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory @@ -328,289 +328,280 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54978267 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346128 # Transaction distribution -system.membus.trans_dist::ReadResp 16346128 # Transaction distribution -system.membus.trans_dist::WriteReq 763361 # Transaction distribution -system.membus.trans_dist::WriteResp 763361 # Transaction distribution -system.membus.trans_dist::Writeback 59160 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4687 # Transaction distribution -system.membus.trans_dist::ReadExReq 131439 # Transaction distribution -system.membus.trans_dist::ReadExResp 131439 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383052 # Packet count per connected master and slave (bytes) +system.membus.throughput 55193080 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16345666 # Transaction distribution +system.membus.trans_dist::ReadResp 16345666 # Transaction distribution +system.membus.trans_dist::WriteReq 763357 # Transaction distribution +system.membus.trans_dist::WriteResp 763357 # Transaction distribution +system.membus.trans_dist::Writeback 58975 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4635 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4635 # Transaction distribution +system.membus.trans_dist::ReadExReq 131547 # Transaction distribution +system.membus.trans_dist::ReadExResp 131547 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272758 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1884913 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4271753 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550390 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390470 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34549385 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16698976 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19097094 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16665056 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19063162 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140207622 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140207622 # Total data (bytes) +system.membus.tot_pkt_size::total 140173690 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140173690 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487194000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487406000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3622500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3427500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17516054500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17563315500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4714051227 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4754319520 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37455331951 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37450374673 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64405 # number of replacements -system.l2c.tags.tagsinuse 51448.142618 # Cycle average of tags in use -system.l2c.tags.total_refs 1904465 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129797 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.672643 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2540066144500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37002.110374 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 24.124150 # Average occupied blocks per requestor +system.l2c.tags.replacements 64063 # number of replacements +system.l2c.tags.tagsinuse 51393.584080 # Cycle average of tags in use +system.l2c.tags.total_refs 1901876 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129454 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.691520 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2528371598500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37072.406553 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.476763 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4932.290143 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3309.962047 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.942781 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3265.462064 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2905.250809 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564607 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000368 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5409.710973 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3302.260075 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.209843 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2641.050651 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2952.468970 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.565680 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000145 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075261 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050506 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000136 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.049827 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044331 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.785036 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65365 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.082546 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050388 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000095 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040299 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.045051 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784204 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3060 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6878 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55034 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997391 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18931296 # Number of tag accesses -system.l2c.tags.data_accesses 18931296 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 32363 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6829 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 504085 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 191784 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30935 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6925 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 466764 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 195789 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435474 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608464 # number of Writeback hits -system.l2c.Writeback_hits::total 608464 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 26 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57858 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55192 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113050 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32363 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6829 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 504085 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 249642 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6925 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 466764 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 250981 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548524 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32363 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6829 # number of overall hits -system.l2c.overall_hits::cpu0.inst 504085 # number of overall hits -system.l2c.overall_hits::cpu0.data 249642 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30935 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6925 # number of overall hits -system.l2c.overall_hits::cpu1.inst 466764 # number of overall hits -system.l2c.overall_hits::cpu1.data 250981 # number of overall hits -system.l2c.overall_hits::total 1548524 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 35 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1024::1 438 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3140 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5952 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55810 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18903981 # Number of tag accesses +system.l2c.tags.data_accesses 18903981 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 27725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7459 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 477090 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 174144 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 29829 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 8048 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 498641 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 211687 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1434623 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 606690 # number of Writeback hits +system.l2c.Writeback_hits::total 606690 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 55364 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57398 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112762 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 27725 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7459 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 477090 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 229508 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 29829 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 8048 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 498641 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 269085 # number of demand (read+write) hits +system.l2c.demand_hits::total 1547385 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 27725 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7459 # number of overall hits +system.l2c.overall_hits::cpu0.inst 477090 # number of overall hits +system.l2c.overall_hits::cpu0.data 229508 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 29829 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 8048 # number of overall hits +system.l2c.overall_hits::cpu1.inst 498641 # number of overall hits +system.l2c.overall_hits::cpu1.data 269085 # number of overall hits +system.l2c.overall_hits::total 1547385 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7820 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6258 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4574 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4456 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23155 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1552 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1356 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2908 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 77511 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 55705 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133216 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 35 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 7229 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6022 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4914 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4504 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22694 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1367 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1538 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 56297 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76980 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133277 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7820 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 83769 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4574 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 60161 # number of demand (read+write) misses -system.l2c.demand_misses::total 156371 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 35 # number of overall misses +system.l2c.demand_misses::cpu0.inst 7229 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 62319 # 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number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 427109500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 366125745 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 625000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 294835000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 281582243 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1371510988 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13679367 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15384538 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29063905 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3324764073 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4773094655 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8097858728 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1163500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 70000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 427109500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3690889818 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 625000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 294835000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5054676898 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9469369716 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1163500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 427109500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3690889818 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 625000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 294835000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5054676898 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9469369716 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6117750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83698669250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83244575500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166949362500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 7714617000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 9329751845 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17044368845 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6117750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91413286250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 92574327345 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183993731345 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000505 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033208 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020750 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015526 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987717 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991618 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.989779 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.504178 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.572862 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541691 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000505 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.213414 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.232382 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091527 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000505 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.213414 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.232382 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091527 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61194.341467 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62769.113464 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60616.591002 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.852231 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.950585 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.786575 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59057.570972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62004.347298 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60759.611396 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59262.842293 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62046.459848 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60738.855032 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59262.842293 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62046.459848 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60738.855032 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -797,48 +776,48 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58447524 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676676 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676675 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763361 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763361 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608464 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2946 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2964 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246266 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246266 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967872 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798454 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37749 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149111 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7953186 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62935104 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85607366 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55020 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253376 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148850866 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148850866 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 204184 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4964883974 # Layer occupancy (ticks) +system.toL2Bus.throughput 58696725 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2675214 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2675214 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 606690 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2935 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2937 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246039 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246039 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1976942 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5792286 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42218 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 136665 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7948111 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63231360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85355770 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 230312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148879474 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148879474 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 192412 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4956067661 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4433375902 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4453658755 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4485758372 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4478828129 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24044394 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 26774357 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86236537 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 79740148 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48427259 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322165 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322165 # Transaction distribution -system.iobus.trans_dist::WriteReq 8177 # Transaction distribution -system.iobus.trans_dist::WriteResp 8177 # Transaction distribution +system.iobus.throughput 48628247 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution +system.iobus.trans_dist::WriteReq 8176 # Transaction distribution +system.iobus.trans_dist::WriteResp 8176 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7932 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -858,14 +837,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -885,18 +864,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390470 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500998 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500998 # Total data (bytes) +system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123501006 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3971000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -938,19 +917,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374875000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38148865049 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38124261327 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7661485 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6126508 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 381527 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4905065 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3983490 # Number of BTB hits +system.cpu0.branchPred.lookups 7765284 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5771603 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 325703 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4845901 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3829041 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.211768 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 723596 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 38982 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 79.016080 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 808445 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 22619 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -974,25 +953,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25785436 # DTB read hits -system.cpu0.dtb.read_misses 39736 # DTB read misses -system.cpu0.dtb.write_hits 6191742 # DTB write hits -system.cpu0.dtb.write_misses 10170 # DTB write misses -system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 27181562 # DTB read hits +system.cpu0.dtb.read_misses 37782 # DTB read misses +system.cpu0.dtb.write_hits 5596065 # DTB write hits +system.cpu0.dtb.write_misses 10098 # DTB write misses +system.cpu0.dtb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5474 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1453 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 731 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5491 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 645 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 284 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 628 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25825172 # DTB read accesses -system.cpu0.dtb.write_accesses 6201912 # DTB write accesses +system.cpu0.dtb.perms_faults 704 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 27219344 # DTB read accesses +system.cpu0.dtb.write_accesses 5606163 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31977178 # DTB hits -system.cpu0.dtb.misses 49906 # DTB misses -system.cpu0.dtb.accesses 32027084 # DTB accesses +system.cpu0.dtb.hits 32777627 # DTB hits +system.cpu0.dtb.misses 47880 # DTB misses +system.cpu0.dtb.accesses 32825507 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1014,696 +993,712 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5958651 # ITB inst hits -system.cpu0.itb.inst_misses 7224 # ITB inst misses +system.cpu0.itb.inst_hits 5349242 # ITB inst hits +system.cpu0.itb.inst_misses 7594 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2573 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 731 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2439 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5965875 # ITB inst accesses -system.cpu0.itb.hits 5958651 # DTB hits -system.cpu0.itb.misses 7224 # DTB misses -system.cpu0.itb.accesses 5965875 # DTB accesses -system.cpu0.numCycles 242096947 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5356836 # ITB inst accesses +system.cpu0.itb.hits 5349242 # DTB hits +system.cpu0.itb.misses 7594 # DTB misses +system.cpu0.itb.accesses 5356836 # DTB accesses +system.cpu0.numCycles 234138431 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15548527 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 46430150 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7661485 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4707086 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10443980 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2504010 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 87505 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 47991707 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1669 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1947 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 50069 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1492171 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 279 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5956718 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 371320 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2975 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77361996 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.753757 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.110815 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 14733348 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 42294638 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7765284 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4637486 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 215157682 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 899672 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 103093 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 978 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1882 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 100153 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1830103 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 127 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5346345 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 204670 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3021 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 232377075 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.216391 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.156919 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 66925381 86.51% 86.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 685980 0.89% 87.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 883677 1.14% 88.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1195178 1.54% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1096516 1.42% 91.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 566437 0.73% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1314357 1.70% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 386846 0.50% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4307624 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 222728537 95.85% 95.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 885926 0.38% 96.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 959241 0.41% 96.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1030592 0.44% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1233052 0.53% 97.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 718062 0.31% 97.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1129349 0.49% 98.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 448984 0.19% 98.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3243332 1.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77361996 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031646 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.191783 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16313273 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49370536 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9491475 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 529288 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1655237 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1021533 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91523 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 55531280 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 303986 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1655237 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17162522 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 7654348 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 28580121 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9244360 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 13063308 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 52889125 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1160 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 8605902 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 9933616 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1829408 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 705 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 54696180 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 245103090 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 223663577 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5274 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39761499 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14934681 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 590339 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 538925 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5812671 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10214201 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 7053988 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1084092 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1355038 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49147671 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1004891 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62507144 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 106564 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10354652 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26208427 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256708 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77361996 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.807983 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.536259 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 232377075 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.033165 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.180639 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12160999 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 212353937 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6177683 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1309281 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 372986 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 974074 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 78107 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 45045632 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 258698 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 372986 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12774661 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 53419035 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 30524585 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6795741 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 128487965 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 43632543 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1343 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 95385189 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 124519108 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1934134 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 46283925 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 200651385 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 53129662 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5272 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36330469 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 9953456 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 576590 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 492282 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 7436987 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7977179 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6240861 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1088795 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1688387 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 41277277 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1012498 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 59014531 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 58753 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7256631 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 15830718 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 292140 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 232377075 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.253960 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.959343 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55228815 71.39% 71.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6921867 8.95% 80.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3371546 4.36% 84.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2828196 3.66% 88.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6343832 8.20% 96.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1429149 1.85% 98.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 903697 1.17% 99.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 264810 0.34% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 70084 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 212079469 91.27% 91.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6238226 2.68% 93.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 2924438 1.26% 95.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2416467 1.04% 96.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6166815 2.65% 98.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1071194 0.46% 99.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 901941 0.39% 99.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 385048 0.17% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 193477 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77361996 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 232377075 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 34065 0.76% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4230863 93.99% 94.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 236461 5.25% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 114630 2.27% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4666706 92.48% 94.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 264598 5.24% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14977 0.02% 0.02% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29471794 47.15% 47.17% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48326 0.08% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1252 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26467836 42.34% 89.60% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6502932 10.40% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 15012 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 25515552 43.24% 43.26% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47770 0.08% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 902 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 27508063 46.61% 89.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5927232 10.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62507144 # Type of FU issued -system.cpu0.iq.rate 0.258191 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4501391 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.072014 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 207022163 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60516960 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43741315 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11807 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6284 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5315 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66987291 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6267 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 331575 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 59014531 # Type of FU issued +system.cpu0.iq.rate 0.252050 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 5045937 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.085503 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 355498871 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 49563440 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 38260615 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11956 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6482 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 64039026 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6430 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 226085 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2258680 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16640 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 890724 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1459518 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2588 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 24632 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 672041 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17025951 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348422 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17098280 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 3147229 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1655237 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6199849 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 752551 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50264845 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10214201 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 7053988 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 705061 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 147463 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 536075 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16640 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186895 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 147787 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 334682 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61435794 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26133192 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1071350 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 372986 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 50915247 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1803662 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 42401043 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 79571 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7977179 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6240861 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 734817 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 139591 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1596321 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 24632 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 160350 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 132588 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 292938 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 58604130 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 27345857 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 362682 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 112283 # number of nop insts executed -system.cpu0.iew.exec_refs 32576038 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6024055 # Number of branches executed -system.cpu0.iew.exec_stores 6442846 # Number of stores executed -system.cpu0.iew.exec_rate 0.253765 # Inst execution rate -system.cpu0.iew.wb_sent 60932314 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43746630 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24175990 # num instructions producing a value -system.cpu0.iew.wb_consumers 44857309 # num instructions consuming a value +system.cpu0.iew.exec_nop 111268 # number of nop insts executed +system.cpu0.iew.exec_refs 33208867 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5668977 # Number of branches executed +system.cpu0.iew.exec_stores 5863010 # Number of stores executed +system.cpu0.iew.exec_rate 0.250297 # Inst execution rate +system.cpu0.iew.wb_sent 55434698 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 38265806 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 21645924 # num instructions producing a value +system.cpu0.iew.wb_consumers 38521221 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.180699 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.538953 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.163432 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.561922 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10244306 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 748183 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 291383 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75706759 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.522606 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.501619 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7110536 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 720358 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 248726 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 231246727 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.150700 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 0.849611 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61320530 81.00% 81.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7333121 9.69% 90.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1910409 2.52% 93.21% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1174950 1.55% 94.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 814971 1.08% 95.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 569506 0.75% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 771340 1.02% 97.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 344904 0.46% 98.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1467028 1.94% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 218753445 94.60% 94.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6297983 2.72% 97.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1708084 0.74% 98.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1059115 0.46% 98.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 644957 0.28% 98.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 581299 0.25% 99.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 449364 0.19% 99.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 245033 0.11% 99.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1507447 0.65% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75706759 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30422123 # Number of instructions committed -system.cpu0.commit.committedOps 39564795 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 231246727 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29059194 # Number of instructions committed +system.cpu0.commit.committedOps 34848810 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14118785 # Number of memory references committed -system.cpu0.commit.loads 7955521 # Number of loads committed -system.cpu0.commit.membars 210845 # Number of memory barriers committed -system.cpu0.commit.branches 5215430 # Number of branches committed -system.cpu0.commit.fp_insts 5270 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35234514 # Number of committed integer instructions. -system.cpu0.commit.function_calls 505825 # Number of function calls committed. +system.cpu0.commit.refs 12086481 # Number of memory references committed +system.cpu0.commit.loads 6517661 # Number of loads committed +system.cpu0.commit.membars 192728 # Number of memory barriers committed +system.cpu0.commit.branches 4958536 # Number of branches committed +system.cpu0.commit.fp_insts 5174 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 30757342 # Number of committed integer instructions. +system.cpu0.commit.function_calls 472350 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 25399613 64.20% 64.20% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 45146 0.11% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 1251 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7955521 20.11% 84.42% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 6163264 15.58% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 22717072 65.19% 65.19% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 44355 0.13% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 902 0.00% 65.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 65.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.32% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 6517661 18.70% 84.02% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5568820 15.98% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 39564795 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1467028 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 34848810 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1507447 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123090455 # The number of ROB reads -system.cpu0.rob.rob_writes 101316686 # The number of ROB writes -system.cpu0.timesIdled 905863 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 164734951 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2248240039 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 30347856 # Number of Instructions Simulated -system.cpu0.committedOps 39490528 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 7.977399 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.977399 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.125354 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.125354 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 279159718 # number of integer regfile reads -system.cpu0.int_regfile_writes 44499662 # number of integer regfile writes -system.cpu0.fp_regfile_reads 45106 # number of floating regfile reads -system.cpu0.fp_regfile_writes 42408 # number of floating regfile writes -system.cpu0.misc_regfile_reads 136236681 # number of misc regfile reads -system.cpu0.misc_regfile_writes 579467 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983848 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.584983 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10572279 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984360 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.740257 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6906897250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 320.103204 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 191.481778 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.625202 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.373988 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999189 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 270795640 # The number of ROB reads +system.cpu0.rob.rob_writes 85052492 # The number of ROB writes +system.cpu0.timesIdled 264396 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 1761356 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2270391996 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 28992496 # Number of Instructions Simulated +system.cpu0.committedOps 34782112 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 8.075829 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.075829 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.123826 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.123826 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66468797 # number of integer regfile reads +system.cpu0.int_regfile_writes 24185826 # number of integer regfile writes +system.cpu0.fp_regfile_reads 44758 # number of floating regfile reads +system.cpu0.fp_regfile_writes 41844 # number of floating regfile writes +system.cpu0.cc_regfile_reads 196782773 # number of cc regfile reads +system.cpu0.cc_regfile_writes 15711716 # number of cc regfile writes +system.cpu0.misc_regfile_reads 291428250 # number of misc regfile reads +system.cpu0.misc_regfile_writes 565781 # number of misc regfile writes +system.cpu0.icache.tags.replacements 988317 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.592753 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 9970376 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 988829 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.083013 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6654117250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 184.676713 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 326.916040 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.360697 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.638508 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999205 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 12622728 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 12622728 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5401219 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5171060 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10572279 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5401219 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5171060 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10572279 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5401219 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5171060 # number of overall hits -system.cpu0.icache.overall_hits::total 10572279 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 555378 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 510680 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1066058 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 555378 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 510680 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1066058 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 555378 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 510680 # number of overall misses -system.cpu0.icache.overall_misses::total 1066058 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7663232618 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6859208809 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14522441427 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7663232618 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6859208809 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14522441427 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7663232618 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6859208809 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14522441427 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5956597 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5681740 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11638337 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5956597 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5681740 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11638337 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5956597 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5681740 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11638337 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.093237 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089881 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.091599 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.093237 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089881 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.091599 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.093237 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089881 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.091599 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13798.228626 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13431.520343 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13622.562212 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13798.228626 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13431.520343 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13622.562212 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13798.228626 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13431.520343 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13622.562212 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6762 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 12025421 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 12025421 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 4823915 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5146461 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 9970376 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 4823915 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5146461 # 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number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7237674573 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7341681631 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14579356204 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7237674573 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 7341681631 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14579356204 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7237674573 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 7341681631 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14579356204 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5346226 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5690359 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11036585 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5346226 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5690359 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11036585 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5346226 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5690359 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11036585 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097697 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.095582 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.096607 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097697 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.095582 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.096607 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097697 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.095582 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.096607 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13857.021148 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13498.269218 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13674.013448 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13857.021148 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13498.269218 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13674.013448 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13857.021148 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13498.269218 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13674.013448 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4158 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 376 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 274 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.984043 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.175182 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 42863 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38803 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 81666 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 42863 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 38803 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 81666 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 42863 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 38803 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 81666 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 512515 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 471877 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984392 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 512515 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 471877 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984392 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 512515 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 471877 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984392 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6228172986 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5583639583 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11811812569 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6228172986 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5583639583 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11811812569 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6228172986 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5583639583 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11811812569 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8994500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8994500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8994500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8994500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086042 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.083051 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084582 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086042 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.083051 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.084582 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086042 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.083051 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.084582 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11999.094435 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11999.094435 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11999.094435 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37549 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39824 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 77373 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 37549 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39824 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 77373 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 37549 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39824 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 77373 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 484762 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 504074 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 988836 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 484762 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 504074 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5888564763 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5971220456 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11859785219 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8523250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8523250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8523250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8523250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090674 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.088584 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089596 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090674 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.088584 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.089596 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090674 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.088584 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.089596 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12147.331604 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11845.920353 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11993.682693 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12147.331604 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11845.920353 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11993.682693 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12147.331604 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11845.920353 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11993.682693 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # 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Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 101726761 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 101726761 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7076892 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6698233 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13775125 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3751457 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3500966 # 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number of overall hits -system.cpu0.dcache.overall_hits::total 21027548 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 365609 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 402058 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 767667 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1663469 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1307220 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2970689 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7411 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6147 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13558 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 9 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 9 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18 # 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miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000018 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150484 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.176964 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.164263 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.155642 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.180266 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.168439 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14806.968490 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14522.200645 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14643.882163 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42473.998435 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50045.856114 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 46698.275038 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14594.998425 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13517.333524 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14030.699775 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37539.711623 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 43390.572975 # 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number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608464 # number of writebacks -system.cpu0.dcache.writebacks::total 608464 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 174205 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 207237 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 381442 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1526591 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1195009 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2721600 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 704 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 669 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1373 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1700796 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1402246 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3103042 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1700796 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1402246 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3103042 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191404 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 194821 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386225 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 136878 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 112211 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249089 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6707 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5478 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 9 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 9 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 18 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 328282 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 307032 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 635314 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 328282 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 307032 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 635314 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2672225710 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2597817092 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5270042802 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6526900100 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4738022235 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11264922335 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84662502 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63153752 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147816254 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 111499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 111499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 222998 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9199125810 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7335839327 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16534965137 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9199125810 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7335839327 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16534965137 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91653477500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90683023500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336501000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13720132000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13077337591 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26797469591 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105373609500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103760361091 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209133970591 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025718 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027438 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026558 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025278 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023337 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024365 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053418 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041675 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047412 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000075 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000071 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000073 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025532 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025783 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025653 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025532 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025783 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025653 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13961.180069 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13334.379210 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13645.006931 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47684.069756 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42224.222536 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45224.487372 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12623.006113 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11528.614823 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.001559 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12388.777778 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12388.777778 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12388.777778 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28022.023169 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23892.751658 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26026.445407 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28022.023169 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23892.751658 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26026.445407 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 606690 # number of writebacks +system.cpu0.dcache.writebacks::total 606690 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 164206 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 218384 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 382590 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1249257 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1583126 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2832383 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 616 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 758 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1374 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1413463 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1801510 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3214973 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1413463 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1801510 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3214973 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 131481 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 177917 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 309398 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 113002 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 135894 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248896 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 42994 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 32087 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 75081 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5734 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6222 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11956 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 244483 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 313811 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 558294 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 287477 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 345898 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 633375 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1725190273 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2222171472 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3947361745 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4787330436 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6538944348 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11326274784 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 807768256 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 644366504 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1452134760 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73471759 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72597010 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146068769 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6512520709 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8761115820 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15273636529 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7320288965 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9405482324 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16725771289 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91407551750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90929310002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336861752 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 11972132389 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14721058995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26693191384 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103379684139 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 105650368997 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209030053136 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021369 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026985 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024274 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023230 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025353 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.394263 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.379732 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.387919 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049205 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044389 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046575 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000018 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.022191 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026253 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024304 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025837 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028734 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027343 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13121.213506 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12489.933351 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12758.200586 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42365.006248 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48117.976864 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45506.053870 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18787.929851 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20081.855705 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19340.908619 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12813.351761 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11667.793314 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12217.193794 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26637.928645 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27918.447154 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27357.694206 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25463.911774 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27191.490914 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26407.375234 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1714,15 +1709,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7344792 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5924572 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 342317 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4758265 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3794052 # Number of BTB hits +system.cpu1.branchPred.lookups 8288231 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6165176 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 342380 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5156418 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4057157 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.736038 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 685317 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35371 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 78.681693 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 881950 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 23449 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1746,25 +1741,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25350014 # DTB read hits -system.cpu1.dtb.read_misses 36246 # DTB read misses -system.cpu1.dtb.write_hits 5533315 # DTB write hits -system.cpu1.dtb.write_misses 8540 # DTB write misses -system.cpu1.dtb.flush_tlb 510 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 28293531 # DTB read hits +system.cpu1.dtb.read_misses 40544 # DTB read misses +system.cpu1.dtb.write_hits 6190636 # DTB write hits +system.cpu1.dtb.write_misses 14491 # DTB write misses +system.cpu1.dtb.flush_tlb 506 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5471 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1908 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 708 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5400 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 865 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 710 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25386260 # DTB read accesses -system.cpu1.dtb.write_accesses 5541855 # DTB write accesses +system.cpu1.dtb.perms_faults 723 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 28334075 # DTB read accesses +system.cpu1.dtb.write_accesses 6205127 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 30883329 # DTB hits -system.cpu1.dtb.misses 44786 # DTB misses -system.cpu1.dtb.accesses 30928115 # DTB accesses +system.cpu1.dtb.hits 34484167 # DTB hits +system.cpu1.dtb.misses 55035 # DTB misses +system.cpu1.dtb.accesses 34539202 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1786,329 +1781,329 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5683844 # ITB inst hits -system.cpu1.itb.inst_misses 6848 # ITB inst misses +system.cpu1.itb.inst_hits 5693555 # ITB inst hits +system.cpu1.itb.inst_misses 8207 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 510 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 506 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2653 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 708 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2675 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1514 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2702 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5690692 # ITB inst accesses -system.cpu1.itb.hits 5683844 # DTB hits -system.cpu1.itb.misses 6848 # DTB misses -system.cpu1.itb.accesses 5690692 # DTB accesses -system.cpu1.numCycles 235812118 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5701762 # ITB inst accesses +system.cpu1.itb.hits 5693555 # DTB hits +system.cpu1.itb.misses 8207 # DTB misses +system.cpu1.itb.accesses 5701762 # DTB accesses +system.cpu1.numCycles 237058963 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14488159 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45028124 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7344792 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4479369 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9950354 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2325910 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82893 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 46948697 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1099 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1893 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 45519 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1268155 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 161 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5681743 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 353393 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2950 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74402978 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.748631 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.104884 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15389347 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 44896719 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8288231 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4939107 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 217242159 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 949095 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 106364 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 1987 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1943 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 92979 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 2091650 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5690360 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 215494 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3361 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 235400962 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.228809 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.188674 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64461074 86.64% 86.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 633258 0.85% 87.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 845202 1.14% 88.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1118143 1.50% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1030578 1.39% 91.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 551741 0.74% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1296054 1.74% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 370486 0.50% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4096442 5.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 225085908 95.62% 95.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 947634 0.40% 96.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1047135 0.44% 96.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1048515 0.45% 96.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1240998 0.53% 97.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 829745 0.35% 97.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1296822 0.55% 98.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 452969 0.19% 98.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3451236 1.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74402978 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.031147 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.190949 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15290128 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 48029788 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9010807 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 535995 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1534066 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 962796 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 84486 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53087117 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 281620 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1534066 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16089413 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 6996685 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 28422508 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8819964 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 12538212 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 50579819 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 715 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 8590875 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 9852379 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1395671 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 1301 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 52976488 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 233969396 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 213834273 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5207 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38971918 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14004569 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 583497 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 540607 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 5363476 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9768473 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6353478 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 903299 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1144541 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47001226 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 985413 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60595640 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 98989 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9593116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24473464 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 250944 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74402978 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.814425 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.533021 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 235400962 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.034963 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.189391 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 12590716 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 214453384 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 6500032 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1465156 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 389454 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1047596 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86470 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 48240012 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 288766 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 389454 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 13272686 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 54002992 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 31282477 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 7201814 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 129249426 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 46761611 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 1258 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 95572539 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 124561907 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 2450017 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 49620172 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 215588900 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 57377506 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 4944 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39615169 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 10004995 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 609511 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 515718 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8221045 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 8459299 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6818667 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1033426 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1557443 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 44314605 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1045489 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62743783 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 61525 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 7205140 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 16025571 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 281591 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 235400962 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.266540 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.981476 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 52794785 70.96% 70.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6823804 9.17% 80.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3272663 4.40% 84.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2786608 3.75% 88.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6272134 8.43% 96.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1319081 1.77% 98.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 820611 1.10% 99.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 247257 0.33% 99.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 66035 0.09% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 213793871 90.82% 90.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6637383 2.82% 93.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3199231 1.36% 95.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2579548 1.10% 96.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6422119 2.73% 98.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1152982 0.49% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1001630 0.43% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 407456 0.17% 99.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 206742 0.09% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74402978 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 235400962 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29526 0.66% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4196905 94.38% 95.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 220217 4.95% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 146491 2.81% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4788852 91.80% 94.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 281237 5.39% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 13541 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28679065 47.33% 47.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45344 0.07% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 858 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26009717 42.92% 90.35% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5847084 9.65% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 13506 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 27516436 43.86% 43.88% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46370 0.07% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1209 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 28654021 45.67% 89.62% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6512241 10.38% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60595640 # Type of FU issued -system.cpu1.iq.rate 0.256966 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4446652 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.073382 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 200172970 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57588554 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41991709 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11520 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6240 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4992 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65022566 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6185 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 323560 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 62743783 # Type of FU issued +system.cpu1.iq.rate 0.264676 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 5216581 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.083141 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 366155152 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 52582376 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41291326 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11482 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6074 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5054 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 67940659 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6199 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 226253 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2067890 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2468 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15600 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 783792 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1460814 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2639 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 24306 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 652998 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16950409 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 331839 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17101900 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3881798 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1534066 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5578937 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 735039 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48101549 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 89840 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9768473 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6353478 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 710230 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 138266 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 531900 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15600 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 167974 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 132221 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 300195 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59563474 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25690610 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1032166 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 389454 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 50160792 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 3093797 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 45494090 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 85835 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 8459299 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6818667 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 741438 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2862513 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 24306 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 166054 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 139765 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 305819 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 62318890 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 28486625 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 369994 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 114910 # number of nop insts executed -system.cpu1.iew.exec_refs 31485549 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5840798 # Number of branches executed -system.cpu1.iew.exec_stores 5794939 # Number of stores executed -system.cpu1.iew.exec_rate 0.252589 # Inst execution rate -system.cpu1.iew.wb_sent 59096440 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41996701 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23719594 # num instructions producing a value -system.cpu1.iew.wb_consumers 43668575 # num instructions consuming a value +system.cpu1.iew.exec_nop 133996 # number of nop insts executed +system.cpu1.iew.exec_refs 34929125 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6064585 # Number of branches executed +system.cpu1.iew.exec_stores 6442500 # Number of stores executed +system.cpu1.iew.exec_rate 0.262884 # Inst execution rate +system.cpu1.iew.wb_sent 58464614 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41296380 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23329556 # num instructions producing a value +system.cpu1.iew.wb_consumers 41830645 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178094 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.543173 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.174203 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.557714 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9469311 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 734469 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 259123 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 72868911 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.524128 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.502288 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 7169441 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 763898 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 257160 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 234250313 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.162130 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 0.884909 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 58802570 80.70% 80.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7335717 10.07% 90.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1834357 2.52% 93.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1110131 1.52% 94.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 806352 1.11% 95.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 478738 0.66% 96.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 708592 0.97% 97.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 352493 0.48% 98.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1439961 1.98% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 220821840 94.27% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6746509 2.88% 97.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1771690 0.76% 97.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1085849 0.46% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 731494 0.31% 98.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 648369 0.28% 98.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 505518 0.22% 99.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 281725 0.12% 99.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1657319 0.71% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 72868911 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30042313 # Number of instructions committed -system.cpu1.commit.committedOps 38192613 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 234250313 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31416794 # Number of instructions committed +system.cpu1.commit.committedOps 37978992 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13270269 # Number of memory references committed -system.cpu1.commit.loads 7700583 # Number of loads committed -system.cpu1.commit.membars 192827 # Number of memory barriers committed -system.cpu1.commit.branches 5091642 # Number of branches committed -system.cpu1.commit.fp_insts 4942 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33962282 # Number of committed integer instructions. -system.cpu1.commit.function_calls 485556 # Number of function calls committed. +system.cpu1.commit.refs 13164154 # Number of memory references committed +system.cpu1.commit.loads 6998485 # Number of loads committed +system.cpu1.commit.membars 211048 # Number of memory barriers committed +system.cpu1.commit.branches 5351716 # Number of branches committed +system.cpu1.commit.fp_insts 5038 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33506635 # Number of committed integer instructions. +system.cpu1.commit.function_calls 519749 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 24878693 65.14% 65.14% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 42793 0.11% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 858 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 7700583 20.16% 85.42% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 5569686 14.58% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 24770094 65.22% 65.22% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 43535 0.11% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 1209 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 6998485 18.43% 83.77% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6165669 16.23% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 38192613 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1439961 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 37978992 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1657319 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 118199712 # The number of ROB reads -system.cpu1.rob.rob_writes 96901530 # The number of ROB writes -system.cpu1.timesIdled 866503 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 161409140 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2317329341 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29966199 # Number of Instructions Simulated -system.cpu1.committedOps 38116499 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 7.869270 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.869270 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.127077 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.127077 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 270334360 # number of integer regfile reads -system.cpu1.int_regfile_writes 43344614 # number of integer regfile writes -system.cpu1.fp_regfile_reads 45048 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42280 # number of floating regfile writes -system.cpu1.misc_regfile_reads 130449609 # number of misc regfile reads -system.cpu1.misc_regfile_writes 594503 # number of misc regfile writes +system.cpu1.rob.rob_reads 276790751 # The number of ROB reads +system.cpu1.rob.rob_writes 91451122 # The number of ROB writes +system.cpu1.timesIdled 270857 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1658001 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2279071980 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31333111 # Number of Instructions Simulated +system.cpu1.committedOps 37895309 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 7.565765 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.565765 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.132174 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.132174 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 71132794 # number of integer regfile reads +system.cpu1.int_regfile_writes 26016814 # number of integer regfile writes +system.cpu1.fp_regfile_reads 44316 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42056 # number of floating regfile writes +system.cpu1.cc_regfile_reads 209312794 # number of cc regfile reads +system.cpu1.cc_regfile_writes 17049814 # number of cc regfile writes +system.cpu1.misc_regfile_reads 299103919 # number of misc regfile reads +system.cpu1.misc_regfile_writes 609097 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2125,17 +2120,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1734330533049 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1734330533049 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732377463327 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1732377463327 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732377463327 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1732377463327 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83365 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |