stats: Update to match ARM ISA changes

3 files changed, 67 insertions, 24 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
index 847b205be..00e7e2739 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -47,6 +47,8 @@ phys_addr_range_64=40
 readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -199,11 +201,18 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
+useIndirect=true
 
 [system.cpu0.dcache]
 type=Cache
@@ -804,11 +813,18 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
+useIndirect=true
 
 [system.cpu1.dstage2_mmu]
 type=ArmStage2MMU
@@ -1339,14 +1355,14 @@ size=4194304
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
 point_of_coherency=true
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -1373,6 +1389,13 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
 IDD0=0.075000
@@ -1577,6 +1600,7 @@ pio=system.iobus.master[5]
 type=SubSystem
 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.dcc.osc_cpu]
 type=RealViewOsc
@@ -1769,6 +1793,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview
@@ -1964,8 +1989,9 @@ pio=system.membus.master[4]
 
 [system.realview.mcc]
 type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.mcc.osc_clcd]
 type=RealViewOsc
@@ -2011,6 +2037,16 @@ position=0
 site=0
 voltage_domain=system.voltage_domain
 
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
index d345b4b2d..2c5672b0b 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
@@ -26,31 +26,38 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[4], crm[12], opc2[0]
 warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
 warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
 warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
 warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
 warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
 warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
+warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1]
 warn: Returning zero for read from miscreg pmcr
 warn: Ignoring write to miscreg pmcntenclr
 warn: Ignoring write to miscreg pmintenclr
 warn: Ignoring write to miscreg pmovsr
 warn: Ignoring write to miscreg pmcr
-warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[6]
+warn: CP14 unimplemented crn[5], opc1[4], crm[8], opc2[2]
+warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2]
 warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
-warn: CP14 unimplemented crn[3], opc1[0], crm[0], opc2[0]
-warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3]
-warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3]
+warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5]
 warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]
+warn: CP14 unimplemented crn[3], opc1[4], crm[0], opc2[3]
+warn: CP14 unimplemented crn[3], opc1[4], crm[4], opc2[3]
 warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[0]
-warn: CP14 unimplemented crn[2], opc1[2], crm[0], opc2[2]
-warn: CP14 unimplemented crn[12], opc1[0], crm[12], opc2[0]
-warn: CP14 unimplemented crn[12], opc1[0], crm[12], opc2[1]
-warn: CP14 unimplemented crn[12], opc1[0], crm[0], opc2[3]
+warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[3]
 warn: 	instruction 'mcr dcisw' unimplemented
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: 	instruction 'mcr bpiall' unimplemented
-warn: CP14 unimplemented crn[2], opc1[2], crm[4], opc2[1]
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index 8140fab33..3a0955877 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.804583                       # Nu
 sim_ticks                                2804582834000                       # Number of ticks simulated
 final_tick                               2804582834000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  77550                       # Simulator instruction rate (inst/s)
-host_op_rate                                    94124                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1860425573                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 586788                       # Number of bytes of host memory used
-host_seconds                                  1507.50                       # Real time elapsed on the host
+host_inst_rate                                 167374                       # Simulator instruction rate (inst/s)
+host_op_rate                                   203147                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4015325540                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 633236                       # Number of bytes of host memory used
+host_seconds                                   698.47                       # Real time elapsed on the host
 sim_insts                                   116905819                       # Number of instructions simulated
 sim_ops                                     141891765                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -639,7 +639,7 @@ system.cpu0.rename.IQFullEvents               1036846                       # Nu
 system.cpu0.rename.LQFullEvents                275223                       # Number of times rename has blocked due to LQ full
 system.cpu0.rename.SQFullEvents               5569610                       # Number of times rename has blocked due to SQ full
 system.cpu0.rename.RenamedOperands           83235701                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            372792978                       # Number of register rename lookups that rename has made
+system.cpu0.rename.RenameLookups            372775200                       # Number of register rename lookups that rename has made
 system.cpu0.rename.int_rename_lookups        90140763                       # Number of integer rename lookups
 system.cpu0.rename.fp_rename_lookups             7010                       # Number of floating rename lookups
 system.cpu0.rename.CommittedMaps             70379825                       # Number of HB maps that are committed
@@ -656,7 +656,7 @@ system.cpu0.iq.iqNonSpecInstsAdded            1057787                       # Nu
 system.cpu0.iq.iqInstsIssued                 74749052                       # Number of instructions issued
 system.cpu0.iq.iqSquashedInstsIssued            90659                       # Number of squashed instructions issued
 system.cpu0.iq.iqSquashedInstsExamined       10605329                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     23154537                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedOperandsExamined     23152649                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu0.iq.iqSquashedNonSpecRemoved        112514                       # Number of squashed non-spec instructions that were removed
 system.cpu0.iq.issued_per_cycle::samples    103827961                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::mean        0.719932                       # Number of insts issued each cycle
@@ -878,7 +878,7 @@ system.cpu0.fp_regfile_reads                    17106                       # nu
 system.cpu0.fp_regfile_writes                   13230                       # number of floating regfile writes
 system.cpu0.cc_regfile_reads                262463335                       # number of cc regfile reads
 system.cpu0.cc_regfile_writes                27226302                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              143950430                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads              143945708                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                725062                       # number of misc regfile writes
 system.cpu0.dcache.tags.replacements           852281                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.984445                       # Cycle average of tags in use
@@ -1571,7 +1571,7 @@ system.cpu1.rename.IQFullEvents               1748729                       # Nu
 system.cpu1.rename.LQFullEvents                211009                       # Number of times rename has blocked due to LQ full
 system.cpu1.rename.SQFullEvents               4894541                       # Number of times rename has blocked due to SQ full
 system.cpu1.rename.RenamedOperands           89713841                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            398200824                       # Number of register rename lookups that rename has made
+system.cpu1.rename.RenameLookups            398185196                       # Number of register rename lookups that rename has made
 system.cpu1.rename.int_rename_lookups        96380963                       # Number of integer rename lookups
 system.cpu1.rename.fp_rename_lookups             6166                       # Number of floating rename lookups
 system.cpu1.rename.CommittedMaps             76287775                       # Number of HB maps that are committed
@@ -1588,7 +1588,7 @@ system.cpu1.iq.iqNonSpecInstsAdded            1152123                       # Nu
 system.cpu1.iq.iqInstsIssued                 80030097                       # Number of instructions issued
 system.cpu1.iq.iqSquashedInstsIssued            91651                       # Number of squashed instructions issued
 system.cpu1.iq.iqSquashedInstsExamined       10961230                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     24701225                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedOperandsExamined     24699895                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu1.iq.iqSquashedNonSpecRemoved        103564                       # Number of squashed non-spec instructions that were removed
 system.cpu1.iq.issued_per_cycle::samples    107161169                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::mean        0.746820                       # Number of insts issued each cycle
@@ -1810,7 +1810,7 @@ system.cpu1.fp_regfile_reads                    16634                       # nu
 system.cpu1.fp_regfile_writes                   13036                       # number of floating regfile writes
 system.cpu1.cc_regfile_reads                280643076                       # number of cc regfile reads
 system.cpu1.cc_regfile_writes                29716175                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              149728966                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads              149724890                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                794523                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution