diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3 | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini | 211 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | 3560 |
2 files changed, 1973 insertions, 1798 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 0865afb47..bd21d2c8f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -184,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -206,18 +218,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -226,15 +241,18 @@ port=system.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -243,16 +261,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -261,22 +282,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu0.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu0.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -285,22 +310,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu0.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu0.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -309,10 +338,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -321,124 +352,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu0.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu0.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu0.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu0.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu0.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu0.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu0.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu0.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu0.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu0.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu0.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu0.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu0.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu0.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu0.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu0.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu0.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -447,10 +499,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -459,16 +513,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu0.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -477,10 +534,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -491,6 +550,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -513,14 +573,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -539,18 +602,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=DerivO3CPU @@ -581,6 +647,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -643,6 +711,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -655,12 +724,14 @@ predType=tournament [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system @@ -668,15 +739,18 @@ sys=system type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -685,16 +759,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -703,22 +780,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu1.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu1.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -727,22 +808,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu1.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu1.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -751,10 +836,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -763,124 +850,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu1.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu1.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu1.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu1.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu1.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu1.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu1.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu1.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu1.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu1.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu1.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu1.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu1.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu1.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu1.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu1.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu1.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -889,10 +997,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -901,16 +1011,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu1.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -919,16 +1032,19 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -947,30 +1063,36 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -983,6 +1105,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1005,6 +1128,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1014,6 +1138,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1036,6 +1161,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1043,6 +1169,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1054,6 +1181,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1080,6 +1208,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1091,19 +1220,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -1113,6 +1246,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -1122,6 +1256,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -1150,6 +1285,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -1159,8 +1295,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1172,6 +1340,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -1187,6 +1356,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -1201,6 +1372,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -1210,6 +1382,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -1231,8 +1404,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1241,6 +1416,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -1251,6 +1427,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1261,6 +1438,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1271,6 +1449,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1285,6 +1464,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1298,6 +1478,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1315,6 +1496,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1327,6 +1509,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1338,6 +1521,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1348,6 +1532,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1360,6 +1545,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1373,6 +1559,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1383,6 +1570,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1393,6 +1581,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1403,6 +1592,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1415,6 +1605,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1429,6 +1620,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1441,6 +1633,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1455,6 +1648,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1465,6 +1659,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1475,6 +1670,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1485,6 +1681,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1493,6 +1690,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1501,6 +1699,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1510,11 +1709,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index cc97b6f9f..5fef90c5a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,166 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.549325 # Number of seconds simulated -sim_ticks 2549325180000 # Number of ticks simulated -final_tick 2549325180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.549345 # Number of seconds simulated +sim_ticks 2549345168000 # Number of ticks simulated +final_tick 2549345168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61075 # Simulator instruction rate (inst/s) -host_op_rate 78588 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2581455626 # Simulator tick rate (ticks/s) -host_mem_usage 428832 # Number of bytes of host memory used -host_seconds 987.55 # Real time elapsed on the host -sim_insts 60314884 # Number of instructions simulated -sim_ops 77609482 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 48945 # Simulator instruction rate (inst/s) +host_op_rate 62980 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2068782078 # Simulator tick rate (ticks/s) +host_mem_usage 448444 # Number of bytes of host memory used +host_seconds 1232.29 # Real time elapsed on the host +sim_insts 60314699 # Number of instructions simulated +sim_ops 77609228 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 507840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4720464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 291712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4372184 # Number of bytes read from this memory -system.physmem.bytes_read::total 131005480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 507840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 291712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785664 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521520 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494580 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801764 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 498624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4680272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 301248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4410392 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 498624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 301248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784640 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521380 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494720 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800740 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7935 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73791 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 68321 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293464 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59151 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380380 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373645 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813176 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47506897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 678 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7791 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 68918 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293442 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59135 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380345 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373680 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813160 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47506524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 199206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1851652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 114427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1715036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51388297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 199206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 114427 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313633 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596832 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586265 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2668064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47506897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 195589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1835872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 118167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1730010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51387342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 195589 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 118167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484554 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596773 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586315 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2667642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47506524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 199206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2448485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 114427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2301301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54056362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293464 # Number of read requests accepted -system.physmem.writeReqs 813176 # Number of write requests accepted -system.physmem.readBursts 15293464 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813176 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978217536 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 564160 # Total number of bytes read from write queue -system.physmem.bytesWritten 6910272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131005480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801764 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8815 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705189 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4711 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955865 # Per bank write bursts -system.physmem.perBankRdBursts::1 955523 # Per bank write bursts -system.physmem.perBankRdBursts::2 954611 # Per bank write bursts -system.physmem.perBankRdBursts::3 954852 # Per bank write bursts -system.physmem.perBankRdBursts::4 955764 # Per bank write bursts -system.physmem.perBankRdBursts::5 955945 # Per bank write bursts -system.physmem.perBankRdBursts::6 954843 # Per bank write bursts -system.physmem.perBankRdBursts::7 954680 # Per bank write bursts -system.physmem.perBankRdBursts::8 956251 # Per bank write bursts -system.physmem.perBankRdBursts::9 955822 # Per bank write bursts -system.physmem.perBankRdBursts::10 954302 # Per bank write bursts -system.physmem.perBankRdBursts::11 954022 # Per bank write bursts -system.physmem.perBankRdBursts::12 956218 # Per bank write bursts -system.physmem.perBankRdBursts::13 955977 # Per bank write bursts -system.physmem.perBankRdBursts::14 955052 # Per bank write bursts -system.physmem.perBankRdBursts::15 954922 # Per bank write bursts -system.physmem.perBankWrBursts::0 6685 # Per bank write bursts -system.physmem.perBankWrBursts::1 6462 # Per bank write bursts -system.physmem.perBankWrBursts::2 6616 # Per bank write bursts -system.physmem.perBankWrBursts::3 6625 # Per bank write bursts -system.physmem.perBankWrBursts::4 6578 # Per bank write bursts -system.physmem.perBankWrBursts::5 6834 # Per bank write bursts -system.physmem.perBankWrBursts::6 6825 # Per bank write bursts -system.physmem.perBankWrBursts::7 6778 # Per bank write bursts -system.physmem.perBankWrBursts::8 7112 # Per bank write bursts -system.physmem.perBankWrBursts::9 6876 # Per bank write bursts -system.physmem.perBankWrBursts::10 6540 # Per bank write bursts -system.physmem.perBankWrBursts::11 6189 # Per bank write bursts -system.physmem.perBankWrBursts::12 7142 # Per bank write bursts -system.physmem.perBankWrBursts::13 6759 # Per bank write bursts -system.physmem.perBankWrBursts::14 7042 # Per bank write bursts -system.physmem.perBankWrBursts::15 6910 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 195589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2432645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 118167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2316325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54054984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293442 # Number of read requests accepted +system.physmem.writeReqs 813160 # Number of write requests accepted +system.physmem.readBursts 15293442 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813160 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978220224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 560064 # Total number of bytes read from write queue +system.physmem.bytesWritten 6909248 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131004072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800740 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8751 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705188 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4685 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955866 # Per bank write bursts +system.physmem.perBankRdBursts::1 955512 # Per bank write bursts +system.physmem.perBankRdBursts::2 954595 # Per bank write bursts +system.physmem.perBankRdBursts::3 954812 # Per bank write bursts +system.physmem.perBankRdBursts::4 955762 # Per bank write bursts +system.physmem.perBankRdBursts::5 955910 # Per bank write bursts +system.physmem.perBankRdBursts::6 954892 # Per bank write bursts +system.physmem.perBankRdBursts::7 954654 # Per bank write bursts +system.physmem.perBankRdBursts::8 956247 # Per bank write bursts +system.physmem.perBankRdBursts::9 955899 # Per bank write bursts +system.physmem.perBankRdBursts::10 954311 # Per bank write bursts +system.physmem.perBankRdBursts::11 954068 # Per bank write bursts +system.physmem.perBankRdBursts::12 956211 # Per bank write bursts +system.physmem.perBankRdBursts::13 955980 # Per bank write bursts +system.physmem.perBankRdBursts::14 955097 # Per bank write bursts +system.physmem.perBankRdBursts::15 954875 # Per bank write bursts +system.physmem.perBankWrBursts::0 6687 # Per bank write bursts +system.physmem.perBankWrBursts::1 6461 # Per bank write bursts +system.physmem.perBankWrBursts::2 6610 # Per bank write bursts +system.physmem.perBankWrBursts::3 6631 # Per bank write bursts +system.physmem.perBankWrBursts::4 6571 # Per bank write bursts +system.physmem.perBankWrBursts::5 6830 # Per bank write bursts +system.physmem.perBankWrBursts::6 6820 # Per bank write bursts +system.physmem.perBankWrBursts::7 6764 # Per bank write bursts +system.physmem.perBankWrBursts::8 7113 # Per bank write bursts +system.physmem.perBankWrBursts::9 6879 # Per bank write bursts +system.physmem.perBankWrBursts::10 6545 # Per bank write bursts +system.physmem.perBankWrBursts::11 6197 # Per bank write bursts +system.physmem.perBankWrBursts::12 7141 # Per bank write bursts +system.physmem.perBankWrBursts::13 6760 # Per bank write bursts +system.physmem.perBankWrBursts::14 7037 # Per bank write bursts +system.physmem.perBankWrBursts::15 6911 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2549324058500 # Total gap between requests +system.physmem.totGap 2549344036000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 42 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154606 # Read request sizes (log2) +system.physmem.readPktSize::6 154584 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754025 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59151 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1187642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1126920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1081304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3687011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2647213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2642028 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2655762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 54010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 60825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59135 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1194358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1134175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1088302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3688965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2641659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2636525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2648641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 52098 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 58013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -171,418 +159,411 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86834 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11344.953359 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1015.074534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16830.192081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23626 27.21% 27.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14089 16.23% 43.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2724 3.14% 46.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2126 2.45% 49.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1310 1.51% 50.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1204 1.39% 51.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 811 0.93% 52.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1018 1.17% 54.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 572 0.66% 54.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 583 0.67% 55.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 533 0.61% 55.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 603 0.69% 56.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 265 0.31% 57.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 147 0.17% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 578 0.67% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 113 0.13% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 129 0.15% 58.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 72 0.08% 58.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 237 0.27% 58.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 56 0.06% 58.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 502 0.58% 59.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 39 0.04% 59.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 171 0.20% 59.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 11 0.01% 59.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 115 0.13% 59.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 15 0.02% 59.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 109 0.13% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 18 0.02% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 54 0.06% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 24 0.03% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 490 0.56% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 17 0.02% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 36 0.04% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 7 0.01% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 154 0.18% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 14 0.02% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 32 0.04% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 7 0.01% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 95 0.11% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 14 0.02% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 9 0.01% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 155 0.18% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 16 0.02% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 10 0.01% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 408 0.47% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 10 0.01% 61.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 7 0.01% 61.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 96 0.11% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 10 0.01% 61.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 20 0.02% 61.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 9 0.01% 61.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 86 0.10% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 6 0.01% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 21 0.02% 62.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 12 0.01% 62.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 58 0.07% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 407 0.47% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 10 0.01% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 18 0.02% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 3 0.00% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 75 0.09% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 12 0.01% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 7 0.01% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 139 0.16% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 8 0.01% 62.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 15 0.02% 63.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 72 0.08% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 6 0.01% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 7 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 17 0.02% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 14 0.02% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 76 0.09% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 9 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 13 0.01% 63.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 144 0.17% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 9 0.01% 63.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 13 0.01% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 12 0.01% 64.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 6 0.01% 64.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 262 0.30% 64.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 5 0.01% 64.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 6 0.01% 64.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 136 0.16% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 3 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 8 0.01% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 8 0.01% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 6 0.01% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 21 0.02% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 74 0.09% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 5 0.01% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 8 0.01% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 452 0.52% 65.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 4 0.00% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 13 0.01% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 11 0.01% 65.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 23 0.03% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 4 0.00% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 73 0.08% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 2 0.00% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 3 0.00% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 132 0.15% 65.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 4 0.00% 65.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 243 0.28% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 128 0.15% 66.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 66 0.08% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 67 0.08% 66.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 450 0.52% 66.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 67 0.08% 66.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 2 0.00% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 133 0.15% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 1 0.00% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 251 0.29% 67.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 68 0.08% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10695 1 0.00% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 128 0.15% 67.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 66 0.08% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 387 0.45% 68.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 67 0.08% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11719 1 0.00% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 121 0.14% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 66 0.08% 68.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 380 0.44% 68.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 37 0.04% 68.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 69 0.08% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 65 0.07% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13255 1 0.00% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 389 0.45% 69.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 129 0.15% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 66 0.08% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 120 0.14% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 443 0.51% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 57 0.07% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 13 0.01% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 119 0.14% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 388 0.45% 71.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 123 0.14% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15751 1 0.00% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 64 0.07% 71.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 66 0.08% 71.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16327 1 0.00% 71.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 526 0.61% 71.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 68 0.08% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 64 0.07% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 122 0.14% 72.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 391 0.45% 72.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 120 0.14% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 15 0.02% 72.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 57 0.07% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 1 0.00% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 444 0.51% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 119 0.14% 73.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 66 0.08% 73.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 129 0.15% 73.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 384 0.44% 74.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 64 0.07% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 70 0.08% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 37 0.04% 74.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 1 0.00% 74.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 382 0.44% 74.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 65 0.07% 74.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 119 0.14% 75.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 66 0.08% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 385 0.44% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 68 0.08% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 128 0.15% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 69 0.08% 75.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 1 0.00% 75.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 253 0.29% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 1 0.00% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 132 0.15% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22976-22983 1 0.00% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 67 0.08% 76.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 450 0.52% 76.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 68 0.08% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 1 0.00% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 67 0.08% 77.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 129 0.15% 77.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 137 0.16% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 1 0.00% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 129 0.15% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 67 0.08% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 67 0.08% 77.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 448 0.52% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25671 1 0.00% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 66 0.08% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 134 0.15% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 253 0.29% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 68 0.08% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 129 0.15% 78.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27264-27271 1 0.00% 78.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 68 0.08% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 384 0.44% 79.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 66 0.08% 79.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 119 0.14% 79.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 64 0.07% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 380 0.44% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 1 0.00% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 37 0.04% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 72 0.08% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 65 0.07% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 385 0.44% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 129 0.15% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 64 0.07% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 119 0.14% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 443 0.51% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 56 0.06% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 13 0.01% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 119 0.14% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 2 0.00% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 1 0.00% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 389 0.45% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31808-31815 1 0.00% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 124 0.14% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 66 0.08% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 66 0.08% 82.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 526 0.61% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 65 0.07% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 65 0.07% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 125 0.14% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 390 0.45% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 119 0.14% 84.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 13 0.01% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 56 0.06% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 441 0.51% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 119 0.14% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 64 0.07% 84.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 129 0.15% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 385 0.44% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 64 0.07% 85.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 72 0.08% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36416-36423 1 0.00% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 37 0.04% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 380 0.44% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 64 0.07% 86.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 119 0.14% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 66 0.08% 86.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 384 0.44% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38080-38087 1 0.00% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 67 0.08% 87.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 128 0.15% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 68 0.08% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 253 0.29% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 134 0.15% 87.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 66 0.08% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 448 0.52% 88.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 68 0.08% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40320-40327 1 0.00% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 66 0.08% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 129 0.15% 88.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 137 0.16% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 129 0.15% 88.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 67 0.08% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 68 0.08% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 449 0.52% 89.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 67 0.08% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 2 0.00% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 132 0.15% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42944-42951 1 0.00% 89.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 251 0.29% 90.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 67 0.08% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43392-43399 2 0.00% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 128 0.15% 90.32% # Bytes accessed per row activation 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Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14187 16.38% 43.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2756 3.18% 46.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2051 2.37% 48.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1336 1.54% 50.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1207 1.39% 51.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 834 0.96% 52.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1069 1.23% 54.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 542 0.63% 54.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 595 0.69% 55.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 544 0.63% 56.06% # Bytes accessed per row activation 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11 0.01% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 8 0.01% 63.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 81 0.09% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 14 0.02% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 6 0.01% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 112 0.13% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 3 0.00% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 16 0.02% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 7 0.01% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.76% # Bytes accessed per row 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3 0.00% 65.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 8 0.01% 65.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 14 0.02% 65.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 15 0.02% 65.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 4 0.00% 65.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 8 0.01% 65.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 3 0.00% 65.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 139 0.16% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 1 0.00% 65.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 8 0.01% 65.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.41% # Bytes accessed per row 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+system.physmem.bytesPerActivate::36352-36359 70 0.08% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 129 0.15% 85.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 384 0.44% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 1 0.00% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 192 0.22% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 312 0.36% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 70 0.08% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 98 0.11% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 64 0.07% 86.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 568 0.66% 87.60% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::40448-40455 136 0.16% 88.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 72 0.08% 88.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 387 0.45% 88.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41024-41031 1 0.00% 88.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 73 0.08% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 135 0.16% 89.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 1 0.00% 89.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 257 0.30% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 183 0.21% 89.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 55 0.06% 89.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 569 0.66% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 66 0.08% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 97 0.11% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 68 0.08% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 314 0.36% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 2 0.00% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 1 0.00% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 196 0.23% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 1 0.00% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44992-44999 1 0.00% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 386 0.45% 91.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 132 0.15% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 70 0.08% 91.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 65 0.08% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46016-46023 3 0.00% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 199 0.23% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 135 0.16% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 1 0.00% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 239 0.28% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47040-47047 1 0.00% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 324 0.37% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 131 0.15% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 64 0.07% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 131 0.15% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 260 0.30% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 128 0.15% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48832-48839 1 0.00% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 61 0.07% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 3 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5274 6.09% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::49344-49351 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49472-49479 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50816-50823 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49536-49543 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50304-50311 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::51072-51079 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86834 # Bytes accessed per row activation -system.physmem.totQLat 369633946000 # Total ticks spent queuing -system.physmem.totMemAccLat 463601929750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76423245000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17544738750 # Total ticks spent accessing banks -system.physmem.avgQLat 24183.35 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1147.87 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::51200-51207 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86636 # Bytes accessed per row activation +system.physmem.totQLat 369559391250 # Total ticks spent queuing +system.physmem.totMemAccLat 463610140000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76423455000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17627293750 # Total ticks spent accessing banks +system.physmem.avgQLat 24178.40 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1153.26 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30331.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30331.67 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.39 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s @@ -592,24 +573,35 @@ system.physmem.busUtilRead 3.00 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing -system.physmem.readRowHits 15212610 # Number of row buffer hits during reads -system.physmem.writeRowHits 93178 # Number of row buffer hits during writes +system.physmem.readRowHits 15212838 # Number of row buffer hits during reads +system.physmem.writeRowHits 93174 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads system.physmem.writeRowHitRate 86.29 # Row buffer hit rate for writes -system.physmem.avgGap 158277.83 # Average gap between requests +system.physmem.avgGap 158279.45 # Average gap between requests system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 1.88 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54996997 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346113 # Transaction distribution -system.membus.trans_dist::ReadResp 16346116 # Transaction distribution +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54995612 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346068 # Transaction distribution +system.membus.trans_dist::ReadResp 16346071 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59151 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4708 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4711 # Transaction distribution -system.membus.trans_dist::ReadExReq 131399 # Transaction distribution -system.membus.trans_dist::ReadExResp 131399 # Transaction distribution +system.membus.trans_dist::Writeback 59135 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4685 # Transaction distribution +system.membus.trans_dist::ReadExReq 131422 # Transaction distribution +system.membus.trans_dist::ReadExResp 131422 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution @@ -617,261 +609,255 @@ system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382960 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885919 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885807 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272561 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550305 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34550193 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390337 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696716 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19094701 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16694284 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19092269 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140205229 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140205229 # Total data (bytes) +system.membus.tot_pkt_size::total 140202797 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140202797 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487741000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487346000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3601000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3636500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17567405000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17566569000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4737923280 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4736419263 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34188515482 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34186627978 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 64379 # number of replacements -system.l2c.tags.tagsinuse 51427.622498 # Cycle average of tags in use -system.l2c.tags.total_refs 1904241 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129768 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.674195 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2512188924000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36951.825179 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.926736 # Average occupied blocks per requestor +system.l2c.tags.replacements 64357 # number of replacements +system.l2c.tags.tagsinuse 51453.251473 # Cycle average of tags in use +system.l2c.tags.total_refs 1905423 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129744 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.686020 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2512210729500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36987.198092 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 19.713113 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4986.850446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3336.949611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.947160 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3226.583152 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2894.539843 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.563840 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000289 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4872.243485 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3313.752357 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 13.584037 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3345.363294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2901.396724 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564380 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000301 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.076093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050918 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000182 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.049234 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044167 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784723 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 32603 # number of ReadReq hits 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UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.988482 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.537930 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.544324 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541047 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.235487 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.211285 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091600 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.235487 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.211285 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091600 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61701.627339 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65461.720946 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61973.540577 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62516.088096 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64764.744789 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62038.855339 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.065604 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.714678 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61956.189415 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63673.743808 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62790.742558 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.666870 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.055860 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61882.451473 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63776.931537 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62811.563019 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1066,43 +1040,43 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58456334 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676393 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676395 # Transaction distribution +system.toL2Bus.throughput 58478558 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677542 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677544 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608382 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2974 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246144 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246144 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608494 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2952 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2958 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246169 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246169 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967115 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798220 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37803 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149157 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7952295 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62908992 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85598765 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55208 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148816461 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148816461 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 207744 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4964319701 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798582 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38031 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149645 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7954666 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62951744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85614957 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254244 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148876637 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148876637 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 205392 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4965399712 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4431802148 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4434611165 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4486267320 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4486677044 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24046904 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24152407 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86228845 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86557036 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48444532 # Throughput (bytes/s) +system.iobus.throughput 48444152 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322136 # Transaction distribution system.iobus.trans_dist::ReadResp 16322136 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution @@ -1212,40 +1186,40 @@ system.iobus.reqLayer25.occupancy 15138816000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41492591518 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41494630022 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7178846 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5689563 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 376334 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4735029 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3823898 # Number of BTB hits +system.cpu0.branchPred.lookups 7183590 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5694303 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 377290 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4721847 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3824688 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 80.757647 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 708733 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 80.999829 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 708757 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39349 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25686724 # DTB read hits -system.cpu0.dtb.read_misses 37672 # DTB read misses -system.cpu0.dtb.write_hits 5882199 # DTB write hits -system.cpu0.dtb.write_misses 9157 # DTB write misses +system.cpu0.dtb.read_hits 25676392 # DTB read hits +system.cpu0.dtb.read_misses 38073 # DTB read misses +system.cpu0.dtb.write_hits 5871403 # DTB write hits +system.cpu0.dtb.write_misses 9193 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5402 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1359 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 227 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5420 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1344 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25724396 # DTB read accesses -system.cpu0.dtb.write_accesses 5891356 # DTB write accesses +system.cpu0.dtb.perms_faults 585 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25714465 # DTB read accesses +system.cpu0.dtb.write_accesses 5880596 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31568923 # DTB hits -system.cpu0.dtb.misses 46829 # DTB misses -system.cpu0.dtb.accesses 31615752 # DTB accesses -system.cpu0.itb.inst_hits 5794960 # ITB inst hits -system.cpu0.itb.inst_misses 6979 # ITB inst misses +system.cpu0.dtb.hits 31547795 # DTB hits +system.cpu0.dtb.misses 47266 # DTB misses +system.cpu0.dtb.accesses 31595061 # DTB accesses +system.cpu0.itb.inst_hits 5793609 # ITB inst hits +system.cpu0.itb.inst_misses 6965 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1254,114 +1228,114 @@ system.cpu0.itb.flush_tlb 257 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2537 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2542 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1475 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5801939 # ITB inst accesses -system.cpu0.itb.hits 5794960 # DTB hits -system.cpu0.itb.misses 6979 # DTB misses -system.cpu0.itb.accesses 5801939 # DTB accesses -system.cpu0.numCycles 241329954 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5800574 # ITB inst accesses +system.cpu0.itb.hits 5793609 # DTB hits +system.cpu0.itb.misses 6965 # DTB misses +system.cpu0.itb.accesses 5800574 # DTB accesses +system.cpu0.numCycles 241355643 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15402359 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 44612176 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7178846 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4532631 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10046821 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2409329 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 81802 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 48777724 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1779 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1966 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 42894 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1416575 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 470 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5793020 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 368373 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3163 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77432013 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.722773 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.070911 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15408312 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 44581736 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7183590 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4533445 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10042154 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2412494 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 81949 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 48815807 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1726 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1993 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 42608 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1411972 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 385 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5791670 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 368874 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3149 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77468964 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.722040 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.069743 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67393349 87.04% 87.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 663167 0.86% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 850708 1.10% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1161944 1.50% 90.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1070979 1.38% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 538004 0.69% 92.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1258402 1.63% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 372673 0.48% 94.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4122787 5.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67434698 87.05% 87.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 662922 0.86% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 849826 1.10% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1158615 1.50% 90.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1071303 1.38% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 540404 0.70% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1264103 1.63% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 371341 0.48% 94.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4115752 5.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77432013 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.029747 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.184860 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16324291 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49901037 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9152885 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 482910 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1568783 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 985989 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 93507 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53239353 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 312067 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1568783 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17193647 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20516369 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 26371209 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8691714 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3088262 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 50703360 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7236 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 484563 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2089605 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 237 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 52223867 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 231534090 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 214067803 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5431 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 38086867 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14136999 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 416413 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 366902 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6391113 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9801074 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6698586 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1023553 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1394670 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 47085778 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 981191 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 61028996 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87181 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9766291 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24255892 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256976 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77432013 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.788162 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.509612 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77468964 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.029764 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.184714 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16332862 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49931887 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9147459 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 483482 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1571127 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 985970 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 93586 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53203424 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 313882 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1571127 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17204608 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20551297 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 26349401 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8685161 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3105311 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 50667470 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7242 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 502803 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2087731 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 194 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 52194379 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 231353972 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 213903823 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5361 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 38031727 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14162651 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 415813 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 366209 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6409920 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9794680 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6688167 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1031152 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1299354 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 47050561 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 979447 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 60972564 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 88288 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9787230 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24359943 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256705 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77468964 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.787058 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.508592 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55649099 71.87% 71.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6737778 8.70% 80.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3435441 4.44% 85.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2925983 3.78% 88.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6185685 7.99% 96.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1437832 1.86% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 773159 1.00% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 224755 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 62281 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55694568 71.89% 71.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6744950 8.71% 80.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3431902 4.43% 85.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2928703 3.78% 88.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6175861 7.97% 96.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1433177 1.85% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 773017 1.00% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 224018 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 62768 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77432013 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77468964 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29912 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 30016 0.67% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available @@ -1390,504 +1364,504 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4221653 94.70% 95.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 206360 4.63% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4221900 94.67% 95.34% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207684 4.66% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 165947 0.27% 0.27% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 28282024 46.34% 46.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46844 0.08% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1271 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26348641 43.17% 89.87% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6184237 10.13% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 165809 0.27% 0.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 28246973 46.33% 46.60% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46806 0.08% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1267 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26338371 43.20% 89.88% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6173305 10.12% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 61028996 # Type of FU issued -system.cpu0.iq.rate 0.252886 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4457926 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.073046 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 204069737 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57841875 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 42095336 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12029 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6474 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5396 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 65314591 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6384 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 305188 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 60972564 # Type of FU issued +system.cpu0.iq.rate 0.252625 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4459601 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.073141 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 203996977 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57825737 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 42036875 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12074 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6420 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5360 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 65259915 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6441 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 303470 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2103037 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3902 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15671 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 837358 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2107176 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3913 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15490 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 838182 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17232684 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348213 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17232343 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348683 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1568783 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15829049 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 237688 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 48167223 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105126 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9801074 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6698586 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 691561 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 54422 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4242 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15671 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 182031 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 143561 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 325592 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 59970791 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26024613 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1058205 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1571127 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15861030 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 237452 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 48130825 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105592 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9794680 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6688167 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 690516 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 54721 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15490 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 181987 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 144371 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 326358 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 59914186 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26012956 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1058378 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 100254 # number of nop insts executed -system.cpu0.iew.exec_refs 32151728 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5674244 # Number of branches executed -system.cpu0.iew.exec_stores 6127115 # Number of stores executed -system.cpu0.iew.exec_rate 0.248501 # Inst execution rate -system.cpu0.iew.wb_sent 59482820 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 42100732 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22797313 # num instructions producing a value -system.cpu0.iew.wb_consumers 41683102 # num instructions consuming a value +system.cpu0.iew.exec_nop 100817 # number of nop insts executed +system.cpu0.iew.exec_refs 32128938 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5674429 # Number of branches executed +system.cpu0.iew.exec_stores 6115982 # Number of stores executed +system.cpu0.iew.exec_rate 0.248240 # Inst execution rate +system.cpu0.iew.wb_sent 59424173 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 42042235 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22754717 # num instructions producing a value +system.cpu0.iew.wb_consumers 41618983 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.174453 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.546920 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.174192 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.546739 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9635326 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 724215 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 284304 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75863230 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.501725 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.477269 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9657152 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 722742 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 285161 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75897837 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.500741 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.473402 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 62300247 82.12% 82.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6632163 8.74% 90.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1905948 2.51% 93.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1063803 1.40% 94.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 963459 1.27% 96.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 539688 0.71% 96.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 720050 0.95% 97.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 348558 0.46% 98.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1389314 1.83% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 62326931 82.12% 82.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6623929 8.73% 90.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1927651 2.54% 93.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1062809 1.40% 94.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 977806 1.29% 96.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 537572 0.71% 96.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 721191 0.95% 97.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 348340 0.46% 98.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1371608 1.81% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75863230 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29321704 # Number of instructions committed -system.cpu0.commit.committedOps 38062462 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75897837 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29270698 # Number of instructions committed +system.cpu0.commit.committedOps 38005132 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13559265 # Number of memory references committed -system.cpu0.commit.loads 7698037 # Number of loads committed -system.cpu0.commit.membars 204059 # Number of memory barriers committed -system.cpu0.commit.branches 4889328 # Number of branches committed -system.cpu0.commit.fp_insts 5354 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 33742241 # Number of committed integer instructions. -system.cpu0.commit.function_calls 497179 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1389314 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13537489 # Number of memory references committed +system.cpu0.commit.loads 7687504 # Number of loads committed +system.cpu0.commit.membars 203418 # Number of memory barriers committed +system.cpu0.commit.branches 4891612 # Number of branches committed +system.cpu0.commit.fp_insts 5306 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 33685063 # Number of committed integer instructions. +system.cpu0.commit.function_calls 497791 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1371608 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 121250209 # The number of ROB reads -system.cpu0.rob.rob_writes 97007351 # The number of ROB writes -system.cpu0.timesIdled 906901 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 163897941 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2251401803 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29254206 # Number of Instructions Simulated -system.cpu0.committedOps 37994964 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29254206 # Number of Instructions Simulated -system.cpu0.cpi 8.249410 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.249410 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.121221 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.121221 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 271506841 # number of integer regfile reads -system.cpu0.int_regfile_writes 42814380 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22646 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19918 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15055897 # number of misc regfile reads -system.cpu0.misc_regfile_writes 404161 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983492 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.574238 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10516196 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984004 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.687148 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6986136250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 318.901478 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 192.672760 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.622854 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.376314 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999168 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5235281 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5280915 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10516196 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5235281 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5280915 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10516196 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5235281 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5280915 # number of overall hits -system.cpu0.icache.overall_hits::total 10516196 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 557620 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 507749 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065369 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 557620 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 507749 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065369 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 557620 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 507749 # number of overall misses -system.cpu0.icache.overall_misses::total 1065369 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7715888650 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6834076460 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14549965110 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7715888650 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6834076460 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14549965110 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7715888650 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6834076460 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14549965110 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5792901 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5788664 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11581565 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5792901 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5788664 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11581565 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5792901 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5788664 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11581565 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.096259 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087714 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.091988 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.096259 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087714 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.091988 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.096259 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087714 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.091988 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13837.180607 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13459.556710 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.207137 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13657.207137 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13657.207137 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6518 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 829 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 410 # number of cycles access was blocked +system.cpu0.rob.rob_reads 121269057 # The number of ROB reads +system.cpu0.rob.rob_writes 96938789 # The number of ROB writes +system.cpu0.timesIdled 907351 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 163886679 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2251360755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 29203197 # Number of Instructions Simulated +system.cpu0.committedOps 37937631 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 29203197 # Number of Instructions Simulated +system.cpu0.cpi 8.264699 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.264699 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.120997 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.120997 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 271224247 # number of integer regfile reads +system.cpu0.int_regfile_writes 42758050 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22657 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19930 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15040337 # number of misc regfile reads +system.cpu0.misc_regfile_writes 403311 # number of misc regfile writes +system.cpu0.icache.tags.replacements 984140 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.573239 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10515740 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 984652 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.679651 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7012159250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 319.827324 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 191.745915 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.624663 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.374504 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999166 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5233615 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5282125 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10515740 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5233615 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5282125 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10515740 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5233615 # number of overall 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miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087780 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.092058 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.096336 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087780 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.092058 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.303610 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13478.738543 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.997786 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13821.303610 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13478.738543 # average overall miss latency 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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.795980 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.088891 # mshr miss rate for ReadReq accesses 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miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.918977 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.918977 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.918977 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643990 # number of replacements +system.cpu0.dcache.tags.replacements 644131 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.993324 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21534082 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644502 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.411971 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 21534637 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644643 # Sample count of references to valid blocks. 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1863754 # number of overall misses -system.cpu0.dcache.overall_misses::total 3711155 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5258794781 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6175311803 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11434106584 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76116558084 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 73496602051 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 149613160135 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 106253499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 82007996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 188261495 # number of LoadLockedReq miss cycles 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+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1328479 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2713835 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 715 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 651 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1366 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1528876 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1548193 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3077069 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1528876 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1548193 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3077069 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181314 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205081 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386395 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127417 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 121592 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249009 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6710 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5481 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12191 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 308731 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 326673 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635404 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 308731 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 326673 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635404 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2537114094 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2716244009 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5253358103 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5888392200 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5776496365 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11664888565 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84437751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63633003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148070754 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8425506294 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8492740374 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16918246668 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8425506294 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 8492740374 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16918246668 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92381073251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 89949254752 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182330328003 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13713085264 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13059234413 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26772319677 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106071136245 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103026320251 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209097456496 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025358 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027786 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024970 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023736 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055086 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040661 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047508 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000051 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000092 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000073 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025666 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13978.974235 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13269.059484 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.899713 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46428.448104 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47251.379913 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46828.660302 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12580.254879 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11592.833121 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12136.336094 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13083.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106094158515 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103008489165 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209102647680 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025341 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027810 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026594 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024927 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023786 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055248 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040486 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047467 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000031 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000024 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025168 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025168 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13992.929912 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13244.737489 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13595.823194 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46213.552352 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47507.207423 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46845.248826 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12583.867511 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11609.743295 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12145.907145 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1902,38 +1876,38 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7299586 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5849815 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 347289 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4589899 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3862662 # Number of BTB hits +system.cpu1.branchPred.lookups 7296861 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5846678 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 347662 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4742078 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3857406 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.155708 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 691728 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34987 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 81.344212 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 691724 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35172 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25535708 # DTB read hits -system.cpu1.dtb.read_misses 37819 # DTB read misses -system.cpu1.dtb.write_hits 5832824 # DTB write hits -system.cpu1.dtb.write_misses 9748 # DTB write misses +system.cpu1.dtb.read_hits 25545961 # DTB read hits +system.cpu1.dtb.read_misses 37652 # DTB read misses +system.cpu1.dtb.write_hits 5843070 # DTB write hits +system.cpu1.dtb.write_misses 9833 # DTB write misses system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2100 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5607 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2149 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25573527 # DTB read accesses -system.cpu1.dtb.write_accesses 5842572 # DTB write accesses +system.cpu1.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25583613 # DTB read accesses +system.cpu1.dtb.write_accesses 5852903 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31368532 # DTB hits -system.cpu1.dtb.misses 47567 # DTB misses -system.cpu1.dtb.accesses 31416099 # DTB accesses -system.cpu1.itb.inst_hits 5790816 # ITB inst hits -system.cpu1.itb.inst_misses 7158 # ITB inst misses +system.cpu1.dtb.hits 31389031 # DTB hits +system.cpu1.dtb.misses 47485 # DTB misses +system.cpu1.dtb.accesses 31436516 # DTB accesses +system.cpu1.itb.inst_hits 5792513 # ITB inst hits +system.cpu1.itb.inst_misses 7242 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1942,284 +1916,284 @@ system.cpu1.itb.flush_tlb 255 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2684 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2667 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1580 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1547 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5797974 # ITB inst accesses -system.cpu1.itb.hits 5790816 # DTB hits -system.cpu1.itb.misses 7158 # DTB misses -system.cpu1.itb.accesses 5797974 # DTB accesses -system.cpu1.numCycles 235384601 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5799755 # ITB inst accesses +system.cpu1.itb.hits 5792513 # DTB hits +system.cpu1.itb.misses 7242 # DTB misses +system.cpu1.itb.accesses 5799755 # DTB accesses +system.cpu1.numCycles 235437063 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14589178 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46084175 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7299586 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4554390 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10179964 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2322435 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82610 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 48394674 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1151 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1760 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 51069 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1300436 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5788667 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 351586 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2955 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76205210 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.749083 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.107109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14594322 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46143705 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7296861 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4549130 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10187153 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2325105 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 84075 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 48390355 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1006 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1773 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 50802 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1299927 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 134 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5790405 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 352119 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3045 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76215873 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.749895 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.108619 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66032287 86.65% 86.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 647062 0.85% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 866139 1.14% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1142625 1.50% 90.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1039142 1.36% 91.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 573208 0.75% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1303078 1.71% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 377648 0.50% 94.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4224021 5.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66035998 86.64% 86.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 646269 0.85% 87.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 866115 1.14% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1144603 1.50% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1038380 1.36% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 570616 0.75% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1298592 1.70% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 378941 0.50% 94.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4236359 5.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76205210 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.031011 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.195782 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15588837 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 49317422 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9252055 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 521656 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1523167 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 986244 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 83403 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54452083 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 278013 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1523167 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16469267 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19674049 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 26510190 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8818021 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3208448 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51956781 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13421 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 604219 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2079670 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 451 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 54191440 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237039699 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 219510796 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 4998 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 40313487 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13877953 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 415796 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 370913 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6599828 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9995387 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6641278 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 924791 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1180275 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 48354458 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1004264 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62036555 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93414 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9463744 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23885542 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 245582 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76205210 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.814072 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.522064 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76215873 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030993 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.195992 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15595502 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49311936 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9258524 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 522439 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1525385 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 986467 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 83299 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54522655 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 277301 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1525385 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16476975 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19655955 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 26515105 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8823591 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3216801 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 52024243 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13429 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 607553 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2083322 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 488 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 54254654 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237368382 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 219812592 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5012 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 40368418 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13886236 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 416636 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 371803 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6618695 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10010762 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6654363 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 928897 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1221940 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 48420965 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1005597 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62096685 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94311 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9477685 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23931706 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 245448 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76215873 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.814747 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.522121 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53886192 70.71% 70.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6968313 9.14% 79.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3603419 4.73% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3067011 4.02% 88.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6180907 8.11% 96.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1416351 1.86% 98.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 790440 1.04% 99.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 228268 0.30% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 64309 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53862159 70.67% 70.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6987914 9.17% 79.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3609115 4.74% 84.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3073312 4.03% 88.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6185840 8.12% 96.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1415029 1.86% 98.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 789705 1.04% 99.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 228522 0.30% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 64277 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76205210 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76215873 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29954 0.68% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 6 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4154847 94.70% 95.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 202692 4.62% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 30122 0.69% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4155854 94.74% 95.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 200598 4.57% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 197719 0.32% 0.32% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 29431617 47.44% 47.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46723 0.08% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 843 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26206761 42.24% 90.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6152865 9.92% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 197857 0.32% 0.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 29468242 47.46% 47.77% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46687 0.08% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 846 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26218549 42.22% 90.07% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6164475 9.93% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62036555 # Type of FU issued -system.cpu1.iq.rate 0.263554 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4387499 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.070724 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 204795562 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58831312 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 43493604 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11047 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6062 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4926 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 66220464 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5871 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 319800 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 62096685 # Type of FU issued +system.cpu1.iq.rate 0.263751 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4386578 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.070641 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 204926211 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58913069 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 43552448 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11222 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6050 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4957 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 66279422 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5984 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 320383 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2036379 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2915 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15518 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 769053 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2041284 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2958 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15466 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 770955 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16877667 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 333288 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16877302 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 331906 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1523167 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14985510 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 225691 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 49480647 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96107 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9995387 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6641278 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 719443 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50947 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6143 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15518 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 171517 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 135143 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 306660 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 61000330 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25886068 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1036225 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1525385 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14957873 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 224833 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 49549209 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 95185 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 10010762 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6654363 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 720304 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50705 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4281 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15466 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 171203 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 135670 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 306873 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 61058870 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25897367 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1037815 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 121925 # number of nop insts executed -system.cpu1.iew.exec_refs 31986182 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5823905 # Number of branches executed -system.cpu1.iew.exec_stores 6100114 # Number of stores executed -system.cpu1.iew.exec_rate 0.259152 # Inst execution rate -system.cpu1.iew.wb_sent 60530443 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 43498530 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24164344 # num instructions producing a value -system.cpu1.iew.wb_consumers 44485345 # num instructions consuming a value +system.cpu1.iew.exec_nop 122647 # number of nop insts executed +system.cpu1.iew.exec_refs 32008147 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5821795 # Number of branches executed +system.cpu1.iew.exec_stores 6110780 # Number of stores executed +system.cpu1.iew.exec_rate 0.259343 # Inst execution rate +system.cpu1.iew.wb_sent 60589807 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 43557405 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24211075 # num instructions producing a value +system.cpu1.iew.wb_consumers 44594441 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.184798 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.543198 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.185007 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.542917 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9351616 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 758682 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 265186 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74682043 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.531552 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.520144 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9363446 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 760149 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 265641 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74690488 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.532256 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.520816 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60574973 81.11% 81.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6925092 9.27% 90.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1956264 2.62% 93.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1088628 1.46% 94.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1022152 1.37% 95.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 532797 0.71% 96.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 718663 0.96% 97.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 378466 0.51% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1485008 1.99% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60561931 81.08% 81.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6932594 9.28% 90.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1961063 2.63% 92.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1092193 1.46% 94.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1024970 1.37% 95.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 536622 0.72% 96.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 713910 0.96% 97.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 380912 0.51% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1486293 1.99% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74682043 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 31143561 # Number of instructions committed -system.cpu1.commit.committedOps 39697401 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74690488 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31194382 # Number of instructions committed +system.cpu1.commit.committedOps 39754477 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13831233 # Number of memory references committed -system.cpu1.commit.loads 7959008 # Number of loads committed -system.cpu1.commit.membars 199700 # Number of memory barriers committed -system.cpu1.commit.branches 5073252 # Number of branches committed -system.cpu1.commit.fp_insts 4858 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 35121772 # Number of committed integer instructions. -system.cpu1.commit.function_calls 494294 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1485008 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13852886 # Number of memory references committed +system.cpu1.commit.loads 7969478 # Number of loads committed +system.cpu1.commit.membars 200339 # Number of memory barriers committed +system.cpu1.commit.branches 5070949 # Number of branches committed +system.cpu1.commit.fp_insts 4906 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 35178713 # Number of committed integer instructions. +system.cpu1.commit.function_calls 493679 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1486293 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 121317994 # The number of ROB reads -system.cpu1.rob.rob_writes 99664484 # The number of ROB writes -system.cpu1.timesIdled 865516 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159179391 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2318646728 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 31060678 # Number of Instructions Simulated -system.cpu1.committedOps 39614518 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 31060678 # Number of Instructions Simulated -system.cpu1.cpi 7.578218 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.578218 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.131957 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.131957 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 276434717 # number of integer regfile reads -system.cpu1.int_regfile_writes 44854574 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22375 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19728 # number of floating regfile writes -system.cpu1.misc_regfile_reads 15285924 # number of misc regfile reads -system.cpu1.misc_regfile_writes 428613 # number of misc regfile writes +system.cpu1.rob.rob_reads 121392021 # The number of ROB reads +system.cpu1.rob.rob_writes 99804752 # The number of ROB writes +system.cpu1.timesIdled 864703 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159221190 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2318646914 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31111502 # Number of Instructions Simulated +system.cpu1.committedOps 39671597 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 31111502 # Number of Instructions Simulated +system.cpu1.cpi 7.567525 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.567525 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.132144 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.132144 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 276724007 # number of integer regfile reads +system.cpu1.int_regfile_writes 44911737 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22398 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19708 # number of floating regfile writes +system.cpu1.misc_regfile_reads 15283998 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429459 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2234,10 +2208,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1518441783518 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1518441783518 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1518454987022 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1518454987022 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |