diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2013-03-04 23:33:47 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2013-03-04 23:33:47 -0500 |
| commit | 09b2430e95df4f744a000bac34100eeb9ebcb878 (patch) | |
| tree | 1db0ab99b4186f15335a866fd7239ba51755b7d9 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3 | |
| parent | f205d83359dfb3c4f75159f83081b5e356c3c4b4 (diff) | |
| download | gem5-09b2430e95df4f744a000bac34100eeb9ebcb878.tar.xz | |
stats: update patches for branch predictor and fetch updates.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini | 11 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | 2620 |
2 files changed, 1322 insertions, 1309 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 9fab0b34a..4166fc5d7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -10,21 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -1029,6 +1029,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 73a40b4c9..8c9cf8058 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,148 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.541289 # Number of seconds simulated -sim_ticks 2541288973500 # Number of ticks simulated -final_tick 2541288973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.541288 # Number of seconds simulated +sim_ticks 2541288206500 # Number of ticks simulated +final_tick 2541288206500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61532 # Simulator instruction rate (inst/s) -host_op_rate 79175 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2592785663 # Simulator tick rate (ticks/s) -host_mem_usage 411940 # Number of bytes of host memory used -host_seconds 980.14 # Real time elapsed on the host -sim_insts 60309889 # Number of instructions simulated -sim_ops 77602313 # Number of ops (including micro ops) simulated +host_inst_rate 64704 # Simulator instruction rate (inst/s) +host_op_rate 83256 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2726411009 # Simulator tick rate (ticks/s) +host_mem_usage 408332 # Number of bytes of host memory used +host_seconds 932.10 # Real time elapsed on the host +sim_insts 60310239 # Number of instructions simulated +sim_ops 77602695 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 501184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4156432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 298496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4937244 # Number of bytes read from this memory -system.physmem.bytes_read::total 131006380 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 501184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 298496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784960 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1345340 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1670772 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801072 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 503232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4160720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 298048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4933980 # Number of bytes read from this memory +system.physmem.bytes_read::total 131009132 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 503232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 298048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 801280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1345260 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1670852 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802288 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7831 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 64978 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4664 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77151 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293479 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59140 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336335 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417693 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813168 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47657126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 197216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1635561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 117459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1942811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51551154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 197216 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 117459 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314675 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489386 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 529393 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 657451 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2676229 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47657126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 197216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2164953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 117459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2600262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54227384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293479 # Total number of read requests seen -system.physmem.writeReqs 813168 # Total number of write requests seen -system.physmem.cpureqs 218447 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978782656 # Total number of bytes read from memory -system.physmem.bytesWritten 52042752 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131006380 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6801072 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955730 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955563 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956167 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955526 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956037 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955427 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955317 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955983 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50411 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50432 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50185 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50857 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50806 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51249 # Track writes on a per bank basis +system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7863 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 65045 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4657 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77100 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293522 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 336315 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 417713 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813187 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47657140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 198022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1637248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 117282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1941527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51552253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 198022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 117282 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315305 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489865 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529361 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 657482 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2676709 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47657140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 198022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2166610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 117282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2599009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54228961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293522 # Total number of read requests seen +system.physmem.writeReqs 813187 # Total number of write requests seen +system.physmem.cpureqs 218489 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978785408 # Total number of bytes read from memory +system.physmem.bytesWritten 52043968 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131009132 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6802288 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4667 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956266 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955445 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956096 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955614 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955324 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955982 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50414 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50430 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50187 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51363 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50809 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51186 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51250 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50729 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51233 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50633 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1856346 # Number of times wr buffer was full causing retry -system.physmem.totGap 2541287786000 # Total gap between requests +system.physmem.numWrRetry 1856598 # Number of times wr buffer was full causing retry +system.physmem.totGap 2541287063000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154620 # Categorize read packet sizes +system.physmem.readPktSize::6 154663 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754028 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59140 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1054883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 992061 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961934 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3604876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2698984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 109990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59159 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1054970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 992041 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3604913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2698919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 109994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -156,46 +168,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2910 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35346 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35291 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32476 # What write queue length does an incoming req see -system.physmem.totQLat 346721486500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 439895947750 # Sum of mem lat for all requests -system.physmem.totBusLat 76467345000 # Total cycles spent in databus access -system.physmem.totBankLat 16707116250 # Total cycles spent in bank access -system.physmem.avgQLat 22671.21 # Average queueing delay per request +system.physmem.wrQLenPdf::18 35258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32483 # What write queue length does an incoming req see +system.physmem.totQLat 346675714750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 439850413500 # Sum of mem lat for all requests +system.physmem.totBusLat 76467555000 # Total cycles spent in databus access +system.physmem.totBankLat 16707143750 # Total cycles spent in bank access +system.physmem.avgQLat 22668.16 # Average queueing delay per request system.physmem.avgBankLat 1092.43 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28763.65 # Average memory access latency +system.physmem.avgMemAccLat 28760.59 # Average memory access latency system.physmem.avgRdBW 385.15 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.55 # Average consumed read bandwidth in MB/s @@ -203,243 +215,235 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.13 # Average write queue length over time -system.physmem.readRowHits 15218362 # Number of row buffer hits during reads -system.physmem.writeRowHits 794635 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.14 # Average write queue length over time +system.physmem.readRowHits 15218363 # Number of row buffer hits during reads +system.physmem.writeRowHits 794663 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes -system.physmem.avgGap 157778.82 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64388 # number of replacements -system.l2c.tagsinuse 51386.157207 # Cycle average of tags in use -system.l2c.total_refs 1906213 # Total number of references to valid blocks. -system.l2c.sampled_refs 129781 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.687920 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2505304860500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36943.345859 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 11.980136 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5122.722111 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3272.415541 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 10.482410 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3080.689127 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2944.521672 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563711 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000183 # Average percentage of cache occupancy +system.physmem.avgGap 157778.17 # Average gap between requests +system.l2c.replacements 64431 # number of replacements +system.l2c.tagsinuse 51403.772051 # Cycle average of tags in use +system.l2c.total_refs 1904252 # Total number of references to valid blocks. +system.l2c.sampled_refs 129822 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.668176 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2505297860000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36947.477101 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 17.181776 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.004228 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5147.781121 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3278.488158 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 8.683561 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3058.770363 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2945.385742 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563774 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000262 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078167 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.049933 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000160 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.047008 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044930 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784091 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 32856 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7561 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 491369 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 213716 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30962 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7078 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 479886 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 173939 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1437367 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608382 # number of Writeback hits -system.l2c.Writeback_hits::total 608382 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 20 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits +system.l2c.occ_percent::cpu0.inst 0.078549 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.050026 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000133 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.046673 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.044943 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784359 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32227 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7171 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 490580 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 213578 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30476 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6774 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 480341 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 174067 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435214 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608440 # number of Writeback hits +system.l2c.Writeback_hits::total 608440 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57851 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55061 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112912 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32856 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7561 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 491369 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 271567 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30962 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7078 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 479886 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 229000 # number of demand (read+write) hits -system.l2c.demand_hits::total 1550279 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32856 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7561 # number of overall hits -system.l2c.overall_hits::cpu0.inst 491369 # number of overall hits -system.l2c.overall_hits::cpu0.data 271567 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30962 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7078 # number of overall hits -system.l2c.overall_hits::cpu1.inst 479886 # number of overall hits -system.l2c.overall_hits::cpu1.data 229000 # number of overall hits -system.l2c.overall_hits::total 1550279 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 25 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7722 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6085 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4670 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4619 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1541 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1365 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2906 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 59871 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 73351 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133222 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7722 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 65956 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4670 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 77970 # 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number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 826500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 270381000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 269029500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1311738500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 205000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 205500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 410500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3130049500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3648768000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6778817500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1696500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025756 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015789 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987188 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.986985 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.987092 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508580 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571216 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541258 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000760 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.195296 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.253934 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091573 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000760 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.195296 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.253934 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091573 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44235.683758 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45743.111981 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44273.292281 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94648810575 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95938677921 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 190592539326 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027591 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025787 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015847 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988372 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988448 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.988408 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508840 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571050 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541281 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.195537 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.253689 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091706 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.195537 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.253689 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091706 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44257.251609 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46034.955512 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44333.289689 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10073.116484 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.874398 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39806.414207 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37287.888795 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38419.733648 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10052.097882 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.130045 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39846.195494 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37287.299468 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38438.418461 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40251.394129 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37804.827188 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39309.990960 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40251.394129 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37804.827188 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39309.990960 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -622,155 +634,155 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7614306 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6072650 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 380012 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4955572 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4051897 # Number of BTB hits +system.cpu0.branchPred.lookups 7613725 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6072642 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 379429 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4956500 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4052223 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.764466 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 730604 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39458 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.755735 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 731018 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26054511 # DTB read hits -system.cpu0.dtb.read_misses 40169 # DTB read misses -system.cpu0.dtb.write_hits 5887052 # DTB write hits -system.cpu0.dtb.write_misses 9355 # DTB write misses +system.cpu0.dtb.read_hits 26054269 # DTB read hits +system.cpu0.dtb.read_misses 40148 # DTB read misses +system.cpu0.dtb.write_hits 5888543 # DTB write hits +system.cpu0.dtb.write_misses 9328 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 772 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5627 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1395 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1467 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 272 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26094680 # DTB read accesses -system.cpu0.dtb.write_accesses 5896407 # DTB write accesses +system.cpu0.dtb.perms_faults 635 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26094417 # DTB read accesses +system.cpu0.dtb.write_accesses 5897871 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31941563 # DTB hits -system.cpu0.dtb.misses 49524 # DTB misses -system.cpu0.dtb.accesses 31991087 # DTB accesses -system.cpu0.itb.inst_hits 6108612 # ITB inst hits -system.cpu0.itb.inst_misses 7590 # ITB inst misses +system.cpu0.dtb.hits 31942812 # DTB hits +system.cpu0.dtb.misses 49476 # DTB misses +system.cpu0.dtb.accesses 31992288 # DTB accesses +system.cpu0.itb.inst_hits 6107608 # ITB inst hits +system.cpu0.itb.inst_misses 7459 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 772 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2620 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1574 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1567 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6116202 # ITB inst accesses -system.cpu0.itb.hits 6108612 # DTB hits -system.cpu0.itb.misses 7590 # DTB misses -system.cpu0.itb.accesses 6116202 # DTB accesses -system.cpu0.numCycles 239083473 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6115067 # ITB inst accesses +system.cpu0.itb.hits 6107608 # DTB hits +system.cpu0.itb.misses 7459 # DTB misses +system.cpu0.itb.accesses 6115067 # DTB accesses +system.cpu0.numCycles 239065725 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15485568 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47808985 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7614306 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4782501 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10601732 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2558486 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 88790 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49524477 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1650 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2036 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 49879 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 101149 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 238 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6106475 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 397023 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3536 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77625046 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.761902 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.119269 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15475182 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47810378 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7613725 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4783241 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10599303 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2556412 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 92588 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49524214 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1680 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1986 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 51259 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101215 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 252 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6105640 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 396425 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3088 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77615764 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.762044 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.119690 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67030834 86.35% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 688188 0.89% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 885369 1.14% 88.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1227712 1.58% 89.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1142460 1.47% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 576598 0.74% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1323002 1.70% 93.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 397300 0.51% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4353583 5.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67024086 86.35% 86.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 687549 0.89% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 884780 1.14% 88.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1227446 1.58% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1139052 1.47% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 576391 0.74% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1322616 1.70% 93.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 397461 0.51% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4356383 5.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77625046 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 77615764 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.branchRate 0.031848 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.199968 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16533020 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49254882 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9604301 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 549145 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1681530 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1023916 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90477 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56278023 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 301850 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1681530 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17466172 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18987810 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27019642 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9149380 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3318436 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53462165 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13485 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 622165 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2153440 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 547 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55626962 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 243359254 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243311426 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 47828 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40393377 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15233585 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 429285 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 381212 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6745205 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10341737 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6773194 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1063883 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1311451 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49606690 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1043899 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63171257 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 95885 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10502922 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26495317 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 267486 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77625046 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.813800 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.519198 # Number of insts issued each cycle +system.cpu0.fetch.rate 0.199988 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16521961 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49260251 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9602479 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 548826 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1680126 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1023427 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90450 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56271590 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 301516 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1680126 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17454704 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18993172 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27018669 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9147780 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3319243 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53454491 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13507 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 621630 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2155035 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 566 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55623215 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 243327513 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 243280007 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 47506 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40387894 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15235321 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 429274 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 381163 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6745844 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10343403 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6774259 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1062911 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1310407 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49609262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1043693 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63170275 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 95774 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10510467 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26507766 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 267313 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77615764 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.813885 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519252 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54791410 70.58% 70.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7205110 9.28% 79.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3690427 4.75% 84.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3148985 4.06% 88.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6276259 8.09% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1405987 1.81% 98.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 810578 1.04% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 230421 0.30% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 65869 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54780189 70.58% 70.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7210578 9.29% 79.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3685843 4.75% 84.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3149398 4.06% 88.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6278761 8.09% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1404530 1.81% 98.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 809241 1.04% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 231115 0.30% 99.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 66109 0.09% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77625046 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77615764 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29841 0.67% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29823 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available @@ -798,13 +810,13 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4229016 94.75% 95.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 204408 4.58% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4228133 94.76% 95.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 204148 4.58% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195533 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29939610 47.39% 47.70% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46892 0.07% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 195616 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29937335 47.39% 47.70% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46928 0.07% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued @@ -817,485 +829,485 @@ system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Ty system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1207 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1205 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26772486 42.38% 90.16% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6215505 9.84% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26771956 42.38% 90.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6217218 9.84% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63171257 # Type of FU issued -system.cpu0.iq.rate 0.264223 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4463267 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070653 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208563844 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61162491 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44139446 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12207 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6555 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5480 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67432539 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6452 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 322060 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63170275 # Type of FU issued +system.cpu0.iq.rate 0.264238 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4462107 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070636 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208551330 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61172484 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44142185 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12154 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6481 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5464 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67430354 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6412 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 323195 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2267012 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3473 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16117 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 886206 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2268860 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3534 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16121 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 886667 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17168110 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367587 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17166750 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367684 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1681530 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14225625 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 233605 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50767973 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 106118 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10341737 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6773194 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 742853 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 56514 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3354 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16117 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186814 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 146956 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 333770 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62000418 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26414197 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1170839 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1680126 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14230285 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 233349 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50770143 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105944 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10343403 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6774259 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 742754 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56167 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3335 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16121 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186307 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 146952 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 333259 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62002420 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26414016 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1167855 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117384 # number of nop insts executed -system.cpu0.iew.exec_refs 32572588 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6026978 # Number of branches executed -system.cpu0.iew.exec_stores 6158391 # Number of stores executed -system.cpu0.iew.exec_rate 0.259325 # Inst execution rate -system.cpu0.iew.wb_sent 61472286 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44144926 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24307807 # num instructions producing a value -system.cpu0.iew.wb_consumers 44674584 # num instructions consuming a value +system.cpu0.iew.exec_nop 117188 # number of nop insts executed +system.cpu0.iew.exec_refs 32573974 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6027717 # Number of branches executed +system.cpu0.iew.exec_stores 6159958 # Number of stores executed +system.cpu0.iew.exec_rate 0.259353 # Inst execution rate +system.cpu0.iew.wb_sent 61473665 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44147649 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24301400 # num instructions producing a value +system.cpu0.iew.wb_consumers 44653762 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184642 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544108 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184667 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544218 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10350620 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 776413 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 290797 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75943516 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.525572 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.508217 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10356873 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 776380 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 290234 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75935638 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.525589 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.508198 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61731521 81.29% 81.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6903711 9.09% 90.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2039504 2.69% 93.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1132941 1.49% 94.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1032773 1.36% 95.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 549051 0.72% 96.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 702703 0.93% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 370837 0.49% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1480475 1.95% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61722766 81.28% 81.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6904437 9.09% 90.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2039889 2.69% 93.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1134781 1.49% 94.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1032872 1.36% 95.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 547307 0.72% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 702356 0.92% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 369637 0.49% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1481593 1.95% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75943516 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31268406 # Number of instructions committed -system.cpu0.commit.committedOps 39913766 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75935638 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31265183 # Number of instructions committed +system.cpu0.commit.committedOps 39910920 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13961713 # Number of memory references committed -system.cpu0.commit.loads 8074725 # Number of loads committed -system.cpu0.commit.membars 212370 # Number of memory barriers committed -system.cpu0.commit.branches 5203416 # Number of branches committed +system.cpu0.commit.refs 13962135 # Number of memory references committed +system.cpu0.commit.loads 8074543 # Number of loads committed +system.cpu0.commit.membars 212305 # Number of memory barriers committed +system.cpu0.commit.branches 5202337 # Number of branches committed system.cpu0.commit.fp_insts 5433 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35263906 # Number of committed integer instructions. -system.cpu0.commit.function_calls 513958 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1480475 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 35261936 # Number of committed integer instructions. +system.cpu0.commit.function_calls 513908 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1481593 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123750130 # The number of ROB reads -system.cpu0.rob.rob_writes 102252787 # The number of ROB writes -system.cpu0.timesIdled 884124 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161458427 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289647904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31189179 # Number of Instructions Simulated -system.cpu0.committedOps 39834539 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31189179 # Number of Instructions Simulated -system.cpu0.cpi 7.665590 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.665590 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130453 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130453 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 280633966 # number of integer regfile reads -system.cpu0.int_regfile_writes 45420954 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22760 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19830 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15480243 # number of misc regfile reads -system.cpu0.misc_regfile_writes 429707 # number of misc regfile writes -system.cpu0.icache.replacements 984233 # number of replacements -system.cpu0.icache.tagsinuse 511.604349 # Cycle average of tags in use -system.cpu0.icache.total_refs 11036411 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984745 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.207380 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 123744681 # The number of ROB reads +system.cpu0.rob.rob_writes 102258102 # The number of ROB writes +system.cpu0.timesIdled 883709 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161449961 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289675923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31185911 # Number of Instructions Simulated +system.cpu0.committedOps 39831648 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31185911 # Number of Instructions Simulated +system.cpu0.cpi 7.665825 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.665825 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.130449 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.130449 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 280645626 # number of integer regfile reads +system.cpu0.int_regfile_writes 45419186 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22697 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19806 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15480369 # number of misc regfile reads +system.cpu0.misc_regfile_writes 429671 # number of misc regfile writes +system.cpu0.icache.replacements 983987 # number of replacements +system.cpu0.icache.tagsinuse 511.561827 # Cycle average of tags in use +system.cpu0.icache.total_refs 11034736 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984499 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.208479 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 356.507188 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 155.097161 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.696303 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.302924 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5565457 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5470954 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11036411 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5565457 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5470954 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11036411 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5565457 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5470954 # number of overall hits -system.cpu0.icache.overall_hits::total 11036411 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 540893 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 524443 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065336 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 540893 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 524443 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065336 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 540893 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 524443 # number of overall misses -system.cpu0.icache.overall_misses::total 1065336 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7322738992 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6974356493 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14297095485 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7322738992 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6974356493 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14297095485 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7322738992 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6974356493 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14297095485 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6106350 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5995397 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12101747 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6106350 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5995397 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12101747 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6106350 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5995397 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12101747 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088579 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087474 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.088032 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088579 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087474 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.088032 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088579 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087474 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.088032 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13538.239526 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13298.597737 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13420.268803 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13538.239526 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13298.597737 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13420.268803 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13538.239526 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13298.597737 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13420.268803 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4718 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 357.606132 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 153.955695 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.698449 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.300695 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999144 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5565566 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5469170 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11034736 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5565566 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5469170 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11034736 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5565566 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5469170 # number of overall hits +system.cpu0.icache.overall_hits::total 11034736 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 539949 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 524997 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1064946 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 539949 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 524997 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1064946 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 539949 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 524997 # number of overall misses +system.cpu0.icache.overall_misses::total 1064946 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7306962994 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6971237994 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14278200988 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7306962994 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6971237994 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14278200988 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7306962994 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6971237994 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14278200988 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6105515 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5994167 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12099682 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6105515 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5994167 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12099682 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6105515 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5994167 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12099682 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088436 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087585 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.088014 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088436 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087585 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.088014 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088436 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087585 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.088014 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13532.691039 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13278.624438 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13407.441305 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13532.691039 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13278.624438 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13407.441305 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13532.691039 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13278.624438 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13407.441305 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4578 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 353 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 340 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.365439 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.464706 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41212 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39352 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80564 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 41212 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39352 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 80564 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 41212 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39352 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80564 # 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number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 41021 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39404 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 80425 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 41021 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39404 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 80425 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 498928 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 485593 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 984521 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 498928 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 485593 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 984521 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 498928 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 485593 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 984521 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5964947994 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5687451995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11652399989 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5964947994 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5687451995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11652399989 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5964947994 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5687451995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11652399989 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7526000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7526000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7526000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7526000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081374 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.081374 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.081374 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11835.532475 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.532475 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.532475 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081368 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.081368 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.081368 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11835.603292 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.603292 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.603292 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643981 # number of replacements +system.cpu0.dcache.replacements 643944 # number of replacements system.cpu0.dcache.tagsinuse 511.992715 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21533340 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 644493 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.411286 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 21531615 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 644456 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.410528 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 320.784691 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 191.208024 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.626533 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.373453 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 318.816885 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 193.175830 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.622689 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.377297 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7106515 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6670987 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13777502 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3768669 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3492995 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261664 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125802 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117658 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243460 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127804 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119816 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247620 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10875184 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10163982 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21039166 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10875184 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10163982 # number of overall hits -system.cpu0.dcache.overall_hits::total 21039166 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 435450 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 315528 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 750978 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1386539 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1574618 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2961157 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6834 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6765 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13599 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1821989 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1890146 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3712135 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1821989 # 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number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 65000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 52000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 117000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 58948500358 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 66843893289 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125792393647 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 58948500358 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 66843893289 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125792393647 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7541965 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6986515 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14528480 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5155208 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5067613 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10222821 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132636 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124423 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257059 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127809 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119820 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247629 # 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number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18625662995 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33514574811 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.writebacks::writebacks 608440 # number of writebacks +system.cpu0.dcache.writebacks::total 608440 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 221787 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 143125 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 364912 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1268338 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1444026 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2712364 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 692 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 696 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1388 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1490125 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1587151 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3077276 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1490125 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1587151 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3077276 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 213622 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 172650 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386272 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119248 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129668 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248916 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6113 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6088 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12201 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 332870 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 302318 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635188 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 332870 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 302318 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635188 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2899035000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2323789000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5222824000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3973939486 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4489804935 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8463744421 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71655500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73661500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145317000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 144000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6872974486 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6813593935 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13686568421 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6872974486 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6813593935 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13686568421 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91950216500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90410818500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182361035000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14891141407 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18622831131 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33513972538 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106847737316 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109028071995 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215875809311 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028335 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024693 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026584 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106841357907 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109033649631 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215875007538 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028325 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024716 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026590 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023129 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025606 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046337 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048841 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047549 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000039 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000033 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000036 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for demand accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025590 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024349 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046091 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048965 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047481 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000047 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026215 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025084 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.025664 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026215 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025084 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.025664 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13567.853199 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13454.175531 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13517.075716 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33287.757611 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34627.697778 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33986.047507 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.009112 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12118.561790 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11890.002454 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13570.863488 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13459.536635 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13521.104300 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33324.999044 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34625.388955 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34002.412143 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11721.822346 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12099.457950 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.253258 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20647.623655 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22537.837426 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21547.271707 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20647.623655 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22537.837426 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21547.271707 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1310,154 +1322,154 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7038093 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5643597 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 344397 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4629014 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3810883 # Number of BTB hits +system.cpu1.branchPred.lookups 7039242 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5645782 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 344121 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4649860 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3812908 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 82.326020 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 671158 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34749 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 82.000490 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 671568 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34742 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25308103 # DTB read hits -system.cpu1.dtb.read_misses 36468 # DTB read misses -system.cpu1.dtb.write_hits 5825949 # DTB write hits -system.cpu1.dtb.write_misses 9352 # DTB write misses +system.cpu1.dtb.read_hits 25307959 # DTB read hits +system.cpu1.dtb.read_misses 36376 # DTB read misses +system.cpu1.dtb.write_hits 5825723 # DTB write hits +system.cpu1.dtb.write_misses 9311 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 667 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1257 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 236 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5515 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1387 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 246 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 652 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25344571 # DTB read accesses -system.cpu1.dtb.write_accesses 5835301 # DTB write accesses +system.cpu1.dtb.perms_faults 651 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25344335 # DTB read accesses +system.cpu1.dtb.write_accesses 5835034 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31134052 # DTB hits -system.cpu1.dtb.misses 45820 # DTB misses -system.cpu1.dtb.accesses 31179872 # DTB accesses -system.cpu1.itb.inst_hits 5997509 # ITB inst hits -system.cpu1.itb.inst_misses 6989 # ITB inst misses +system.cpu1.dtb.hits 31133682 # DTB hits +system.cpu1.dtb.misses 45687 # DTB misses +system.cpu1.dtb.accesses 31179369 # DTB accesses +system.cpu1.itb.inst_hits 5996114 # ITB inst hits +system.cpu1.itb.inst_misses 6834 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 667 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2597 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2600 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1435 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1401 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6004498 # ITB inst accesses -system.cpu1.itb.hits 5997509 # DTB hits -system.cpu1.itb.misses 6989 # DTB misses -system.cpu1.itb.accesses 6004498 # DTB accesses -system.cpu1.numCycles 234155519 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6002948 # ITB inst accesses +system.cpu1.itb.hits 5996114 # DTB hits +system.cpu1.itb.misses 6834 # DTB misses +system.cpu1.itb.accesses 6002948 # DTB accesses +system.cpu1.numCycles 234172204 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15142136 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46597306 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7038093 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4482041 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10279188 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2613913 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 81086 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47501023 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2061 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 42896 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 94668 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 141 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5995399 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 442650 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3270 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74933804 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.773237 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.138568 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15150430 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46599302 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7039242 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4484476 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10276938 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2612454 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 82512 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47518747 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2108 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 42921 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94711 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 94 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5994168 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 443200 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2937 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74957939 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.773072 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.138667 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64662280 86.29% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 620375 0.83% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 831799 1.11% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1204715 1.61% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1045196 1.39% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 534648 0.71% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1368616 1.83% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 351624 0.47% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4314551 5.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64688840 86.30% 86.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 619651 0.83% 87.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 831575 1.11% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1205005 1.61% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1040099 1.39% 91.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 534718 0.71% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1368218 1.83% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 351871 0.47% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4317962 5.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74933804 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030057 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199002 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16155094 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47289878 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9321974 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 458622 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1706108 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 946431 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86032 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54867135 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286067 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1706108 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17091509 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18549403 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25716073 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8765190 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3103459 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51703267 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7138 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 482463 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2122538 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 91 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53752733 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237374868 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 237332026 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42842 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 37999603 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15753129 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 403463 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 357307 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6254395 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9847442 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6700780 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 890369 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1126759 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47663057 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 942444 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60816475 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 81421 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10551432 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 27971257 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 236318 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74933804 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.811603 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521433 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74957939 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030060 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.198996 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16159118 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47313522 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9319419 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 458702 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1705045 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 945660 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85957 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54861176 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 287371 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1705045 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17094797 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18547389 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25741637 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8764339 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3102678 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51699813 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7117 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 482642 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2122595 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 48 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53761457 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237355866 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 237312988 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42878 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38005573 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15755883 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 403501 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 357316 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6247551 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9846699 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6699378 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 894839 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1124277 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47671789 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 942558 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60820762 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 80974 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10554667 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27991193 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 236389 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74957939 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.811399 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521506 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53188932 70.98% 70.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6663266 8.89% 79.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3530113 4.71% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2889463 3.86% 88.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6218055 8.30% 96.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1440706 1.92% 98.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 733706 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 209896 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59667 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53217841 71.00% 71.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6660852 8.89% 79.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3522155 4.70% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2891310 3.86% 88.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6221103 8.30% 96.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1440067 1.92% 98.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 734950 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 210065 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59596 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74933804 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74957939 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24001 0.55% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24217 0.55% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 1 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available @@ -1486,13 +1498,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4142238 94.88% 95.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 199692 4.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4143294 94.86% 95.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 200406 4.59% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 168133 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28440656 46.76% 47.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46730 0.08% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 168050 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28446121 46.77% 47.05% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46643 0.08% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.12% # Type of FU issued @@ -1505,129 +1517,129 @@ system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.12% # Ty system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 904 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 906 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26040768 42.82% 89.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6119264 10.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26040786 42.82% 89.94% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6118237 10.06% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60816475 # Type of FU issued +system.cpu1.iq.FU_type_0::total 60820762 # Type of FU issued system.cpu1.iq.rate 0.259727 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4365932 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071789 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 201049061 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59165079 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41785793 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10680 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5951 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65008639 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5635 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 303573 # Number of loads that had data forwarded from stores +system.cpu1.iq.fu_busy_cnt 4367918 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.071816 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 201083162 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59177242 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41793523 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10683 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5961 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4808 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65014989 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5641 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 303389 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2266828 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3041 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14605 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 855166 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2265840 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3135 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14672 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 854347 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16935844 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 457097 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16937147 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 456872 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1706108 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13962333 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229984 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48711452 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98533 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9847442 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6700780 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 669329 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49837 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3707 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14605 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 166001 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133612 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 299613 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59448141 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25635797 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1368334 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1705045 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 13964953 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 229910 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48720174 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98231 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9846699 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6699378 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 669323 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49676 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3736 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14672 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 165888 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133425 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 299313 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59456626 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25635805 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1364136 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105951 # number of nop insts executed -system.cpu1.iew.exec_refs 31702689 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5524822 # Number of branches executed -system.cpu1.iew.exec_stores 6066892 # Number of stores executed -system.cpu1.iew.exec_rate 0.253883 # Inst execution rate -system.cpu1.iew.wb_sent 58868959 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41790607 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22765083 # num instructions producing a value -system.cpu1.iew.wb_consumers 41748877 # num instructions consuming a value +system.cpu1.iew.exec_nop 105827 # number of nop insts executed +system.cpu1.iew.exec_refs 31702395 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5527346 # Number of branches executed +system.cpu1.iew.exec_stores 6066590 # Number of stores executed +system.cpu1.iew.exec_rate 0.253901 # Inst execution rate +system.cpu1.iew.wb_sent 58878116 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41798331 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22764679 # num instructions producing a value +system.cpu1.iew.wb_consumers 41753721 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178474 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545286 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178494 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.545213 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10475750 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 706126 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 259614 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73227696 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.516730 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.497193 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10481198 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 706169 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 259373 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73252894 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.516596 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.497283 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59700930 81.53% 81.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6668134 9.11% 90.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1908648 2.61% 93.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1011673 1.38% 94.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 958934 1.31% 95.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 524760 0.72% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 701730 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 374533 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1378354 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59734394 81.55% 81.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6658117 9.09% 90.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1908666 2.61% 93.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1009766 1.38% 94.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 959602 1.31% 95.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 525640 0.72% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 705032 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 372807 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1378870 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73227696 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29191864 # Number of instructions committed -system.cpu1.commit.committedOps 37838928 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73252894 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29195437 # Number of instructions committed +system.cpu1.commit.committedOps 37842156 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13426228 # Number of memory references committed -system.cpu1.commit.loads 7580614 # Number of loads committed -system.cpu1.commit.membars 191280 # Number of memory barriers committed -system.cpu1.commit.branches 4758264 # Number of branches committed +system.cpu1.commit.refs 13425890 # Number of memory references committed +system.cpu1.commit.loads 7580859 # Number of loads committed +system.cpu1.commit.membars 191347 # Number of memory barriers committed +system.cpu1.commit.branches 4759387 # Number of branches committed system.cpu1.commit.fp_insts 4779 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33593707 # Number of committed integer instructions. -system.cpu1.commit.function_calls 477362 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1378354 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 33596023 # Number of committed integer instructions. +system.cpu1.commit.function_calls 477418 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1378870 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119292034 # The number of ROB reads -system.cpu1.rob.rob_writes 98387822 # The number of ROB writes -system.cpu1.timesIdled 873010 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159221715 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285865988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29120710 # Number of Instructions Simulated -system.cpu1.committedOps 37767774 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29120710 # Number of Instructions Simulated -system.cpu1.cpi 8.040859 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.040859 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124365 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124365 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 269346342 # number of integer regfile reads -system.cpu1.int_regfile_writes 42878504 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22102 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14810651 # number of misc regfile reads -system.cpu1.misc_regfile_writes 402789 # number of misc regfile writes +system.cpu1.rob.rob_reads 119325211 # The number of ROB reads +system.cpu1.rob.rob_writes 98404070 # The number of ROB writes +system.cpu1.timesIdled 873125 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159214265 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285839594 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29124328 # Number of Instructions Simulated +system.cpu1.committedOps 37771047 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29124328 # Number of Instructions Simulated +system.cpu1.cpi 8.040433 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.040433 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124371 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124371 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 269378788 # number of integer regfile reads +system.cpu1.int_regfile_writes 42887039 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22080 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19702 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14812812 # number of misc regfile reads +system.cpu1.misc_regfile_writes 402828 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1642,17 +1654,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192717579972 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192717579972 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192668399444 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192668399444 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192668399444 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192668399444 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83049 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83052 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |