diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:29 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:29 -0500 |
| commit | 93c0307d418e08db609818f19f5d2b02d45e7465 (patch) | |
| tree | 1f72a6617fb4a74d904a933bc48136fa0760bd19 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3 | |
| parent | f2db2a96d181f796e6e475121f10230b9d1d007f (diff) | |
| download | gem5-93c0307d418e08db609818f19f5d2b02d45e7465.tar.xz | |
tests: Update regressions for the new kernels and various preceeding fixes.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3')
5 files changed, 2362 insertions, 2041 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 5d2c59c2a..9bcc8ea41 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain -atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +atags_addr=134217728 +boot_loader=/dist/binaries/boot_emm.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename= +dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 -flags_addr=268435504 -gic_cpu_addr=520093952 +flags_addr=469827632 +gic_cpu_addr=738205696 have_generic_timer=false have_large_asid_64=false have_lpae=false @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 -load_offset=0 -machine_type=RealView_PBX +load_offset=2147483648 +machine_type=VExpress_EMM mem_mode=timing -mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +mem_ranges=2147483648:2415919103 +memories=system.realview.vram system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -53,14 +53,14 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[0] +system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 -ranges=268435456:520093695 1073741824:1610612735 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -654,6 +654,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu0.istage2_mmu] @@ -1180,6 +1181,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu1.istage2_mmu] @@ -1251,15 +1253,16 @@ type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 -use_default_range=false +use_default_range=true width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] type=BaseCache children=tags -addr_ranges=0:134217727 +addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain eventq_index=0 @@ -1278,8 +1281,8 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[26] -mem_side=system.membus.slave[2] +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] [system.iocache.tags] type=LRU @@ -1314,7 +1317,7 @@ tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.l2c.tags] type=LRU @@ -1337,8 +1340,8 @@ system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.system_port system.l2c.mem_side system.iocache.mem_side +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -1394,6 +1397,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -1403,7 +1407,7 @@ mem_sched_policy=frfcfs min_writes_per_switch=16 null=false page_policy=open_adaptive -range=0:134217727 +range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1432,46 +1436,37 @@ tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 -port=system.membus.master[6] +port=system.membus.master[5] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=0 +pci_cfg_base=805306368 pci_cfg_gen_offsets=false pci_io_base=0 system=system -[system.realview.a9scu] -type=A9SCU -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=520093696 -pio_latency=100000 -system=system -pio=system.membus.master[4] - [system.realview.aaci_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268451840 +pio_addr=470024192 pio_latency=100000 system=system -pio=system.iobus.master[21] +pio=system.iobus.master[18] [system.realview.cf_ctrl] type=IdeController -BAR0=402653184 +BAR0=471465984 BAR0LegacyIO=true -BAR0Size=16 -BAR1=402653440 +BAR0Size=256 +BAR1=471466240 BAR1LegacyIO=true -BAR1Size=1 +BAR1Size=4096 BAR2=1 BAR2LegacyIO=false BAR2Size=8 @@ -1541,18 +1536,18 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 -disks=system.cf0 +disks= eventq_index=0 -io_shift=1 +io_shift=2 pci_bus=2 -pci_dev=7 +pci_dev=0 pci_func=0 pio_latency=30000 platform=system.realview system=system -config=system.iobus.master[8] +config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.clcd] type=Pl111 @@ -1561,8 +1556,8 @@ clk_domain=system.clk_domain enable_capture=true eventq_index=0 gic=system.realview.gic -int_num=55 -pio_addr=268566528 +int_num=46 +pio_addr=471793664 pio_latency=10000 pixel_clock=41667 system=system @@ -1570,51 +1565,129 @@ vnc=system.vncserver dma=system.iobus.slave[1] pio=system.iobus.master[4] -[system.realview.dmac_fake] -type=AmbaFake -amba_id=0 +[system.realview.energy_ctrl] +type=EnergyCtrl clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler eventq_index=0 -ignore_access=false -pio_addr=268632064 +pio_addr=470286336 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[22] -[system.realview.energy_ctrl] -type=EnergyCtrl +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 clk_domain=system.clk_domain -dvfs_handler=system.dvfs_handler +config_latency=20000 eventq_index=0 -pio_addr=268496896 -pio_latency=100000 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] pio=system.iobus.master[25] -[system.realview.flash_fake] -type=IsaFake -clk_domain=system.clk_domain +[system.realview.generic_timer] +type=GenericTimer eventq_index=0 -fake_mem=true -pio_addr=1073741824 -pio_latency=100000 -pio_size=536870912 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 +gic=system.realview.gic +int_num=29 system=system -update_data=false -warn_access= -pio=system.iobus.master[24] [system.realview.gic] type=Pl390 clk_domain=system.clk_domain -cpu_addr=520093952 +cpu_addr=738205696 cpu_pio_delay=10000 -dist_addr=520097792 +dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 int_latency=10000 @@ -1624,38 +1697,111 @@ platform=system.realview system=system pio=system.membus.master[2] -[system.realview.gpio0_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268513280 -pio_latency=100000 -system=system -pio=system.iobus.master[16] - -[system.realview.gpio1_fake] -type=AmbaFake -amba_id=0 +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 clk_domain=system.clk_domain +enable_capture=true eventq_index=0 -ignore_access=false -pio_addr=268517376 -pio_latency=100000 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 system=system -pio=system.iobus.master[17] +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] -[system.realview.gpio2_fake] -type=AmbaFake -amba_id=0 +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 eventq_index=0 -ignore_access=false -pio_addr=268521472 -pio_latency=100000 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview system=system -pio=system.iobus.master[18] +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] [system.realview.kmi0] type=Pl050 @@ -1664,13 +1810,13 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=52 +int_num=44 is_mouse=false -pio_addr=268460032 +pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.kmi1] type=Pl050 @@ -1679,20 +1825,20 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=53 +int_num=45 is_mouse=true -pio_addr=268464128 +pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=false -pio_addr=520101888 +pio_addr=739246080 pio_latency=100000 pio_size=4095 ret_bad_addr=false @@ -1703,7 +1849,25 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[3] +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer @@ -1712,10 +1876,10 @@ eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 -pio_addr=520095232 +pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[3] [system.realview.mmc_fake] type=AmbaFake @@ -1723,10 +1887,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268455936 +pio_addr=470089728 pio_latency=100000 system=system -pio=system.iobus.master[22] +pio=system.iobus.master[21] [system.realview.nvmem] type=SimpleMemory @@ -1738,18 +1902,30 @@ in_addr_map=true latency=30000 latency_var=0 null=false -range=2147483648:2214592511 +range=0:67108863 port=system.membus.master[1] +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain eventq_index=0 -idreg=0 -pio_addr=268435456 +idreg=35979264 +pio_addr=469827584 pio_latency=100000 -proc_id0=201326592 -proc_id1=201327138 +proc_id0=335544320 +proc_id1=335544320 system=system pio=system.iobus.master[1] @@ -1760,34 +1936,12 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=42 -pio_addr=268529664 +int_num=36 +pio_addr=471269376 pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[23] - -[system.realview.sci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268492800 -pio_latency=100000 -system=system -pio=system.iobus.master[20] - -[system.realview.smc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=269357056 -pio_latency=100000 -system=system -pio=system.iobus.master[13] +pio=system.iobus.master[10] [system.realview.sp810_fake] type=AmbaFake @@ -1795,21 +1949,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=true -pio_addr=268439552 -pio_latency=100000 -system=system -pio=system.iobus.master[14] - -[system.realview.ssp_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268488704 +pio_addr=469893120 pio_latency=100000 system=system -pio=system.iobus.master[19] +pio=system.iobus.master[16] [system.realview.timer0] type=Sp804 @@ -1819,9 +1962,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=36 -int_num1=36 -pio_addr=268505088 +int_num0=34 +int_num1=34 +pio_addr=470876160 pio_latency=100000 system=system pio=system.iobus.master[2] @@ -1834,9 +1977,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=37 -int_num1=37 -pio_addr=268509184 +int_num0=35 +int_num1=35 +pio_addr=470941696 pio_latency=100000 system=system pio=system.iobus.master[3] @@ -1848,8 +1991,8 @@ end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=44 -pio_addr=268472320 +int_num=37 +pio_addr=470351872 pio_latency=100000 platform=system.realview system=system @@ -1862,10 +2005,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268476416 +pio_addr=470417408 pio_latency=100000 system=system -pio=system.iobus.master[10] +pio=system.iobus.master[13] [system.realview.uart2_fake] type=AmbaFake @@ -1873,10 +2016,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268480512 +pio_addr=470482944 pio_latency=100000 system=system -pio=system.iobus.master[11] +pio=system.iobus.master[14] [system.realview.uart3_fake] type=AmbaFake @@ -1884,10 +2027,54 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268484608 +pio_addr=470548480 pio_latency=100000 system=system -pio=system.iobus.master[12] +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] [system.realview.watchdog_fake] type=AmbaFake @@ -1895,10 +2082,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268500992 +pio_addr=470745088 pio_latency=100000 system=system -pio=system.iobus.master[15] +pio=system.iobus.master[17] [system.terminal] type=Terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr index 5150881aa..adbb69884 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr @@ -1,24 +1,54 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. +warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] +warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: LCD dual screen mode not supported -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4] +warn: CP14 unimplemented crn[8], opc1[4], crm[12], opc2[0] +warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] +warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] +warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1] +warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[5] +warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1] +warn: Returning zero for read from miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr +warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[6] +warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] +warn: CP14 unimplemented crn[4], opc1[5], crm[12], opc2[1] +warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0] +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: instruction 'mcr bpiall' unimplemented warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout index 74b77ce44..4796b8caa 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:22:42 -gem5 started Jun 21 2014 21:27:42 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:21:54 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x60c5390 0x60c5390 - 0: system.cpu1.isa: ISA system set to: 0x60c5390 0x60c5390 + 0: system.cpu0.isa: ISA system set to: 0x422cb00 0x422cb00 + 0: system.cpu1.isa: ISA system set to: 0x422cb00 0x422cb00 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 6d01b379d..9eb62fabd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,154 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.539695 # Number of seconds simulated -sim_ticks 2539695141000 # Number of ticks simulated -final_tick 2539695141000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.804329 # Number of seconds simulated +sim_ticks 2804328920000 # Number of ticks simulated +final_tick 2804328920000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66572 # Simulator instruction rate (inst/s) -host_op_rate 80202 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2802822069 # Simulator tick rate (ticks/s) -host_mem_usage 418352 # Number of bytes of host memory used -host_seconds 906.12 # Real time elapsed on the host -sim_insts 60322278 # Number of instructions simulated -sim_ops 72673006 # Number of ops (including micro ops) simulated +host_inst_rate 115537 # Simulator instruction rate (inst/s) +host_op_rate 140231 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2770199215 # Simulator tick rate (ticks/s) +host_mem_usage 563788 # Number of bytes of host memory used +host_seconds 1012.32 # Real time elapsed on the host +sim_insts 116960928 # Number of instructions simulated +sim_ops 141958852 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 4992 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 471296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3922776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 314048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5167104 # Number of bytes read from this memory -system.physmem.bytes_read::total 130987352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 471296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 314048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 785344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3775232 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1328636 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1687436 # Number of bytes written to this memory -system.physmem.bytes_written::total 6791304 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 739456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5170528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 635584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4648772 # Number of bytes read from this memory +system.physmem.bytes_read::total 11204324 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 739456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 635584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1375040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6110656 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory +system.physmem.bytes_written::total 8446516 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 78 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7364 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 61319 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 80736 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293167 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58988 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 332159 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 421859 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813006 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47687034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 185572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1544585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 123656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2034537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51576014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 185572 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 123656 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 309228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1486490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 523148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 664425 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2674063 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1486490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47687034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 185572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2067733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 123656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2698962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54250077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293167 # Number of read requests accepted -system.physmem.writeReqs 813006 # Number of write requests accepted -system.physmem.readBursts 15293167 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813006 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 975220032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3542656 # Total number of bytes read from write queue -system.physmem.bytesWritten 6827904 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130987352 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6791304 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 55354 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706297 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4647 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 954783 # Per bank write bursts -system.physmem.perBankRdBursts::1 950591 # Per bank write bursts -system.physmem.perBankRdBursts::2 950729 # Per bank write bursts -system.physmem.perBankRdBursts::3 950904 # Per bank write bursts -system.physmem.perBankRdBursts::4 954888 # Per bank write bursts -system.physmem.perBankRdBursts::5 951868 # Per bank write bursts -system.physmem.perBankRdBursts::6 951800 # Per bank write bursts -system.physmem.perBankRdBursts::7 951730 # Per bank write bursts -system.physmem.perBankRdBursts::8 955391 # Per bank write bursts -system.physmem.perBankRdBursts::9 951917 # Per bank write bursts -system.physmem.perBankRdBursts::10 951458 # Per bank write bursts -system.physmem.perBankRdBursts::11 951066 # Per bank write bursts -system.physmem.perBankRdBursts::12 955340 # Per bank write bursts -system.physmem.perBankRdBursts::13 951888 # Per bank write bursts -system.physmem.perBankRdBursts::14 951979 # Per bank write bursts -system.physmem.perBankRdBursts::15 951481 # Per bank write bursts -system.physmem.perBankWrBursts::0 6606 # Per bank write bursts -system.physmem.perBankWrBursts::1 6389 # Per bank write bursts -system.physmem.perBankWrBursts::2 6527 # Per bank write bursts -system.physmem.perBankWrBursts::3 6560 # Per bank write bursts -system.physmem.perBankWrBursts::4 6487 # Per bank write bursts -system.physmem.perBankWrBursts::5 6764 # Per bank write bursts -system.physmem.perBankWrBursts::6 6744 # Per bank write bursts -system.physmem.perBankWrBursts::7 6672 # Per bank write bursts -system.physmem.perBankWrBursts::8 7003 # Per bank write bursts -system.physmem.perBankWrBursts::9 6796 # Per bank write bursts -system.physmem.perBankWrBursts::10 6466 # Per bank write bursts -system.physmem.perBankWrBursts::11 6118 # Per bank write bursts -system.physmem.perBankWrBursts::12 7066 # Per bank write bursts -system.physmem.perBankWrBursts::13 6690 # Per bank write bursts -system.physmem.perBankWrBursts::14 6968 # Per bank write bursts -system.physmem.perBankWrBursts::15 6830 # Per bank write bursts +system.physmem.num_reads::cpu0.inst 11554 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 81308 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 72638 # Number of read requests responded to by this memory +system.physmem.num_reads::total 175587 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 95479 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136084 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 1780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 263684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1843767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 226644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1657713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3995367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 263684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 226644 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 490328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2179008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 826699 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3011956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2179008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 827041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 263684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1850013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1415 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 226644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1657716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7007324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175588 # Number of read requests accepted +system.physmem.writeReqs 136084 # Number of write requests accepted +system.physmem.readBursts 175588 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 136084 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11230016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 8460224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11204388 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8446516 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3871 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4656 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11119 # Per bank write bursts +system.physmem.perBankRdBursts::1 11133 # Per bank write bursts +system.physmem.perBankRdBursts::2 11709 # Per bank write bursts +system.physmem.perBankRdBursts::3 11218 # Per bank write bursts +system.physmem.perBankRdBursts::4 11369 # Per bank write bursts +system.physmem.perBankRdBursts::5 11386 # Per bank write bursts +system.physmem.perBankRdBursts::6 11957 # Per bank write bursts +system.physmem.perBankRdBursts::7 11810 # Per bank write bursts +system.physmem.perBankRdBursts::8 10209 # Per bank write bursts +system.physmem.perBankRdBursts::9 10442 # Per bank write bursts +system.physmem.perBankRdBursts::10 10595 # Per bank write bursts +system.physmem.perBankRdBursts::11 9762 # Per bank write bursts +system.physmem.perBankRdBursts::12 10419 # Per bank write bursts +system.physmem.perBankRdBursts::13 11416 # Per bank write bursts +system.physmem.perBankRdBursts::14 10636 # Per bank write bursts +system.physmem.perBankRdBursts::15 10289 # Per bank write bursts +system.physmem.perBankWrBursts::0 8317 # Per bank write bursts +system.physmem.perBankWrBursts::1 8433 # Per bank write bursts +system.physmem.perBankWrBursts::2 9040 # Per bank write bursts +system.physmem.perBankWrBursts::3 8546 # Per bank write bursts +system.physmem.perBankWrBursts::4 8342 # Per bank write bursts +system.physmem.perBankWrBursts::5 8537 # Per bank write bursts +system.physmem.perBankWrBursts::6 8976 # Per bank write bursts +system.physmem.perBankWrBursts::7 8813 # Per bank write bursts +system.physmem.perBankWrBursts::8 7760 # Per bank write bursts +system.physmem.perBankWrBursts::9 7806 # Per bank write bursts +system.physmem.perBankWrBursts::10 7935 # Per bank write bursts +system.physmem.perBankWrBursts::11 7392 # Per bank write bursts +system.physmem.perBankWrBursts::12 7884 # Per bank write bursts +system.physmem.perBankWrBursts::13 8744 # Per bank write bursts +system.physmem.perBankWrBursts::14 8047 # Per bank write bursts +system.physmem.perBankWrBursts::15 7619 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2539694027000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2804328669500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 18 # Read request sizes (log2) -system.physmem.readPktSize::3 15138826 # Read request sizes (log2) +system.physmem.readPktSize::2 541 # Read request sizes (log2) +system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154323 # Read request sizes (log2) +system.physmem.readPktSize::6 175033 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 58988 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1062880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1005296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961490 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1064387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 969141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1032129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2687855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2599195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3397795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 112262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 102458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 95445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 91862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 18918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131703 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 104493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60900 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,477 +164,480 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1008813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.468756 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 909.284641 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.732372 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22320 2.21% 2.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20114 1.99% 4.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8797 0.87% 5.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2199 0.22% 5.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2055 0.20% 5.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1694 0.17% 5.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9190 0.91% 6.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 817 0.08% 6.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 941627 93.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1008813 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6078 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2507.042448 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 47447.723031 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6050 99.54% 99.54% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::65536-131071 3 0.05% 99.59% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 5 0.08% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.84% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6078 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.552813 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.369881 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.322612 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 5 0.08% 0.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 4 0.07% 0.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 4 0.07% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 3 0.05% 0.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 1 0.02% 0.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 6 0.10% 0.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 3 0.05% 0.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 2 0.03% 0.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 3 0.05% 0.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 3 0.05% 0.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 2 0.03% 0.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 13 0.21% 0.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2782 45.77% 46.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 46 0.76% 47.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1401 23.05% 70.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1370 22.54% 93.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 152 2.50% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 75 1.23% 96.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 36 0.59% 97.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 22 0.36% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 24 0.39% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 25 0.41% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 13 0.21% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 15 0.25% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 16 0.26% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 12 0.20% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 9 0.15% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 11 0.18% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 12 0.20% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6078 # Writes before turning the bus around for reads -system.physmem.totQLat 392436805250 # Total ticks spent queuing -system.physmem.totMemAccLat 678145799000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76189065000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25754.14 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 9 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.565754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.964808 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.021120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24334 37.64% 37.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15675 24.25% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6689 10.35% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3630 5.61% 77.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2748 4.25% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1525 2.36% 84.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1125 1.74% 86.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1111 1.72% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7813 12.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64650 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6707 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.160877 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 477.303834 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6704 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6707 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.709408 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.238406 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.151792 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 14 0.21% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 6 0.09% 0.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 4 0.06% 0.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 11 0.16% 0.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5779 86.16% 86.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 101 1.51% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 51 0.76% 88.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 232 3.46% 92.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 200 2.98% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.31% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.33% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.18% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 28 0.42% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.12% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.07% 96.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 157 2.34% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.07% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.07% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 11 0.16% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 5 0.07% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.06% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.10% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6707 # Writes before turning the bus around for reads +system.physmem.totQLat 2725885000 # Total ticks spent queuing +system.physmem.totMemAccLat 6015928750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 877345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15534.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44504.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.69 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34284.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.02 # Data bus utilization in percentage -system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.40 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.87 # Average write queue length when enqueuing -system.physmem.readRowHits 14244486 # Number of row buffer hits during reads -system.physmem.writeRowHits 91200 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.47 # Row buffer hit rate for writes -system.physmem.avgGap 157684.51 # Average gap between requests -system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2193361967750 # Time in different power states -system.physmem.memoryStateTime::REF 84805760000 # Time in different power states +system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.75 # Average write queue length when enqueuing +system.physmem.readRowHits 145120 # Number of row buffer hits during reads +system.physmem.writeRowHits 97889 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.04 # Row buffer hit rate for writes +system.physmem.avgGap 8997692.03 # Average gap between requests +system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2678489596250 # Time in different power states +system.physmem.memoryStateTime::REF 93642640000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 261520412250 # Time in different power states +system.physmem.memoryStateTime::ACT 32196672750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3810769200 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3815857080 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2079288750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2082064875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 59414885400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 59440056000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 341813520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 349511760 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 165880066560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 165880066560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 143884087110 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 144952782390 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1397598764250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1396661312250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1773009674790 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1773181650915 # Total energy per rank (pJ) -system.physmem.averagePower::0 698.121024 # Core power per rank (mW) -system.physmem.averagePower::1 698.188739 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 16345693 # Transaction distribution -system.membus.trans_dist::ReadResp 16345693 # Transaction distribution -system.membus.trans_dist::WriteReq 763357 # Transaction distribution -system.membus.trans_dist::WriteResp 763357 # Transaction distribution -system.membus.trans_dist::Writeback 58988 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4647 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4647 # Transaction distribution -system.membus.trans_dist::ReadExReq 131549 # Transaction distribution -system.membus.trans_dist::ReadExResp 131549 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885020 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4271848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34549480 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16668128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19066210 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 140176738 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 217843 # Request fanout histogram +system.physmem.actEnergy::0 258567120 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 230186880 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 141083250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 125598000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 715260000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 653390400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 447145920 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 409451760 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 183165003840 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 183165003840 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 77778018765 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 76614000390 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1614369982500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1615391051250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1876875061395 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1876588682520 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.278202 # Core power per rank (mW) +system.physmem.averagePower::1 669.176082 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 251 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 251 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 251 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 251 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 251 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 251 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 67981 # Transaction distribution +system.membus.trans_dist::ReadResp 67980 # Transaction distribution +system.membus.trans_dist::WriteReq 27608 # Transaction distribution +system.membus.trans_dist::WriteResp 27608 # Transaction distribution +system.membus.trans_dist::Writeback 95479 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4633 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 23 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4656 # Transaction distribution +system.membus.trans_dist::ReadExReq 138435 # Transaction distribution +system.membus.trans_dist::ReadExResp 138435 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464698 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 572340 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645052 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17331544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17495585 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19814881 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 234 # Total snoops (count) +system.membus.snoop_fanout::samples 310978 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 217843 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 310978 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 217843 # Request fanout histogram -system.membus.reqLayer0.occupancy 1488348000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 310978 # Request fanout histogram +system.membus.reqLayer0.occupancy 81489000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 16812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3508000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1718500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17564779000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4755343440 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37440252152 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.5 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1433405250 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 1729661846 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38504711 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64097 # number of replacements -system.l2c.tags.tagsinuse 51403.492359 # Cycle average of tags in use -system.l2c.tags.total_refs 1900046 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129489 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.673416 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2528369126500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37092.927950 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.579992 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5418.531577 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3300.356905 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.423602 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2630.879076 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2944.793006 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.565993 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000146 # Average percentage of cache occupancy +system.l2c.tags.replacements 104201 # number of replacements +system.l2c.tags.tagsinuse 65131.975269 # Cycle average of tags in use +system.l2c.tags.total_refs 3107275 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169441 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 18.338389 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 48640.203385 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 54.461812 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000235 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5568.717985 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2872.344417 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 41.548233 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4966.062481 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2988.636721 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.742191 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000831 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.082680 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050359 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000098 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040144 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044934 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784355 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 434 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3142 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5950 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55813 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18888451 # Number of tag accesses -system.l2c.tags.data_accesses 18888451 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 27538 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7475 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 477559 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 174980 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30012 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 8090 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 496617 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 210611 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1432882 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 606482 # number of Writeback hits -system.l2c.Writeback_hits::total 606482 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55610 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57109 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112719 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 27538 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7475 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 477559 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 230590 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30012 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 8090 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 496617 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 267720 # number of demand (read+write) hits -system.l2c.demand_hits::total 1545601 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 27538 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7475 # number of overall hits -system.l2c.overall_hits::cpu0.inst 477559 # number of overall hits -system.l2c.overall_hits::cpu0.data 230590 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30012 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 8090 # number of overall hits -system.l2c.overall_hits::cpu1.inst 496617 # number of overall hits -system.l2c.overall_hits::cpu1.data 267720 # number of overall hits -system.l2c.overall_hits::total 1545601 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 15 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.084972 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043828 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000634 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.075776 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.045603 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993835 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65170 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 70 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3222 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8954 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52610 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.001068 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994415 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 29225778 # Number of tag accesses +system.l2c.tags.data_accesses 29225778 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 36725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 8774 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 958768 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 271288 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 36918 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 8011 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 964418 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 269869 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2554771 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 703572 # number of Writeback hits +system.l2c.Writeback_hits::total 703572 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 47 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 58 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 105 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 15 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 45 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 77545 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 79094 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 156639 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 36725 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 8774 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 958768 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 348833 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 36918 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 8011 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 964418 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 348963 # number of demand (read+write) hits +system.l2c.demand_hits::total 2711410 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 36725 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 8774 # number of overall hits +system.l2c.overall_hits::cpu0.inst 958768 # number of overall hits +system.l2c.overall_hits::cpu0.data 348833 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 36918 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 8011 # number of overall hits +system.l2c.overall_hits::cpu1.inst 964418 # number of overall hits +system.l2c.overall_hits::cpu1.data 348963 # number of overall hits +system.l2c.overall_hits::total 2711410 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 78 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7255 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6034 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4911 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4500 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22725 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1367 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1537 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 56126 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 77166 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133292 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 15 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 10910 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7138 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 62 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 9936 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 7955 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36080 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1305 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1437 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2742 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 6 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 17 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 23 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 74623 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 65703 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140326 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 78 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7255 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 62160 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4911 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 81666 # number of demand (read+write) misses -system.l2c.demand_misses::total 156017 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 15 # number of overall misses +system.l2c.demand_misses::cpu0.inst 10910 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 81761 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 62 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 9936 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 73658 # number of demand (read+write) misses +system.l2c.demand_misses::total 176406 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 78 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7255 # number of overall misses -system.l2c.overall_misses::cpu0.data 62160 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4911 # number of overall misses -system.l2c.overall_misses::cpu1.data 81666 # number of overall misses -system.l2c.overall_misses::total 156017 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1563750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 521104500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 442572744 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 713750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 356046000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 335278744 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1657361488 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 185992 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 279488 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4022661419 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5771447585 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9794109004 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1563750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 82000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 521104500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4465234163 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 713750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 356046000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6106726329 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11451470492 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1563750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 82000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 521104500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4465234163 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 713750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 356046000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6106726329 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11451470492 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 27553 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 7476 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 484814 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 181014 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30021 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 8090 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 501528 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 215111 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1455607 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 606482 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 606482 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1384 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1553 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111736 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 134275 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246011 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 27553 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7476 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 484814 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 292750 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30021 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 8090 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 501528 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 349386 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1701618 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 27553 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7476 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 484814 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 292750 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30021 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 8090 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 501528 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 349386 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1701618 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000544 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000134 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014965 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.033334 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000300 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009792 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.020919 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015612 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987717 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989697 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.988764 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.502309 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.574686 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541813 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000544 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000134 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014965 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.212331 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000300 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009792 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.233741 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091687 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000544 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000134 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014965 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.212331 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000300 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009792 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.233741 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091687 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 104250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71826.946933 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 73346.493868 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79305.555556 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72499.694563 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 74506.387556 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 72931.198592 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 136.058522 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 181.839948 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 160.289256 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71671.977675 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74792.623500 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73478.595895 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 104250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 71826.946933 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 71834.526432 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79305.555556 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 72499.694563 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 74776.851187 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 73398.863534 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 104250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 71826.946933 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 71834.526432 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79305.555556 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 72499.694563 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 74776.851187 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 73398.863534 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 10910 # number of overall misses +system.l2c.overall_misses::cpu0.data 81761 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 62 # number of overall misses +system.l2c.overall_misses::cpu1.inst 9936 # number of overall misses +system.l2c.overall_misses::cpu1.data 73658 # number of overall misses +system.l2c.overall_misses::total 176406 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 6586000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 832891250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 575497992 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5167000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 747110750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 644595992 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2811923484 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 329986 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 419482 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 749468 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 92496 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162493 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 254989 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5741186064 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5103227796 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10844413860 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 6586000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 74500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 832891250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 6316684056 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 5167000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 747110750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 5747823788 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 13656337344 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 6586000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 74500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 832891250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 6316684056 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 5167000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 747110750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 5747823788 # number of overall miss cycles +system.l2c.overall_miss_latency::total 13656337344 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 36803 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 8775 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 969678 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 278426 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 36980 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 8011 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 974354 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 277824 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2590851 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 703572 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 703572 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1352 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1495 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2847 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 21 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 47 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 68 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 152168 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 144797 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296965 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 36803 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 8775 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 969678 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 430594 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 36980 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 8011 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 974354 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 422621 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2887816 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 36803 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 8775 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 969678 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 430594 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 36980 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 8011 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 974354 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 422621 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2887816 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002119 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000114 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.011251 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.025637 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001677 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010198 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.028633 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.965237 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.961204 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.963119 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.285714 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.361702 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.338235 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.490399 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.453759 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.472534 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002119 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000114 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.011251 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.189880 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001677 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010198 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.174289 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.061086 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002119 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000114 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.011251 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.189880 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001677 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010198 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.174289 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.061086 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 84435.897436 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76342.002750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 80624.543570 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83338.709677 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75192.305757 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 81030.294406 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 77935.795011 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 252.862835 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 291.915101 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 273.328957 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15416 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9558.411765 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 11086.478261 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76935.878536 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77671.153463 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 77280.146658 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 84435.897436 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 76342.002750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 77257.910936 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83338.709677 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75192.305757 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 78033.937766 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 77414.245230 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 84435.897436 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 76342.002750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 77257.910936 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83338.709677 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75192.305757 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 78033.937766 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 77414.245230 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -640,154 +646,166 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58988 # number of writebacks -system.l2c.writebacks::total 58988 # number of writebacks +system.l2c.writebacks::writebacks 95479 # number of writebacks +system.l2c.writebacks::total 95479 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 18 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 71 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 66 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 148 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 71 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 66 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 148 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 66 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 15 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::cpu0.data 71 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 66 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 148 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 78 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7249 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5996 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 9 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4907 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4482 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22659 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1367 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1537 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2904 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 56126 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 77166 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133292 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 15 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 10904 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 7067 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 62 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 9931 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 7889 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 35932 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1305 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1437 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 6 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 17 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 23 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 74623 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 65703 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140326 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 78 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7249 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 62122 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 9 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4907 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 81648 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 155951 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 15 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 10904 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 81690 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 62 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 9931 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 73592 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 176258 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 78 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7249 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 62122 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 9 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4907 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 81648 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 155951 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1379250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 70000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 429544750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 365182494 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 294088000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 278470744 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1369338988 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13675367 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15376536 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29051903 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3321727581 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4810247909 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8131975490 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1379250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 70000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 429544750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3686910075 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 603750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 294088000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5088718653 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9501314478 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1379250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 429544750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3686910075 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 603750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 294088000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5088718653 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9501314478 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6123500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83706366250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83236564000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166949053750 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 7705500500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 9339419914 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17044920414 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6123500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91411866750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 92575983914 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183993974164 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033125 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020836 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015567 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987717 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989697 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.988764 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.502309 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.574686 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541813 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.212202 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.233690 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091649 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.212202 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.233690 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091649 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 91950 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60904.351901 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62130.911200 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60432.454566 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.926116 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.252440 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.098829 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59183.401294 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62336.364578 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61008.728881 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91950 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59349.507018 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62325.086383 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 60924.998737 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91950 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59349.507018 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62325.086383 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 60924.998737 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.inst 10904 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 81690 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 62 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 9931 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 73592 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 176258 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5619000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 695263500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 482934742 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4398500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 621792250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 542490992 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2352561484 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13058305 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14434936 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 27493241 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 60006 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 170017 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 230023 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4809749936 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4286056704 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9095806640 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 5619000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 695263500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 5292684678 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4398500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 621792250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4828547696 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 11448368124 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5619000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 695263500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5292684678 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4398500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 621792250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4828547696 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 11448368124 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 36174500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2949055750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2430218500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5415448750 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2226044000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1876060498 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4102104498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 36174500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5175099750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4306278998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 9517553248 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002119 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000114 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.011245 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.025382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001677 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010192 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.028396 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.013869 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.965237 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.961204 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.963119 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.361702 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.338235 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.490399 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.453759 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.472534 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002119 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000114 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.011245 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.189715 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001677 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010192 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.174132 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.061035 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002119 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000114 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.011245 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.189715 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001677 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010192 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.174132 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.061035 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 72038.461538 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63762.243213 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68336.598557 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70943.548387 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62611.242574 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68765.495247 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 65472.600579 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.363985 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10045.188587 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.710795 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64453.987859 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65233.805214 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64819.111498 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 72038.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63762.243213 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64789.872420 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70943.548387 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62611.242574 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65612.399391 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 64952.331945 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72038.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63762.243213 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64789.872420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70943.548387 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62611.242574 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65612.399391 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 64952.331945 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -800,177 +818,203 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2673184 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2673184 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 606482 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2937 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2940 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246011 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246011 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1973853 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5791552 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42247 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 136455 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7944107 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63133312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85325794 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 230296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 148751666 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 33359 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2344441 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 2655300 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2655214 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 703572 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2847 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 68 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2915 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296965 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296965 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3889644 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2533488 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43405 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169876 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6636413 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124460352 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99828001 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 67144 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 295132 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224650629 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 69040 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3663181 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.009957 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.099289 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 2344441 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3626705 99.00% 99.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36476 1.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2344441 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4954098182 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3663181 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4671577230 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4446552172 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4477877910 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26748853 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 8759110629 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 3910283961 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 26690343 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 79493732 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 96888385 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 16322162 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322162 # Transaction distribution -system.iobus.trans_dist::WriteReq 8176 # Transaction distribution -system.iobus.trans_dist::WriteResp 8176 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 30210 # Transaction distribution +system.iobus.trans_dist::ReadResp 30210 # Transaction distribution +system.iobus.trans_dist::WriteReq 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660676 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15856 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 123500982 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480421 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3969000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38127481848 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7736387 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5741528 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 324689 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4736478 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3796485 # Number of BTB hits +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326614549 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36835289 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu0.branchPred.lookups 26968745 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14109241 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 549589 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 16704483 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12571056 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 80.154178 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 808967 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 22406 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 75.255583 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6684107 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29871 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -994,25 +1038,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 27184101 # DTB read hits -system.cpu0.dtb.read_misses 37692 # DTB read misses -system.cpu0.dtb.write_hits 5601213 # DTB write hits -system.cpu0.dtb.write_misses 10069 # DTB write misses -system.cpu0.dtb.flush_tlb 510 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5493 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 558 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch +system.cpu0.dtb.read_hits 14281958 # DTB read hits +system.cpu0.dtb.read_misses 49036 # DTB read misses +system.cpu0.dtb.write_hits 10331652 # DTB write hits +system.cpu0.dtb.write_misses 7432 # DTB write misses +system.cpu0.dtb.flush_tlb 178 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 474 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 3418 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 971 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1307 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 698 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 27221793 # DTB read accesses -system.cpu0.dtb.write_accesses 5611282 # DTB write accesses +system.cpu0.dtb.perms_faults 583 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14330994 # DTB read accesses +system.cpu0.dtb.write_accesses 10339084 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32785314 # DTB hits -system.cpu0.dtb.misses 47761 # DTB misses -system.cpu0.dtb.accesses 32833075 # DTB accesses +system.cpu0.dtb.hits 24613610 # DTB hits +system.cpu0.dtb.misses 56468 # DTB misses +system.cpu0.dtb.accesses 24670078 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1034,720 +1078,720 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5349776 # ITB inst hits -system.cpu0.itb.inst_misses 7612 # ITB inst misses +system.cpu0.itb.inst_hits 20359986 # ITB inst hits +system.cpu0.itb.inst_misses 8688 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 510 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2622 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb 178 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 474 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2307 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2424 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1454 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5357388 # ITB inst accesses -system.cpu0.itb.hits 5349776 # DTB hits -system.cpu0.itb.misses 7612 # DTB misses -system.cpu0.itb.accesses 5357388 # DTB accesses -system.cpu0.numCycles 234157878 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20368674 # ITB inst accesses +system.cpu0.itb.hits 20359986 # DTB hits +system.cpu0.itb.misses 8688 # DTB misses +system.cpu0.itb.accesses 20368674 # DTB accesses +system.cpu0.numCycles 107845593 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 14748705 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 42201957 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7736387 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4605452 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 215146781 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 898208 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 106243 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 1405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1864 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 95051 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1850622 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5346983 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 204760 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2833 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 232399808 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.216000 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.156571 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 40386810 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 105587816 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 26968745 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19255163 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 62197124 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3245751 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 127625 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 7153 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 414 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 560512 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 142803 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20358682 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 375797 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3540 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 105045556 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.208380 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.316447 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 222777653 95.86% 95.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 886693 0.38% 96.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 957710 0.41% 96.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1031526 0.44% 97.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1201262 0.52% 97.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 716459 0.31% 97.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1131800 0.49% 98.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 450199 0.19% 98.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3246506 1.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 76194887 72.54% 72.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3754274 3.57% 76.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2490616 2.37% 78.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 7859227 7.48% 85.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1696652 1.62% 87.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1110270 1.06% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6030562 5.74% 94.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1172073 1.12% 95.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4736995 4.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 232399808 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.033039 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.180229 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12178110 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 212389955 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6147086 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1310186 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 372224 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 973042 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 78155 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 44916036 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 260169 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 372224 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12790792 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 53545394 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 30504571 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6768689 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 128415973 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 43504199 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1378 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 95402427 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 124537502 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1839930 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 46109442 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 200228601 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 53009049 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5261 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36340147 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 9769295 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 578634 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 493652 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 7443860 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7970278 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6245265 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1090249 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1688574 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 41187030 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 989826 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 58971927 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 58739 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7127220 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 15644672 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 268943 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 232399808 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.253752 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.958915 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 105045556 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.250068 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.979065 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27992831 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58288752 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15795686 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1494186 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1473806 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1905882 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 151125 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 87429633 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 488960 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1473806 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28854522 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 7825241 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 44530433 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16415738 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 5945509 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 83590953 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2363 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1232745 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 241627 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3747183 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 86230749 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 384928079 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 93177414 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5669 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 72449468 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13781265 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1547727 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1453455 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8907873 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 15026911 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11459129 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1951942 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2729865 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 80431590 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1054195 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 77118742 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 91388 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10043438 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24751793 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 115145 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 105045556 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.734146 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.428326 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 212110796 91.27% 91.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6244814 2.69% 93.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 2921782 1.26% 95.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2401444 1.03% 96.25% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6174292 2.66% 98.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1067597 0.46% 99.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 901998 0.39% 99.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 384604 0.17% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 192481 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 74311546 70.74% 70.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10189117 9.70% 80.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7864547 7.49% 87.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6570455 6.25% 94.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2322662 2.21% 96.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1491632 1.42% 97.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1567348 1.49% 99.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 489722 0.47% 99.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 238527 0.23% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 232399808 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 105045556 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 115073 2.28% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4670641 92.37% 94.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 270791 5.36% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 112665 9.94% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 535473 47.24% 57.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 485278 42.82% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 15020 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 25465355 43.18% 43.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47791 0.08% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 896 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 27510585 46.65% 89.94% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5932280 10.06% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2200 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 51451834 66.72% 66.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57694 0.07% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 2 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4462 0.01% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14684703 19.04% 85.84% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10917839 14.16% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 58971927 # Type of FU issued -system.cpu0.iq.rate 0.251847 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 5056507 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.085744 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 355447115 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 49321417 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 38218166 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11793 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6394 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5095 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 64007055 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6359 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 225424 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 77118742 # Type of FU issued +system.cpu0.iq.rate 0.715085 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1133419 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014697 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 260495273 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 91574151 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 74667012 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12574 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6644 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5487 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 78243199 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6762 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 345945 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1448099 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2516 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 24796 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 671952 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2206741 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2565 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 52530 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1128151 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17102895 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 3149110 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 207860 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 209627 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 372224 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 50935329 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1903194 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 42289333 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 78950 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7970278 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6245265 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 710795 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 138182 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1696089 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 24796 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 159500 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 133057 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 292557 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 58565137 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 27348453 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 359214 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1473806 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5382891 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 2162428 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 81613092 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 131628 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 15026911 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11459129 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 550936 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 43632 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2106388 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 52530 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 254626 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 219922 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 474548 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 76513772 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14449148 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 548624 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 112477 # number of nop insts executed -system.cpu0.iew.exec_refs 33216509 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5651382 # Number of branches executed -system.cpu0.iew.exec_stores 5868056 # Number of stores executed -system.cpu0.iew.exec_rate 0.250110 # Inst execution rate -system.cpu0.iew.wb_sent 55395790 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 38223261 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 21614386 # num instructions producing a value -system.cpu0.iew.wb_consumers 38462259 # num instructions consuming a value +system.cpu0.iew.exec_nop 127307 # number of nop insts executed +system.cpu0.iew.exec_refs 25261391 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14437195 # Number of branches executed +system.cpu0.iew.exec_stores 10812243 # Number of stores executed +system.cpu0.iew.exec_rate 0.709475 # Inst execution rate +system.cpu0.iew.wb_sent 75851893 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 74672499 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 39010696 # num instructions producing a value +system.cpu0.iew.wb_consumers 67649101 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.163237 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.561964 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.692402 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.576662 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7051288 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 720883 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 247682 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 231240606 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.150761 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 0.850016 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11320580 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 939050 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 400483 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 102489063 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.685035 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.574738 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 218744105 94.60% 94.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6302358 2.73% 97.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1708730 0.74% 98.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1054896 0.46% 98.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 648771 0.28% 98.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 578680 0.25% 99.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 445136 0.19% 99.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 245162 0.11% 99.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1512768 0.65% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 75163014 73.34% 73.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12241374 11.94% 85.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6264234 6.11% 91.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2647997 2.58% 93.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1295474 1.26% 95.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 837997 0.82% 96.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1889450 1.84% 97.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 409985 0.40% 98.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1739538 1.70% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 231240606 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29065490 # Number of instructions committed -system.cpu0.commit.committedOps 34862084 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 102489063 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 57892234 # Number of instructions committed +system.cpu0.commit.committedOps 70208613 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12095492 # Number of memory references committed -system.cpu0.commit.loads 6522179 # Number of loads committed -system.cpu0.commit.membars 193065 # Number of memory barriers committed -system.cpu0.commit.branches 4958543 # Number of branches committed -system.cpu0.commit.fp_insts 5094 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 30770331 # Number of committed integer instructions. -system.cpu0.commit.function_calls 472637 # Number of function calls committed. +system.cpu0.commit.refs 23151148 # Number of memory references committed +system.cpu0.commit.loads 12820170 # Number of loads committed +system.cpu0.commit.membars 372459 # Number of memory barriers committed +system.cpu0.commit.branches 13651808 # Number of branches committed +system.cpu0.commit.fp_insts 5463 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 61466111 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2656847 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 22721291 65.17% 65.17% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 44405 0.13% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 896 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 6522179 18.71% 84.01% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5573313 15.99% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 46997024 66.94% 66.94% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55979 0.08% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4462 0.01% 67.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.03% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12820170 18.26% 85.29% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10330978 14.71% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 34862084 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1512768 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 70208613 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1739538 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 270737391 # The number of ROB reads -system.cpu0.rob.rob_writes 84952654 # The number of ROB writes -system.cpu0.timesIdled 265059 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 1758070 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2270312982 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 28998871 # Number of Instructions Simulated -system.cpu0.committedOps 34795465 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 8.074724 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.074724 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.123843 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.123843 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66418764 # number of integer regfile reads -system.cpu0.int_regfile_writes 24158486 # number of integer regfile writes -system.cpu0.fp_regfile_reads 44743 # number of floating regfile reads -system.cpu0.fp_regfile_writes 41780 # number of floating regfile writes -system.cpu0.cc_regfile_reads 196661933 # number of cc regfile reads -system.cpu0.cc_regfile_writes 15655112 # number of cc regfile writes -system.cpu0.misc_regfile_reads 292292897 # number of misc regfile reads -system.cpu0.misc_regfile_writes 565980 # number of misc regfile writes -system.cpu0.icache.tags.replacements 986757 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.592826 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 9965260 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 987269 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.093764 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6651821250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 184.507996 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 327.084830 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.360367 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.638838 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999205 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 169616941 # The number of ROB reads +system.cpu0.rob.rob_writes 165619058 # The number of ROB writes +system.cpu0.timesIdled 398870 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2800037 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2442123265 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 57820351 # Number of Instructions Simulated +system.cpu0.committedOps 70136730 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.865184 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.865184 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.536140 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.536140 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 83228446 # number of integer regfile reads +system.cpu0.int_regfile_writes 47576245 # number of integer regfile writes +system.cpu0.fp_regfile_reads 16184 # number of floating regfile reads +system.cpu0.fp_regfile_writes 12998 # number of floating regfile writes +system.cpu0.cc_regfile_reads 270476207 # number of cc regfile reads +system.cpu0.cc_regfile_writes 28213628 # number of cc regfile writes +system.cpu0.misc_regfile_reads 191272649 # number of misc regfile reads +system.cpu0.misc_regfile_writes 720305 # number of misc regfile writes +system.cpu0.icache.tags.replacements 1943673 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.578352 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 38923517 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1944185 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 20.020480 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9481344250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 274.782570 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 236.795782 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.536685 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.462492 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999176 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 12017349 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 12017349 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 4823854 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5141406 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 9965260 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 4823854 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5141406 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 9965260 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 4823854 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5141406 # number of overall hits -system.cpu0.icache.overall_hits::total 9965260 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 523011 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 541799 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1064810 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 523011 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 541799 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1064810 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 523011 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 541799 # number of overall misses -system.cpu0.icache.overall_misses::total 1064810 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7244933790 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7308182079 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14553115869 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7244933790 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7308182079 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14553115869 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7244933790 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7308182079 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14553115869 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5346865 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5683205 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11030070 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5346865 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5683205 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11030070 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5346865 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5683205 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11030070 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097816 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.095333 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.096537 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097816 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.095333 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.096537 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097816 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.095333 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.096537 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13852.354520 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13488.733052 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13667.335834 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13852.354520 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13488.733052 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13667.335834 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13852.354520 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13488.733052 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13667.335834 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4607 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 42951658 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 42951658 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 19318996 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19604521 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 38923517 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19318996 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 19604521 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 38923517 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19318996 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 19604521 # number of overall hits +system.cpu0.icache.overall_hits::total 38923517 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1039021 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 1044832 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2083853 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1039021 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 1044832 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2083853 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1039021 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 1044832 # number of overall misses +system.cpu0.icache.overall_misses::total 2083853 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14217432245 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14193731102 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28411163347 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14217432245 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 14193731102 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28411163347 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14217432245 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 14193731102 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28411163347 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 20358017 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20649353 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 41007370 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 20358017 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20649353 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 41007370 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 20358017 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20649353 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 41007370 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051037 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050599 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050817 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051037 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050599 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050817 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051037 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050599 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050817 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13683.488827 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13584.701753 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13633.957552 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13683.488827 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13584.701753 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13633.957552 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13683.488827 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13584.701753 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13633.957552 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8339 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 283 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 489 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.279152 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.053170 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37777 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39754 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 77531 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 37777 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39754 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 77531 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 37777 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39754 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 77531 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 485234 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 502045 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 987279 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 485234 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 502045 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 987279 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 485234 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 502045 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 987279 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5896477037 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5947728017 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11844205054 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5896477037 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5947728017 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11844205054 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5896477037 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5947728017 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11844205054 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8530500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8530500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8530500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8530500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090751 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.088338 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089508 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090751 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.088338 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.089508 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090751 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.088338 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.089508 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12151.821672 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11847.001797 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11996.816557 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12151.821672 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11847.001797 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11996.816557 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12151.821672 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11847.001797 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11996.816557 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 69244 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 70320 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 139564 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 69244 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 70320 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 139564 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 69244 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 70320 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 139564 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 969777 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 974512 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1944289 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 969777 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 974512 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1944289 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 969777 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 974512 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1944289 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11614628478 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11591128360 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 23205756838 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11614628478 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11591128360 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 23205756838 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11614628478 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11591128360 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 23205756838 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 49940000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 49940000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 49940000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 49940000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047636 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047193 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047413 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047636 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.047193 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047413 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047636 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.047193 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047413 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11976.597174 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11894.290024 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11935.343376 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11976.597174 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11894.290024 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11935.343376 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11976.597174 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11894.290024 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11935.343376 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 641624 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993418 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19749835 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 642136 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.756467 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 42094250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 133.332182 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 378.661236 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.260414 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.739573 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 852682 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.984423 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42512914 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 853194 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.827957 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 91705250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 329.938362 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 182.046061 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.644411 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.355559 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 95284916 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 95284916 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5852905 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6194424 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 12047329 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3505923 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3637478 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7143401 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 35429 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 29531 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 64960 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 110357 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 133056 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243413 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 112492 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 135154 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247646 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9358828 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 9831902 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19190730 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9394257 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 9861433 # number of overall hits -system.cpu0.dcache.overall_hits::total 19255690 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 296259 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 395495 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 691754 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1362667 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1717725 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3080392 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 74316 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 54156 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 128472 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6370 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6955 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13325 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1658926 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2113220 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3772146 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1733242 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2167376 # number of overall misses -system.cpu0.dcache.overall_misses::total 3900618 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4388776307 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5728170629 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 10116946936 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 57800783004 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 86624659870 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 144425442874 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92286740 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 93793740 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 186080480 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 13000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 39000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 62189559311 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 92352830499 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 154542389810 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 62189559311 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 92352830499 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 154542389810 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6149164 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6589919 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12739083 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4868590 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5355203 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223793 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 109745 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 83687 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 193432 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 116727 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 140011 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256738 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 112494 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 135155 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247649 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11017754 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11945122 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 22962876 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11127499 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12028809 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23156308 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048179 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060015 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.054302 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.279889 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.320758 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.301296 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.677170 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.647126 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.664171 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054572 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049675 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.051901 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000018 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000007 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150568 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.176911 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.164271 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.155762 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.180182 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.168447 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14813.984746 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14483.547527 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14625.064598 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42417.393981 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50429.876651 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 46885.410322 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14487.714286 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13485.800144 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13964.763977 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37487.844130 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 43702.421186 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 40969.355325 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35880.482536 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42610.433307 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39619.975555 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 200600 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 41919 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 27184 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 783 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.379341 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 53.536398 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 189863403 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189863403 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 12602173 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 12737013 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25339186 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7727036 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 8174827 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15901863 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180867 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 181606 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 362473 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 207945 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 238852 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 446797 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 213795 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 245624 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459419 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20329209 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 20911840 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41241049 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20510076 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21093446 # number of overall hits +system.cpu0.dcache.overall_hits::total 41603522 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 421777 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 407630 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 829407 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1909127 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1794923 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 3704050 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 96495 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 85144 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 181639 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13429 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14216 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 27645 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 47 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 68 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2330904 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 2202553 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4533457 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2427399 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 2287697 # number of overall misses +system.cpu0.dcache.overall_misses::total 4715096 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7013958136 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6635684452 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13649642588 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84643454348 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 74838228910 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 159481683258 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 181700494 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 211428245 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 393128739 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 350006 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 828017 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 1178023 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 91657412484 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 81473913362 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 173131325846 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 91657412484 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 81473913362 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 173131325846 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 13023950 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 13144643 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26168593 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9636163 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9969750 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19605913 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 277362 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 266750 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 544112 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 221374 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 253068 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 474442 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 213816 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 245671 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 459487 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 22660113 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 23114393 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 45774506 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 22937475 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 23381143 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 46318618 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032385 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031011 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.031695 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.198121 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.180037 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.188925 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.347903 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.319190 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.333826 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060662 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056175 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058268 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000098 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000191 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000148 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.102864 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.095289 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.099039 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.105827 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.097844 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.101797 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16629.541525 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16278.695022 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16457.110427 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44336.209350 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41694.395197 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43056.028741 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13530.456028 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14872.555219 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14220.609116 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16666.952381 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 17617.382979 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17323.867647 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39322.688744 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 36990.670990 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 38189.691850 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37759.516455 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35613.944225 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36718.515561 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1117471 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 160932 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 70035 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 2415 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.955893 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 66.638509 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 606482 # number of writebacks -system.cpu0.dcache.writebacks::total 606482 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 164188 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 218355 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 382543 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1249592 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1581925 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2831517 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 626 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 765 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1391 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1413780 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1800280 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3214060 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1413780 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1800280 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3214060 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 132071 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 177140 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 309211 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 113075 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 135800 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248875 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 43244 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 31809 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 75053 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5744 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6190 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11934 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 245146 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 312940 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 558086 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 288390 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 344749 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 633139 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1730710058 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2210787235 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3941497293 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4783325934 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6576818347 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11360144281 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 814553760 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 636336252 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1450890012 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72971510 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72018008 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 144989518 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6514035992 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8787605582 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15301641574 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7328589752 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9423941834 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16752531586 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91416176750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90920349500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336526250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 11961680895 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14731919998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26693600893 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103377857645 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 105652269498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209030127143 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021478 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026880 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024273 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023225 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025359 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024343 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.394041 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.380095 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.388007 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049209 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044211 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046483 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000018 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000007 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.022250 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026198 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024304 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028660 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027342 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13104.391259 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12480.451818 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12746.950442 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42302.241291 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48430.179286 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45645.984052 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18836.226066 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20004.912195 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19331.539206 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12703.953691 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11634.573183 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12149.280878 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26572.067225 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 28080.800096 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27418.071003 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25412.080003 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27335.661116 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26459.484546 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 703572 # number of writebacks +system.cpu0.dcache.writebacks::total 703572 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 210384 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 193413 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 403797 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1755618 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1648654 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3404272 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9415 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8951 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18366 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1966002 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1842067 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3808069 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1966002 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1842067 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3808069 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 211393 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 214217 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 425610 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 153509 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 146269 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 299778 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 63030 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58365 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 121395 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4014 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5265 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9279 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 47 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 68 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 364902 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 360486 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 725388 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 427932 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 418851 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 846783 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2857072417 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2926033619 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5783106036 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6788582559 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6159862377 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12948444936 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 975244760 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 899933504 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1875178264 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 46933501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81366752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 128300253 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 307994 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 733983 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1041977 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9645654976 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9085895996 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 18731550972 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10620899736 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9985829500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 20606729236 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3170906750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2613622501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784529251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2427957377 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2008001500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4435958877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5598864127 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4621624001 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220488128 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016231 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016297 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016264 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015931 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014671 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015290 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227248 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.218800 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223107 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018132 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020805 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019558 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000098 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000191 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000148 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016103 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015596 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015847 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018656 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017914 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018282 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13515.454235 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13659.203607 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13587.805822 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44222.700682 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42113.245985 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43193.446270 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15472.707600 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15419.061150 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15446.915145 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11692.451669 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15454.273884 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13826.948270 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14666.380952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15616.659574 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15323.191176 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26433.549216 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25204.573814 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25822.802379 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24819.129525 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23841.006706 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24335.312868 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1758,15 +1802,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8293404 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6173471 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 340831 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5168505 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4065400 # Number of BTB hits +system.cpu1.branchPred.lookups 27347291 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14229080 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 552926 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17264130 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 12844736 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 78.657175 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 881063 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 23561 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 74.401293 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6762355 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 29663 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1790,25 +1834,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 28281448 # DTB read hits -system.cpu1.dtb.read_misses 40913 # DTB read misses -system.cpu1.dtb.write_hits 6183126 # DTB write hits -system.cpu1.dtb.write_misses 14267 # DTB write misses -system.cpu1.dtb.flush_tlb 506 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5407 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 858 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch +system.cpu1.dtb.read_hits 14380313 # DTB read hits +system.cpu1.dtb.read_misses 50338 # DTB read misses +system.cpu1.dtb.write_hits 10697385 # DTB write hits +system.cpu1.dtb.write_misses 9618 # DTB write misses +system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 443 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 785 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1275 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 709 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 28322361 # DTB read accesses -system.cpu1.dtb.write_accesses 6197393 # DTB write accesses +system.cpu1.dtb.perms_faults 552 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14430651 # DTB read accesses +system.cpu1.dtb.write_accesses 10707003 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 34464574 # DTB hits -system.cpu1.dtb.misses 55180 # DTB misses -system.cpu1.dtb.accesses 34519754 # DTB accesses +system.cpu1.dtb.hits 25077698 # DTB hits +system.cpu1.dtb.misses 59956 # DTB misses +system.cpu1.dtb.accesses 25137654 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1830,356 +1874,416 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5686404 # ITB inst hits -system.cpu1.itb.inst_misses 8235 # ITB inst misses +system.cpu1.itb.inst_hits 20651138 # ITB inst hits +system.cpu1.itb.inst_misses 8123 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 506 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 443 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2271 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2705 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1349 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5694639 # ITB inst accesses -system.cpu1.itb.hits 5686404 # DTB hits -system.cpu1.itb.misses 8235 # DTB misses -system.cpu1.itb.accesses 5694639 # DTB accesses -system.cpu1.numCycles 237046957 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20659261 # ITB inst accesses +system.cpu1.itb.hits 20651138 # DTB hits +system.cpu1.itb.misses 8123 # DTB misses +system.cpu1.itb.accesses 20659261 # DTB accesses +system.cpu1.numCycles 107249974 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15347817 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 44890949 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8293404 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4946463 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 217272167 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 945647 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 107708 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 1915 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1869 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 102411 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 2087291 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5683206 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 214159 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3400 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 235393992 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.228723 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.188286 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40725468 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 106761765 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27347291 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19607091 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 61565472 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3230729 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 119361 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 4162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 473 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 476136 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 133238 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 223 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20649355 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 381272 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3428 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 104639861 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.227831 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.325701 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 225080067 95.62% 95.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 947919 0.40% 96.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1046635 0.44% 96.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1047767 0.45% 96.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1244626 0.53% 97.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 829831 0.35% 97.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1297650 0.55% 98.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 454057 0.19% 98.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3445440 1.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 75287195 71.95% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3919090 3.75% 75.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2500009 2.39% 78.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8110720 7.75% 85.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1591501 1.52% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1177075 1.12% 88.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6154172 5.88% 94.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1148436 1.10% 95.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4751663 4.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 235393992 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.034986 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.189376 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 12555511 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 214484659 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 6498538 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1464859 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 388308 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1045918 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85921 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 48232824 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 288029 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 388308 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 13237235 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 54097542 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 31323893 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 7199069 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 129145928 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 46754074 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 1435 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 95558668 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 124530529 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 2374363 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 49626992 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 215510826 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 57366811 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 4976 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39600958 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 10026026 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 608668 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 515191 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8234978 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 8452340 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6808261 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1032874 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1526046 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 44303656 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1049317 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62721282 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 61124 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 7218810 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 16029580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 286052 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 235393992 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.266452 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.981415 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 104639861 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.254986 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.995448 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27852312 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 57848791 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15754577 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1718968 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1464898 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1977106 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 152502 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 89215039 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 494329 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1464898 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28797360 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 6699621 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 45356537 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16519675 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 5801450 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 85333745 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2191 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1572004 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 242988 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 3188310 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 88168045 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 393456751 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 95320905 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6151 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 74288331 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13879714 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1591572 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1490290 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10044487 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15194391 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11866887 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2182296 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2756146 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 82055126 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1162203 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 78681977 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 95018 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10109005 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 25435903 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 107068 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 104639861 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.751931 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.430939 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 213794873 90.82% 90.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6639662 2.82% 93.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3193505 1.36% 95.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2580445 1.10% 96.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6412648 2.72% 98.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1155018 0.49% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1003845 0.43% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 407445 0.17% 99.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 206551 0.09% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 72959997 69.72% 69.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10709404 10.23% 79.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8056823 7.70% 87.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6679323 6.38% 94.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2498342 2.39% 96.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1545149 1.48% 97.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1464114 1.40% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 496511 0.47% 99.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 230198 0.22% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 235393992 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 104639861 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 146677 2.81% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 3 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4785763 91.77% 94.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 282272 5.41% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 103205 8.90% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 5 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 536017 46.20% 55.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 520896 44.90% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 13498 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 27514443 43.87% 43.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46382 0.07% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1213 0.00% 43.97% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.97% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.97% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.97% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 28642016 45.67% 89.63% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6503730 10.37% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 137 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 52524607 66.76% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 58923 0.07% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4123 0.01% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14785011 18.79% 85.63% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11309172 14.37% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62721282 # Type of FU issued -system.cpu1.iq.rate 0.264594 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 5214715 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.083141 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 366100496 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 52588764 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41277568 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11899 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6202 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5156 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 67916046 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 226153 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 78681977 # Type of FU issued +system.cpu1.iq.rate 0.733632 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1160123 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014744 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 263245129 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 93371477 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 76291260 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 13827 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7286 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6040 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 79834510 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7453 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 367216 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1459547 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2673 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 24270 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 647934 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2201674 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2649 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 53639 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1152377 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17097171 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3878321 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 193043 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 153958 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 388308 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 50150951 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 3201381 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 45487056 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 83691 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 8452340 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6808261 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 746320 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 150012 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2969807 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 24270 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 165680 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 138748 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 304428 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 62296746 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 28474223 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 369499 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1464898 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4313031 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2150253 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 83357725 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 132748 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15194391 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11866887 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 585663 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 47230 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2090333 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 53639 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 255743 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 221088 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 476831 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 78071744 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14543565 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 550444 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 134083 # number of nop insts executed -system.cpu1.iew.exec_refs 34908741 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6065757 # Number of branches executed -system.cpu1.iew.exec_stores 6434518 # Number of stores executed -system.cpu1.iew.exec_rate 0.262803 # Inst execution rate -system.cpu1.iew.wb_sent 58446379 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41282724 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23334628 # num instructions producing a value -system.cpu1.iew.wb_consumers 41837805 # num instructions consuming a value +system.cpu1.iew.exec_nop 140396 # number of nop insts executed +system.cpu1.iew.exec_refs 25744293 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14514927 # Number of branches executed +system.cpu1.iew.exec_stores 11200728 # Number of stores executed +system.cpu1.iew.exec_rate 0.727942 # Inst execution rate +system.cpu1.iew.wb_sent 77444184 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 76297300 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 39931831 # num instructions producing a value +system.cpu1.iew.wb_consumers 69996884 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.174154 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.557740 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.711397 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.570480 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 7166738 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 763265 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 256189 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 234203986 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.162086 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 0.884581 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 11439631 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1055135 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 402423 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 102076918 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.704421 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.588048 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 220778060 94.27% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6743716 2.88% 97.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1772623 0.76% 97.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1087484 0.46% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 731864 0.31% 98.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 647370 0.28% 98.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 507514 0.22% 99.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 282341 0.12% 99.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1653014 0.71% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 73994277 72.49% 72.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12594887 12.34% 84.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6447399 6.32% 91.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2674121 2.62% 93.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1416644 1.39% 95.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 932745 0.91% 96.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1821915 1.78% 97.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 428135 0.42% 98.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1766795 1.73% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 234203986 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 31407169 # Number of instructions committed -system.cpu1.commit.committedOps 37961303 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 102076918 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 59223599 # Number of instructions committed +system.cpu1.commit.committedOps 71905144 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13153120 # Number of memory references committed -system.cpu1.commit.loads 6992793 # Number of loads committed -system.cpu1.commit.membars 210663 # Number of memory barriers committed -system.cpu1.commit.branches 5351172 # Number of branches committed -system.cpu1.commit.fp_insts 5118 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33489601 # Number of committed integer instructions. -system.cpu1.commit.function_calls 519360 # Number of function calls committed. +system.cpu1.commit.refs 23707227 # Number of memory references committed +system.cpu1.commit.loads 12992717 # Number of loads committed +system.cpu1.commit.membars 441930 # Number of memory barriers committed +system.cpu1.commit.branches 13739507 # Number of branches committed +system.cpu1.commit.fp_insts 5965 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 63021848 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2684059 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 24763487 65.23% 65.23% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 43483 0.11% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 1213 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 6992793 18.42% 83.77% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6160327 16.23% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 48136675 66.94% 66.94% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57123 0.08% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4119 0.01% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 12992717 18.07% 85.10% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10714510 14.90% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 37961303 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1653014 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 71905144 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1766795 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 276729293 # The number of ROB reads -system.cpu1.rob.rob_writes 91408516 # The number of ROB writes -system.cpu1.timesIdled 270232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1652965 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2279190242 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 31323407 # Number of Instructions Simulated -system.cpu1.committedOps 37877541 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 7.567726 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.567726 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.132140 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.132140 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 71111518 # number of integer regfile reads -system.cpu1.int_regfile_writes 26004877 # number of integer regfile writes -system.cpu1.fp_regfile_reads 44415 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42120 # number of floating regfile writes -system.cpu1.cc_regfile_reads 209232786 # number of cc regfile reads -system.cpu1.cc_regfile_writes 17062784 # number of cc regfile writes -system.cpu1.misc_regfile_reads 298304880 # number of misc regfile reads -system.cpu1.misc_regfile_writes 608841 # number of misc regfile writes -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.cpu1.rob.rob_reads 171176371 # The number of ROB reads +system.cpu1.rob.rob_writes 169257009 # The number of ROB writes +system.cpu1.timesIdled 392905 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2610113 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2951402872 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 59140577 # Number of Instructions Simulated +system.cpu1.committedOps 71822122 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.813475 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.813475 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.551427 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.551427 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 84961864 # number of integer regfile reads +system.cpu1.int_regfile_writes 48575931 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16615 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13105 # number of floating regfile writes +system.cpu1.cc_regfile_reads 275730923 # number of cc regfile reads +system.cpu1.cc_regfile_writes 28983730 # number of cc regfile writes +system.cpu1.misc_regfile_reads 192710320 # number of misc regfile reads +system.cpu1.misc_regfile_writes 799493 # number of misc regfile writes +system.iocache.tags.replacements 36423 # number of replacements +system.iocache.tags.tagsinuse 0.982033 # Cycle average of tags in use +system.iocache.tags.total_refs 16 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 234020639000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.982033 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.061377 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.061377 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328241 # Number of tag accesses +system.iocache.tags.data_accesses 328241 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses +system.iocache.ReadReq_misses::total 249 # number of ReadReq misses +system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses +system.iocache.demand_misses::total 249 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 249 # number of overall misses +system.iocache.overall_misses::total 249 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 29659377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29659377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29659377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29659377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29659377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29659377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 119113.963855 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119113.963855 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119113.963855 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119113.963855 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119113.963855 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119113.963855 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1732753268848 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1732753268848 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16710377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16710377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2222587461 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2222587461 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16710377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16710377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16710377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16710377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67109.947791 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67109.947791 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 67109.947791 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 67109.947791 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 67109.947791 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 67109.947791 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83356 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal Binary files differindex 46f8f01b2..b3be0ec54 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal |