diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:29 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:29 -0500 |
| commit | 93c0307d418e08db609818f19f5d2b02d45e7465 (patch) | |
| tree | 1f72a6617fb4a74d904a933bc48136fa0760bd19 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt | |
| parent | f2db2a96d181f796e6e475121f10230b9d1d007f (diff) | |
| download | gem5-93c0307d418e08db609818f19f5d2b02d45e7465.tar.xz | |
tests: Update regressions for the new kernels and various preceeding fixes.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt | 2744 |
1 files changed, 1446 insertions, 1298 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 3aad6c8ee..e78ea31b3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,148 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.627904 # Number of seconds simulated -sim_ticks 2627903712000 # Number of ticks simulated -final_tick 2627903712000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.904683 # Number of seconds simulated +sim_ticks 2904682547500 # Number of ticks simulated +final_tick 2904682547500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 449186 # Simulator instruction rate (inst/s) -host_op_rate 536465 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19602826894 # Simulator tick rate (ticks/s) -host_mem_usage 462988 # Number of bytes of host memory used -host_seconds 134.06 # Real time elapsed on the host -sim_insts 60216663 # Number of instructions simulated -sim_ops 71917112 # Number of ops (including micro ops) simulated +host_inst_rate 708228 # Simulator instruction rate (inst/s) +host_op_rate 853902 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18288406087 # Simulator tick rate (ticks/s) +host_mem_usage 555560 # Number of bytes of host memory used +host_seconds 158.83 # Real time elapsed on the host +sim_insts 112485368 # Number of instructions simulated +sim_ops 135622164 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 306056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4559448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 399872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4486720 # Number of bytes read from this memory -system.physmem.bytes_read::total 134008544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 306056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 399872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3673856 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1536536 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1479536 # Number of bytes written to this memory -system.physmem.bytes_written::total 6689928 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 71267 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6248 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 70105 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690649 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57404 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 384134 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 369884 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811422 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47283413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 116464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1735013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 152164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1707338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50994465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 116464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 152164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268628 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1398018 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 584700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 563010 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2545728 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1398018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47283413 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 116464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2319714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 152164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2270348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53540193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690649 # Number of read requests accepted -system.physmem.writeReqs 811422 # Number of write requests accepted -system.physmem.readBursts 15690649 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811422 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004200960 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue -system.physmem.bytesWritten 6711168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134008544 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6689928 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706554 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 980414 # Per bank write bursts -system.physmem.perBankRdBursts::1 980044 # Per bank write bursts -system.physmem.perBankRdBursts::2 979984 # Per bank write bursts -system.physmem.perBankRdBursts::3 980262 # Per bank write bursts -system.physmem.perBankRdBursts::4 986671 # Per bank write bursts -system.physmem.perBankRdBursts::5 980424 # Per bank write bursts -system.physmem.perBankRdBursts::6 980555 # Per bank write bursts -system.physmem.perBankRdBursts::7 980428 # Per bank write bursts -system.physmem.perBankRdBursts::8 980781 # Per bank write bursts -system.physmem.perBankRdBursts::9 980432 # Per bank write bursts -system.physmem.perBankRdBursts::10 979731 # Per bank write bursts -system.physmem.perBankRdBursts::11 979566 # Per bank write bursts -system.physmem.perBankRdBursts::12 980337 # Per bank write bursts -system.physmem.perBankRdBursts::13 980248 # Per bank write bursts -system.physmem.perBankRdBursts::14 980396 # Per bank write bursts -system.physmem.perBankRdBursts::15 980367 # Per bank write bursts -system.physmem.perBankWrBursts::0 6669 # Per bank write bursts -system.physmem.perBankWrBursts::1 6337 # Per bank write bursts -system.physmem.perBankWrBursts::2 6309 # Per bank write bursts -system.physmem.perBankWrBursts::3 6427 # Per bank write bursts -system.physmem.perBankWrBursts::4 6393 # Per bank write bursts -system.physmem.perBankWrBursts::5 6675 # Per bank write bursts -system.physmem.perBankWrBursts::6 6845 # Per bank write bursts -system.physmem.perBankWrBursts::7 6769 # Per bank write bursts -system.physmem.perBankWrBursts::8 7058 # Per bank write bursts -system.physmem.perBankWrBursts::9 6682 # Per bank write bursts -system.physmem.perBankWrBursts::10 6146 # Per bank write bursts -system.physmem.perBankWrBursts::11 6016 # Per bank write bursts -system.physmem.perBankWrBursts::12 6658 # Per bank write bursts -system.physmem.perBankWrBursts::13 6472 # Per bank write bursts -system.physmem.perBankWrBursts::14 6707 # Per bank write bursts -system.physmem.perBankWrBursts::15 6699 # Per bank write bursts +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 557732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4265248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 631552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4773892 # Number of bytes read from this memory +system.physmem.bytes_read::total 10229960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 557732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 631552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1189284 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5300352 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory +system.physmem.bytes_written::total 7636212 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17168 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 67163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9868 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74593 # Number of read requests responded to by this memory +system.physmem.num_reads::total 168816 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 82818 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123423 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 192011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1468404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 217425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1643516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3521886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 192011 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 217425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 409437 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1824761 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 798137 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6030 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2628932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1824761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 798468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 192011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1474434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 217425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1643519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6150817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168816 # Number of read requests accepted +system.physmem.writeReqs 123423 # Number of write requests accepted +system.physmem.readBursts 168816 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123423 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10794880 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue +system.physmem.bytesWritten 7651200 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10229960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7636212 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4512 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9768 # Per bank write bursts +system.physmem.perBankRdBursts::1 9653 # Per bank write bursts +system.physmem.perBankRdBursts::2 10324 # Per bank write bursts +system.physmem.perBankRdBursts::3 9994 # Per bank write bursts +system.physmem.perBankRdBursts::4 18675 # Per bank write bursts +system.physmem.perBankRdBursts::5 10148 # Per bank write bursts +system.physmem.perBankRdBursts::6 10372 # Per bank write bursts +system.physmem.perBankRdBursts::7 10429 # Per bank write bursts +system.physmem.perBankRdBursts::8 9938 # Per bank write bursts +system.physmem.perBankRdBursts::9 10451 # Per bank write bursts +system.physmem.perBankRdBursts::10 9811 # Per bank write bursts +system.physmem.perBankRdBursts::11 9561 # Per bank write bursts +system.physmem.perBankRdBursts::12 9986 # Per bank write bursts +system.physmem.perBankRdBursts::13 9803 # Per bank write bursts +system.physmem.perBankRdBursts::14 9966 # Per bank write bursts +system.physmem.perBankRdBursts::15 9791 # Per bank write bursts +system.physmem.perBankWrBursts::0 7253 # Per bank write bursts +system.physmem.perBankWrBursts::1 7191 # Per bank write bursts +system.physmem.perBankWrBursts::2 8157 # Per bank write bursts +system.physmem.perBankWrBursts::3 7614 # Per bank write bursts +system.physmem.perBankWrBursts::4 7092 # Per bank write bursts +system.physmem.perBankWrBursts::5 7380 # Per bank write bursts +system.physmem.perBankWrBursts::6 7560 # Per bank write bursts +system.physmem.perBankWrBursts::7 7725 # Per bank write bursts +system.physmem.perBankWrBursts::8 7575 # Per bank write bursts +system.physmem.perBankWrBursts::9 8007 # Per bank write bursts +system.physmem.perBankWrBursts::10 7415 # Per bank write bursts +system.physmem.perBankWrBursts::11 7436 # Per bank write bursts +system.physmem.perBankWrBursts::12 7462 # Per bank write bursts +system.physmem.perBankWrBursts::13 7248 # Per bank write bursts +system.physmem.perBankWrBursts::14 7309 # Per bank write bursts +system.physmem.perBankWrBursts::15 7126 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2627899414000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2904682126000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6644 # Read request sizes (log2) -system.physmem.readPktSize::3 15532042 # Read request sizes (log2) +system.physmem.readPktSize::2 9558 # Read request sizes (log2) +system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 151963 # Read request sizes (log2) +system.physmem.readPktSize::6 159244 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57404 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1139478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 982369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 987635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1091943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 997696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1062131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2775683 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2686264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3513182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 100216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 94857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 91541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 119042 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -157,453 +164,470 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5665 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1040215 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.829985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 906.043406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 203.863923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22728 2.18% 2.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22848 2.20% 4.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9187 0.88% 5.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2378 0.23% 5.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2112 0.20% 5.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1712 0.16% 5.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9383 0.90% 6.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 867 0.08% 6.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 969000 93.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1040215 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6002 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2614.234255 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 48623.103038 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 5977 99.58% 99.58% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 9 0.15% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6002 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6002 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.471176 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.313667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.128575 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 1 0.02% 0.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 5 0.08% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 9 0.15% 0.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 6 0.10% 0.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 1 0.02% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 2 0.03% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 2 0.03% 0.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 6 0.10% 0.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 3 0.05% 0.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 2 0.03% 0.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 2 0.03% 0.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 2 0.03% 0.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 2 0.03% 0.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 12 0.20% 0.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2065 34.41% 35.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 28 0.47% 35.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3575 59.56% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 74 1.23% 96.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 26 0.43% 97.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 13 0.22% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 8 0.13% 97.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 17 0.28% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 20 0.33% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 23 0.38% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 19 0.32% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 14 0.23% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 21 0.35% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 6 0.10% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 12 0.20% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 10 0.17% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 12 0.20% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6002 # Writes before turning the bus around for reads -system.physmem.totQLat 402684411250 # Total ticks spent queuing -system.physmem.totMemAccLat 696883911250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78453200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25663.99 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 162 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58497 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 315.331590 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.690243 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.870742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21229 36.29% 36.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14764 25.24% 61.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5739 9.81% 71.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3179 5.43% 76.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2288 3.91% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1563 2.67% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1023 1.75% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1098 1.88% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7614 13.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58497 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5866 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.752472 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 562.127013 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5865 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5866 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.380157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.599784 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.515949 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 16 0.27% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 10 0.17% 0.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 13 0.22% 0.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 18 0.31% 0.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4930 84.04% 85.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 59 1.01% 86.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 57 0.97% 86.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 249 4.24% 91.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 210 3.58% 94.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.34% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 11 0.19% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.14% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 30 0.51% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.09% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.07% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.05% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 157 2.68% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 19 0.32% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 6 0.10% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.10% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 6 0.10% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.12% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5866 # Writes before turning the bus around for reads +system.physmem.totQLat 1486718500 # Total ticks spent queuing +system.physmem.totMemAccLat 4649281000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 843350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8814.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44413.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 382.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.55 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.99 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27564.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.01 # Data bus utilization in percentage -system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 16.63 # Average write queue length when enqueuing -system.physmem.readRowHits 14667378 # Number of row buffer hits during reads -system.physmem.writeRowHits 87909 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.83 # Row buffer hit rate for writes -system.physmem.avgGap 159246.64 # Average gap between requests -system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2254944154750 # Time in different power states -system.physmem.memoryStateTime::REF 87751300000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.56 # Average write queue length when enqueuing +system.physmem.readRowHits 139009 # Number of row buffer hits during reads +system.physmem.writeRowHits 90713 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.41 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.88 # Row buffer hit rate for writes +system.physmem.avgGap 9939406.19 # Average gap between requests +system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2756104323000 # Time in different power states +system.physmem.memoryStateTime::REF 96993520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 285203111500 # Time in different power states +system.physmem.memoryStateTime::ACT 51578552000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3933127800 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3930897600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2146051875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2144835000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 61220499600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 61166492400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 339707520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 339798240 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 171641542800 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 171641542800 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 154602145665 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 155429248725 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1441123214250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1440397685250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1835006289510 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1835050500015 # Total energy per rank (pJ) -system.physmem.averagePower::0 698.278968 # Core power per rank (mW) -system.physmem.averagePower::1 698.295792 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.physmem.actEnergy::0 224721000 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 217516320 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 122615625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 118684500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 697031400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 618579000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 388618560 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 386065440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 189719325120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 189719325120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 86947680015 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 86005039095 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1666535934000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1667362812000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1944635925720 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1944428021475 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.484538 # Core power per rank (mW) +system.physmem.averagePower::1 669.412962 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 16743265 # Transaction distribution -system.membus.trans_dist::ReadResp 16743265 # Transaction distribution -system.membus.trans_dist::WriteReq 763389 # Transaction distribution -system.membus.trans_dist::WriteResp 763389 # Transaction distribution -system.membus.trans_dist::Writeback 57404 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution -system.membus.trans_dist::ReadExReq 131496 # Transaction distribution -system.membus.trans_dist::ReadExResp 131496 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383094 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1891706 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4278672 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35342736 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390554 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16442216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18840514 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 143096770 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 213883 # Request fanout histogram +system.membus.trans_dist::ReadReq 70577 # Transaction distribution +system.membus.trans_dist::ReadResp 70577 # Transaction distribution +system.membus.trans_dist::WriteReq 27613 # Transaction distribution +system.membus.trans_dist::WriteResp 27613 # Transaction distribution +system.membus.trans_dist::Writeback 82818 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4510 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4512 # Transaction distribution +system.membus.trans_dist::ReadExReq 129059 # Transaction distribution +system.membus.trans_dist::ReadExResp 129059 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 545872 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 618569 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15546876 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15710305 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18029601 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 219 # Total snoops (count) +system.membus.snoop_fanout::samples 283020 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 213883 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 283020 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 213883 # Request fanout histogram -system.membus.reqLayer0.occupancy 1223591000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 283020 # Request fanout histogram +system.membus.reqLayer0.occupancy 87171000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3677500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1735500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171099000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4987168321 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 38457119250 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.5 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1336695500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1640330738 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38340241 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 61855 # number of replacements -system.l2c.tags.tagsinuse 50930.330896 # Cycle average of tags in use -system.l2c.tags.total_refs 1699074 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127234 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.353931 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2574032162000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37932.108407 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000700 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2848.249708 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3170.076160 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4147.610246 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2832.285487 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.578798 # Average percentage of cache occupancy +system.l2c.tags.replacements 89435 # number of replacements +system.l2c.tags.tagsinuse 64928.071050 # Cycle average of tags in use +system.l2c.tags.total_refs 2766017 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 154676 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 17.882651 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 50556.019026 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943993 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000464 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3889.866505 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2064.899937 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768384 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5760.330467 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2651.242275 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.771424 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.043461 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.048372 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.063288 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.043217 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.777135 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6516 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56686 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17278829 # Number of tag accesses -system.l2c.tags.data_accesses 17278829 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9065 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3142 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 447117 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 182266 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10696 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4002 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 397485 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 188475 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1242248 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596597 # number of Writeback hits -system.l2c.Writeback_hits::total 596597 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57734 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56826 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114560 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9065 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3142 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 447117 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 240000 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10696 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4002 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 397485 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 245301 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356808 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9065 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3142 # number of overall hits -system.l2c.overall_hits::cpu0.inst 447117 # number of overall hits -system.l2c.overall_hits::cpu0.data 240000 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10696 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4002 # number of overall hits -system.l2c.overall_hits::cpu1.inst 397485 # number of overall hits -system.l2c.overall_hits::cpu1.data 245301 # number of overall hits -system.l2c.overall_hits::total 1356808 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4368 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5525 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6248 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4323 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20467 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1358 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1517 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2875 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 66435 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 66702 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133137 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 4368 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 71960 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6248 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 71025 # number of demand (read+write) misses -system.l2c.demand_misses::total 153604 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 4368 # number of overall misses -system.l2c.overall_misses::cpu0.data 71960 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6248 # number of overall misses -system.l2c.overall_misses::cpu1.data 71025 # number of overall misses -system.l2c.overall_misses::total 153604 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 305909750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 407234000 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.019800 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001313 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026104 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.013445 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.991590 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991684 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991639 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57372.653388 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61240.090498 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57026.568502 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62489.706223 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 59393.242781 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.647989 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.869565 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56809.298126 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56830.198795 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56819.769418 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63831.251220 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62881.393361 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61336.650646 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.698535 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.771488 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56620.078400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57321.826037 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -745,167 +789,194 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2471648 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471648 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763389 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763389 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596597 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2901 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2901 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247697 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247697 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725344 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5754019 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20105 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50232 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549700 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54760476 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83807014 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79048 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 138675122 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 18167 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2128077 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 2301461 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2301446 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 686956 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36226 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2753 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295910 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295910 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415394 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457263 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18122 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34349 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5925128 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750524 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96868197 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24732 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46148 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205689601 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 53732 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3283133 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.011105 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104795 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 2128077 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3246673 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36460 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2128077 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4809198500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3283133 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4418861248 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3866085496 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4420737429 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12959000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 7658492249 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 3782893262 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 11939000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30470250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22834207 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 16715395 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715395 # Transaction distribution -system.iobus.trans_dist::WriteReq 8184 # Transaction distribution -system.iobus.trans_dist::WriteResp 8184 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 30195 # Transaction distribution +system.iobus.trans_dist::ReadResp 30195 # Transaction distribution +system.iobus.trans_dist::WriteReq 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383094 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447158 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2390554 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 126646810 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 528000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374910000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 39130786750 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36804759 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -929,25 +1000,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6554416 # DTB read hits -system.cpu0.dtb.read_misses 6570 # DTB read misses -system.cpu0.dtb.write_hits 5649486 # DTB write hits -system.cpu0.dtb.write_misses 1771 # DTB write misses -system.cpu0.dtb.flush_tlb 2491 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 28 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6094 # Number of entries that have been flushed from TLB +system.cpu0.dtb.read_hits 12289558 # DTB read hits +system.cpu0.dtb.read_misses 5978 # DTB read misses +system.cpu0.dtb.write_hits 9834640 # DTB write hits +system.cpu0.dtb.write_misses 1046 # DTB write misses +system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 4657 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 864 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 206 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6560986 # DTB read accesses -system.cpu0.dtb.write_accesses 5651257 # DTB write accesses +system.cpu0.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12295536 # DTB read accesses +system.cpu0.dtb.write_accesses 9835686 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12203902 # DTB hits -system.cpu0.dtb.misses 8341 # DTB misses -system.cpu0.dtb.accesses 12212243 # DTB accesses +system.cpu0.dtb.hits 22124198 # DTB hits +system.cpu0.dtb.misses 7024 # DTB misses +system.cpu0.dtb.accesses 22131222 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -969,162 +1040,162 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30237068 # ITB inst hits -system.cpu0.itb.inst_misses 3286 # ITB inst misses +system.cpu0.itb.inst_hits 58032783 # ITB inst hits +system.cpu0.itb.inst_misses 3465 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2491 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 28 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2575 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30240354 # ITB inst accesses -system.cpu0.itb.hits 30237068 # DTB hits -system.cpu0.itb.misses 3286 # DTB misses -system.cpu0.itb.accesses 30240354 # DTB accesses -system.cpu0.numCycles 2626678485 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 58036248 # ITB inst accesses +system.cpu0.itb.hits 58032783 # DTB hits +system.cpu0.itb.misses 3465 # DTB misses +system.cpu0.itb.accesses 58036248 # DTB accesses +system.cpu0.numCycles 2905319694 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29654606 # Number of instructions committed -system.cpu0.committedOps 35595186 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31825632 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5298 # Number of float alu accesses -system.cpu0.num_func_calls 1084226 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3738020 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31825632 # number of integer instructions -system.cpu0.num_fp_insts 5298 # number of float instructions -system.cpu0.num_int_register_reads 57689563 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21244985 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3888 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1412 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 127837061 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 14183382 # number of times the CC registers were written -system.cpu0.num_mem_refs 12632580 # number of memory refs -system.cpu0.num_load_insts 6723962 # Number of load instructions -system.cpu0.num_store_insts 5908618 # Number of store instructions -system.cpu0.num_idle_cycles 2294291978.637380 # Number of idle cycles -system.cpu0.num_busy_cycles 332386506.362621 # Number of busy cycles -system.cpu0.not_idle_fraction 0.126543 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.873457 # Percentage of idle cycles -system.cpu0.Branches 5094853 # Number of branches fetched -system.cpu0.op_class::No_OpClass 11433 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 23427860 64.87% 64.90% # Class of executed instruction -system.cpu0.op_class::IntMult 44876 0.12% 65.02% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 988 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::MemRead 6723962 18.62% 83.64% # Class of executed instruction -system.cpu0.op_class::MemWrite 5908618 16.36% 100.00% # Class of executed instruction +system.cpu0.committedInsts 56513152 # Number of instructions committed +system.cpu0.committedOps 68067865 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 60172056 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 6287 # Number of float alu accesses +system.cpu0.num_func_calls 4924591 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7649382 # number of instructions that are conditional controls +system.cpu0.num_int_insts 60172056 # number of integer instructions +system.cpu0.num_fp_insts 6287 # number of float instructions +system.cpu0.num_int_register_reads 109432778 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41532373 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4990 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 245794862 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 26123490 # number of times the CC registers were written +system.cpu0.num_mem_refs 22763355 # number of memory refs +system.cpu0.num_load_insts 12450624 # Number of load instructions +system.cpu0.num_store_insts 10312731 # Number of store instructions +system.cpu0.num_idle_cycles 2685746001.120693 # Number of idle cycles +system.cpu0.num_busy_cycles 219573692.879307 # Number of busy cycles +system.cpu0.not_idle_fraction 0.075576 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.924424 # Percentage of idle cycles +system.cpu0.Branches 12983474 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46789640 67.21% 67.21% # Class of executed instruction +system.cpu0.op_class::IntMult 58624 0.08% 67.30% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4273 0.01% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::MemRead 12450624 17.88% 85.19% # Class of executed instruction +system.cpu0.op_class::MemWrite 10312731 14.81% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 36117737 # Class of executed instruction +system.cpu0.op_class::total 69618096 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83036 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856352 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.872863 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60653974 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856864 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.785999 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 19832593000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 151.975513 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 358.897350 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.296827 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.700971 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997799 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 1698167 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.774848 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113885210 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1698679 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.043397 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 25359588250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 419.089770 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 91.685078 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.818535 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.179072 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997607 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62367702 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62367702 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29784788 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30869186 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60653974 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29784788 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30869186 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60653974 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29784788 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30869186 # number of overall hits -system.cpu0.icache.overall_hits::total 60653974 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 452280 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 404584 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856864 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 452280 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 404584 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856864 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 452280 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 404584 # number of overall misses -system.cpu0.icache.overall_misses::total 856864 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6154944247 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5645212999 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11800157246 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6154944247 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 5645212999 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11800157246 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6154944247 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 5645212999 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11800157246 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30237068 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 31273770 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61510838 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30237068 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 31273770 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61510838 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30237068 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 31273770 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61510838 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014958 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012937 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013930 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014958 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012937 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013930 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014958 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012937 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013930 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13608.703120 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13953.129632 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13771.330393 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13608.703120 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13953.129632 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13771.330393 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13608.703120 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13953.129632 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7726648063 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15453284234 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91635621250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90440418250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182076039500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13169946836 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13069221001 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26239167837 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104805568086 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103509639251 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208315207337 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024990 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026178 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025588 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024427 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024582 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.405988 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.391579 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.398948 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048503 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043758 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046177 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024724 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025433 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025079 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028001 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028434 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028218 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11979.369508 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11592.953814 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11780.390067 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42740.384905 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43022.134234 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42880.988611 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16806.578638 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16494.840246 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16657.087797 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11375.367167 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12612.417686 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11949.947566 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26339.543065 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25768.662677 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26049.740170 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25151.564832 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24722.030271 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24934.947711 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 686956 # number of writebacks +system.cpu0.dcache.writebacks::total 686956 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 328 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 615 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7032 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7182 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14214 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 287 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 328 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 615 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 287 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 328 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 615 # 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number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8558 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 347198 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 353662 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 700860 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 404837 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 412884 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 817721 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2467791750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2647821500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5115613250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5416554578 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5704545869 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11121100447 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 696038250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 742244000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1438282250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48274750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52699750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100974500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 47998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 47998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884346328 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8352367369 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16236713697 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8580384578 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9094611369 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 17674995947 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2687639750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3103027500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5790667250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2165315000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2264487500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429802500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4852954750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5367515000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220469750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016725 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017479 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017102 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015665 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015565 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015615 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223161 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.234332 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228686 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017195 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019582 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018362 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016249 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016621 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016435 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018721 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019177 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018948 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12526.670914 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12903.865085 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12719.109819 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36063.481328 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38423.247538 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37236.533886 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12075.821059 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12533.247780 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12307.632572 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11788.705739 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11808.144746 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11798.843188 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23999 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23999 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.501570 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23616.807486 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.843160 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.664959 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22027.037543 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21614.946843 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1440,25 +1528,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6613806 # DTB read hits -system.cpu1.dtb.read_misses 7420 # DTB read misses -system.cpu1.dtb.write_hits 5584575 # DTB write hits -system.cpu1.dtb.write_misses 1868 # DTB write misses -system.cpu1.dtb.flush_tlb 2491 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6816 # Number of entries that have been flushed from TLB +system.cpu1.dtb.read_hits 12236378 # DTB read hits +system.cpu1.dtb.read_misses 5657 # DTB read misses +system.cpu1.dtb.write_hits 9775690 # DTB write hits +system.cpu1.dtb.write_misses 790 # DTB write misses +system.cpu1.dtb.flush_tlb 2934 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 4044 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 152 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 917 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 246 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6621226 # DTB read accesses -system.cpu1.dtb.write_accesses 5586443 # DTB write accesses +system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12242035 # DTB read accesses +system.cpu1.dtb.write_accesses 9776480 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12198381 # DTB hits -system.cpu1.dtb.misses 9288 # DTB misses -system.cpu1.dtb.accesses 12207669 # DTB accesses +system.cpu1.dtb.hits 22012068 # DTB hits +system.cpu1.dtb.misses 6447 # DTB misses +system.cpu1.dtb.accesses 22018515 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1480,113 +1568,173 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 31273770 # ITB inst hits -system.cpu1.itb.inst_misses 4023 # ITB inst misses +system.cpu1.itb.inst_hits 57551112 # ITB inst hits +system.cpu1.itb.inst_misses 3277 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2491 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 3046 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb 2934 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2396 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31277793 # ITB inst accesses -system.cpu1.itb.hits 31273770 # DTB hits -system.cpu1.itb.misses 4023 # DTB misses -system.cpu1.itb.accesses 31277793 # DTB accesses -system.cpu1.numCycles 2629128939 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 57554389 # ITB inst accesses +system.cpu1.itb.hits 57551112 # DTB hits +system.cpu1.itb.misses 3277 # DTB misses +system.cpu1.itb.accesses 57554389 # DTB accesses +system.cpu1.numCycles 2904045401 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30562057 # Number of instructions committed -system.cpu1.committedOps 36321926 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 32452923 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 4971 # Number of float alu accesses -system.cpu1.num_func_calls 1056400 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3813741 # number of instructions that are conditional controls -system.cpu1.num_int_insts 32452923 # number of integer instructions -system.cpu1.num_fp_insts 4971 # number of float instructions -system.cpu1.num_int_register_reads 58477662 # number of times the integer registers were read -system.cpu1.num_int_register_writes 21639168 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3605 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1368 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 130057431 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 14822724 # number of times the CC registers were written -system.cpu1.num_mem_refs 12626030 # number of memory refs -system.cpu1.num_load_insts 6797131 # Number of load instructions -system.cpu1.num_store_insts 5828899 # Number of store instructions -system.cpu1.num_idle_cycles 2287592720.742589 # Number of idle cycles -system.cpu1.num_busy_cycles 341536218.257411 # Number of busy cycles -system.cpu1.not_idle_fraction 0.129905 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.870095 # Percentage of idle cycles -system.cpu1.Branches 5215542 # Number of branches fetched -system.cpu1.op_class::No_OpClass 17085 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 24167965 65.58% 65.62% # Class of executed instruction -system.cpu1.op_class::IntMult 43107 0.12% 65.74% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1123 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::MemRead 6797131 18.44% 84.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 5828899 15.82% 100.00% # Class of executed instruction +system.cpu1.committedInsts 55972216 # Number of instructions committed +system.cpu1.committedOps 67554299 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 59752061 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5003 # Number of float alu accesses +system.cpu1.num_func_calls 4972349 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7584517 # number of instructions that are conditional controls +system.cpu1.num_int_insts 59752061 # number of integer instructions +system.cpu1.num_fp_insts 5003 # number of float instructions +system.cpu1.num_int_register_reads 108688873 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41135339 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3588 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 244070995 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 25783519 # number of times the CC registers were written +system.cpu1.num_mem_refs 22653694 # number of memory refs +system.cpu1.num_load_insts 12397895 # Number of load instructions +system.cpu1.num_store_insts 10255799 # Number of store instructions +system.cpu1.num_idle_cycles 2693922745.089012 # Number of idle cycles +system.cpu1.num_busy_cycles 210122655.910988 # Number of busy cycles +system.cpu1.not_idle_fraction 0.072355 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.927645 # Percentage of idle cycles +system.cpu1.Branches 12941354 # Number of branches fetched +system.cpu1.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 46411426 67.14% 67.14% # Class of executed instruction +system.cpu1.op_class::IntMult 56056 0.08% 67.22% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4164 0.01% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::MemRead 12397895 17.94% 85.16% # Class of executed instruction +system.cpu1.op_class::MemWrite 10255799 14.84% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 36855310 # Class of executed instruction +system.cpu1.op_class::total 69125473 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.replacements 36424 # number of replacements +system.iocache.tags.tagsinuse 1.083103 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 309429741000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.083103 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067694 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067694 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328122 # Number of tag accesses +system.iocache.tags.data_accesses 328122 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses +system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses +system.iocache.demand_misses::total 234 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 234 # number of overall misses +system.iocache.overall_misses::total 234 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1779782747750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1779782747750 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2203719731 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2203719731 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |