diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt | 2031 |
1 files changed, 1041 insertions, 990 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 094868576..cce768d16 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,147 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.629695 # Number of seconds simulated -sim_ticks 2629694709500 # Number of ticks simulated -final_tick 2629694709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.631271 # Number of seconds simulated +sim_ticks 2631271319500 # Number of ticks simulated +final_tick 2631271319500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 422902 # Simulator instruction rate (inst/s) -host_op_rate 538135 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18468797106 # Simulator tick rate (ticks/s) -host_mem_usage 466428 # Number of bytes of host memory used -host_seconds 142.39 # Real time elapsed on the host -sim_insts 60215255 # Number of instructions simulated -sim_ops 76622777 # Number of ops (including micro ops) simulated +host_inst_rate 354699 # Simulator instruction rate (inst/s) +host_op_rate 451347 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15499898557 # Simulator tick rate (ticks/s) +host_mem_usage 465856 # Number of bytes of host memory used +host_seconds 169.76 # Real time elapsed on the host +sim_insts 60213853 # Number of instructions simulated +sim_ops 76620850 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 291720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4684888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 299528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4518680 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 412356 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4375828 # Number of bytes read from this memory -system.physmem.bytes_read::total 134021240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 291720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 412356 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704076 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3689664 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1522876 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1493404 # Number of bytes written to this memory -system.physmem.bytes_written::total 6705944 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 404800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4542464 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 299528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 404800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3690624 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1524152 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1491920 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706696 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10770 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73237 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10892 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70640 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6459 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 68407 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690908 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57651 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380719 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373351 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811721 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47251210 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 70976 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690868 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57666 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 381038 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 372980 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811684 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47222898 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 110933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1781533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 113834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1717299 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 156808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1664006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50964562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 110933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 156808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267741 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1403077 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 579108 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 567900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2550085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1403077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47251210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 153842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1726338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50934284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 113834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 153842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267676 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1402601 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 579245 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 566996 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2548842 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1402601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47222898 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 110933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2360641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 113834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2296545 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 156808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2231906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53514647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690908 # Number of read requests accepted -system.physmem.writeReqs 811721 # Number of write requests accepted -system.physmem.readBursts 15690908 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811721 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004216192 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1920 # Total number of bytes read from write queue -system.physmem.bytesWritten 6737024 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134021240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6705944 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 30 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706455 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu1.inst 153842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2293334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53483126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690868 # Number of read requests accepted +system.physmem.writeReqs 811684 # Number of write requests accepted +system.physmem.readBursts 15690868 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811684 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004214848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue +system.physmem.bytesWritten 6724608 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134021920 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706696 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706598 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980391 # Per bank write bursts system.physmem.perBankRdBursts::1 980206 # Per bank write bursts -system.physmem.perBankRdBursts::2 980218 # Per bank write bursts -system.physmem.perBankRdBursts::3 980431 # Per bank write bursts +system.physmem.perBankRdBursts::2 980222 # Per bank write bursts +system.physmem.perBankRdBursts::3 980428 # Per bank write bursts system.physmem.perBankRdBursts::4 986950 # Per bank write bursts system.physmem.perBankRdBursts::5 980708 # Per bank write bursts -system.physmem.perBankRdBursts::6 980610 # Per bank write bursts -system.physmem.perBankRdBursts::7 980421 # Per bank write bursts +system.physmem.perBankRdBursts::6 980611 # Per bank write bursts +system.physmem.perBankRdBursts::7 980420 # Per bank write bursts system.physmem.perBankRdBursts::8 980615 # Per bank write bursts system.physmem.perBankRdBursts::9 980431 # Per bank write bursts system.physmem.perBankRdBursts::10 979815 # Per bank write bursts -system.physmem.perBankRdBursts::11 979558 # Per bank write bursts -system.physmem.perBankRdBursts::12 980154 # Per bank write bursts -system.physmem.perBankRdBursts::13 980093 # Per bank write bursts -system.physmem.perBankRdBursts::14 980167 # Per bank write bursts +system.physmem.perBankRdBursts::11 979544 # Per bank write bursts +system.physmem.perBankRdBursts::12 980153 # Per bank write bursts +system.physmem.perBankRdBursts::13 980076 # Per bank write bursts +system.physmem.perBankRdBursts::14 980177 # Per bank write bursts system.physmem.perBankRdBursts::15 980110 # Per bank write bursts -system.physmem.perBankWrBursts::0 6645 # Per bank write bursts -system.physmem.perBankWrBursts::1 6506 # Per bank write bursts -system.physmem.perBankWrBursts::2 6513 # Per bank write bursts -system.physmem.perBankWrBursts::3 6561 # Per bank write bursts -system.physmem.perBankWrBursts::4 6643 # Per bank write bursts -system.physmem.perBankWrBursts::5 6949 # Per bank write bursts -system.physmem.perBankWrBursts::6 6933 # Per bank write bursts -system.physmem.perBankWrBursts::7 6786 # Per bank write bursts -system.physmem.perBankWrBursts::8 6904 # Per bank write bursts -system.physmem.perBankWrBursts::9 6725 # Per bank write bursts -system.physmem.perBankWrBursts::10 6221 # Per bank write bursts -system.physmem.perBankWrBursts::11 6029 # Per bank write bursts -system.physmem.perBankWrBursts::12 6513 # Per bank write bursts -system.physmem.perBankWrBursts::13 6297 # Per bank write bursts +system.physmem.perBankWrBursts::0 6626 # Per bank write bursts +system.physmem.perBankWrBursts::1 6496 # Per bank write bursts +system.physmem.perBankWrBursts::2 6497 # Per bank write bursts +system.physmem.perBankWrBursts::3 6558 # Per bank write bursts +system.physmem.perBankWrBursts::4 6634 # Per bank write bursts +system.physmem.perBankWrBursts::5 6937 # Per bank write bursts +system.physmem.perBankWrBursts::6 6920 # Per bank write bursts +system.physmem.perBankWrBursts::7 6772 # Per bank write bursts +system.physmem.perBankWrBursts::8 6893 # Per bank write bursts +system.physmem.perBankWrBursts::9 6718 # Per bank write bursts +system.physmem.perBankWrBursts::10 6212 # Per bank write bursts +system.physmem.perBankWrBursts::11 6014 # Per bank write bursts +system.physmem.perBankWrBursts::12 6499 # Per bank write bursts +system.physmem.perBankWrBursts::13 6274 # Per bank write bursts system.physmem.perBankWrBursts::14 6516 # Per bank write bursts -system.physmem.perBankWrBursts::15 6525 # Per bank write bursts +system.physmem.perBankWrBursts::15 6506 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2629690290000 # Total gap between requests +system.physmem.totGap 2631266900000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6718 # Read request sizes (log2) +system.physmem.readPktSize::2 6664 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152158 # Read request sizes (log2) +system.physmem.readPktSize::6 152172 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754070 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57651 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1128915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 971082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 971066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 973046 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 971647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 972454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2865167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2865325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3808659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 25323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 23577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 23920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 23318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 22983 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 22230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 22150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57666 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1139961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 982153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 987606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1093203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 997403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1062031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2774379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2684271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3510460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 111897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 101929 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 96137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 92760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -157,60 +169,60 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 339 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 318 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see @@ -221,373 +233,350 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 990183 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1014.719065 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1002.794597 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 86.877825 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3622 0.37% 0.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 3291 0.33% 0.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1715 0.17% 0.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1178 0.12% 0.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 920 0.09% 1.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 703 0.07% 1.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 532 0.05% 1.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 420 0.04% 1.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 977802 98.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 990183 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4537 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3458.425832 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 54557.622307 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 4511 99.43% 99.43% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 8 0.18% 99.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 4 0.09% 99.69% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::393216-458751 2 0.04% 99.74% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 3 0.07% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.13% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1040545 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.548041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.383017 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 204.411888 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22983 2.21% 2.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22832 2.19% 4.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9281 0.89% 5.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2277 0.22% 5.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2320 0.22% 5.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1623 0.16% 5.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9470 0.91% 6.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 703 0.07% 6.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 969056 93.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1040545 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6005 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2612.962531 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 47489.703553 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 5977 99.53% 99.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 11 0.18% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.77% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 3 0.05% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4537 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4537 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.201675 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.361663 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.873768 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 5 0.11% 0.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 7 0.15% 0.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 5 0.11% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 2 0.04% 0.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 2 0.04% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 4 0.09% 0.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 6 0.13% 0.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 3 0.07% 0.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 3 0.07% 0.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 3 0.07% 0.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 3 0.07% 0.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 2 0.04% 0.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 4 0.09% 1.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 7 0.15% 1.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 17 0.37% 1.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1491 32.86% 34.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 339 7.47% 41.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 208 4.58% 46.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1050 23.14% 69.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 16 0.35% 70.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 12 0.26% 70.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.44% 70.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 24 0.53% 71.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 18 0.40% 71.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 14 0.31% 71.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 18 0.40% 72.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 18 0.40% 72.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 19 0.42% 73.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 13 0.29% 73.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 11 0.24% 73.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 12 0.26% 73.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 11 0.24% 74.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 3 0.07% 74.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.04% 74.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.02% 74.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1015 22.37% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 76 1.68% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 13 0.29% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 42 0.93% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 5 0.11% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 5 0.11% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 5 0.11% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4537 # Writes before turning the bus around for reads -system.physmem.totQLat 592300556750 # Total ticks spent queuing -system.physmem.totMemAccLat 700300341750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454390000 # Total ticks spent in databus transfers -system.physmem.totBankLat 29545395000 # Total ticks spent accessing banks -system.physmem.avgQLat 37748.08 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1882.97 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6005 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6005 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.497419 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.315574 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.169730 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 7 0.12% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 6 0.10% 0.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 6 0.10% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 4 0.07% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 3 0.05% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 1 0.02% 0.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 3 0.05% 0.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 3 0.05% 0.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 4 0.07% 0.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 3 0.05% 0.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 4 0.07% 0.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 8 0.13% 0.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 3 0.05% 0.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 4 0.07% 0.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 16 0.27% 1.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1890 31.47% 32.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 59 0.98% 33.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3765 62.70% 96.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 21 0.35% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 14 0.23% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 16 0.27% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 19 0.32% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 20 0.33% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 12 0.20% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.10% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 23 0.38% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 21 0.35% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 18 0.30% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 14 0.23% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 10 0.17% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 11 0.18% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 11 0.18% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6005 # Writes before turning the bus around for reads +system.physmem.totQLat 402822623250 # Total ticks spent queuing +system.physmem.totMemAccLat 697026192000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454285000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25672.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44631.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44422.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.89 # Average write queue length when enqueuing -system.physmem.readRowHits 14676487 # Number of row buffer hits during reads -system.physmem.writeRowHits 89750 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.26 # Row buffer hit rate for writes -system.physmem.avgGap 159349.78 # Average gap between requests -system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.16 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54426652 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743677 # Transaction distribution -system.membus.trans_dist::ReadResp 16743677 # Transaction distribution -system.membus.trans_dist::WriteReq 763441 # Transaction distribution -system.membus.trans_dist::WriteResp 763441 # Transaction distribution -system.membus.trans_dist::Writeback 57651 # Transaction distribution +system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.68 # Average write queue length when enqueuing +system.physmem.readRowHits 14667283 # Number of row buffer hits during reads +system.physmem.writeRowHits 88101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.84 # Row buffer hit rate for writes +system.physmem.avgGap 159446.06 # Average gap between requests +system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2257272287500 # Time in different power states +system.physmem.memoryStateTime::REF 87863880000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 286133845000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 54394584 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743630 # Transaction distribution +system.membus.trans_dist::ReadResp 16743630 # Transaction distribution +system.membus.trans_dist::WriteReq 763389 # Transaction distribution +system.membus.trans_dist::WriteResp 763389 # Transaction distribution +system.membus.trans_dist::Writeback 57666 # Transaction distribution system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution -system.membus.trans_dist::ReadExReq 131342 # Transaction distribution -system.membus.trans_dist::ReadExResp 131342 # Transaction distribution +system.membus.trans_dist::ReadExReq 131349 # Transaction distribution +system.membus.trans_dist::ReadExResp 131349 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383092 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892577 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892408 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279372 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35343436 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390550 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16470928 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18869222 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472360 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18870654 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143125478 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143125478 # Total data (bytes) +system.membus.tot_pkt_size::total 143126910 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143126910 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225762000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225776000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3755500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3753500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171181500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171055500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4987933108 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4987830629 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 38819144750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 38455776750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62041 # number of replacements -system.l2c.tags.tagsinuse 51600.507824 # Cycle average of tags in use -system.l2c.tags.total_refs 1699332 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127423 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.336148 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2574803290500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38204.625202 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2677.995545 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3048.557344 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4342.999627 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3326.329216 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.582956 # Average percentage of cache occupancy +system.l2c.tags.replacements 62060 # number of replacements +system.l2c.tags.tagsinuse 51620.522057 # Cycle average of tags in use +system.l2c.tags.total_refs 1699511 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127448 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.334937 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2576403565500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38224.293292 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000700 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2572.111888 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3079.413643 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4449.101058 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3295.601290 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583256 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.040863 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046517 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.039247 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046988 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.066269 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.050756 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787361 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65382 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2132 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6447 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56751 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.997650 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17277037 # Number of tag accesses -system.l2c.tags.data_accesses 17277037 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9996 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3617 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 411271 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 183421 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9883 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 433200 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 187065 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241955 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596489 # number of Writeback hits -system.l2c.Writeback_hits::total 596489 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.067888 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050287 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787667 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65388 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2135 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6611 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56587 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.997742 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17278044 # Number of tag accesses +system.l2c.tags.data_accesses 17278044 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 10108 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3664 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 418356 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 187332 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9807 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3568 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 426125 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 183124 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1242084 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596476 # number of Writeback hits +system.l2c.Writeback_hits::total 596476 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 11 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55903 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58636 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114539 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9996 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3617 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 411271 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 239324 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9883 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 433200 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 245701 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356494 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9996 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3617 # number of overall hits -system.l2c.overall_hits::cpu0.inst 411271 # number of overall hits -system.l2c.overall_hits::cpu0.data 239324 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9883 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3502 # number of overall hits -system.l2c.overall_hits::cpu1.inst 433200 # number of overall hits -system.l2c.overall_hits::cpu1.data 245701 # number of overall hits -system.l2c.overall_hits::total 1356494 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 57771 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 56762 # 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average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58025.807203 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57988.084297 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57853.998478 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57134.782609 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57158.678388 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57162.247256 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -729,7 +715,6 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate @@ -739,39 +724,39 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52790847 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471761 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471761 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763441 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763441 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596489 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2909 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2909 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247515 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247515 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725013 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5754007 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20046 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50514 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549580 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54750240 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83796742 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28484 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138654986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138654986 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 168824 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808734000 # Layer occupancy (ticks) +system.toL2Bus.throughput 52759012 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471877 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471877 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763389 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763389 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596476 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2915 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2915 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247510 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247510 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725028 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753762 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20291 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50582 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549663 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54751132 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83793442 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138653174 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138653174 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 170100 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808682000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865148750 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865303000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4420266392 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4420412121 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12925000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13057000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30634250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30666250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48160270 # Throughput (bytes/s) +system.iobus.throughput 48131413 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16715394 # Transaction distribution system.iobus.trans_dist::ReadResp 16715394 # Transaction distribution system.iobus.trans_dist::WriteReq 8184 # Transaction distribution @@ -881,7 +866,7 @@ system.iobus.reqLayer25.occupancy 15532032000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374908000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38823243250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 39139813250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -906,25 +891,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7344844 # DTB read hits -system.cpu0.dtb.read_misses 6860 # DTB read misses -system.cpu0.dtb.write_hits 5551128 # DTB write hits -system.cpu0.dtb.write_misses 1832 # DTB write misses -system.cpu0.dtb.flush_tlb 2493 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7447963 # DTB read hits +system.cpu0.dtb.read_misses 7119 # DTB read misses +system.cpu0.dtb.write_hits 5549645 # DTB write hits +system.cpu0.dtb.write_misses 1815 # DTB write misses +system.cpu0.dtb.flush_tlb 2495 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 699 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6351 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6552 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 220 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7351704 # DTB read accesses -system.cpu0.dtb.write_accesses 5552960 # DTB write accesses +system.cpu0.dtb.perms_faults 230 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7455082 # DTB read accesses +system.cpu0.dtb.write_accesses 5551460 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12895972 # DTB hits -system.cpu0.dtb.misses 8692 # DTB misses -system.cpu0.dtb.accesses 12904664 # DTB accesses +system.cpu0.dtb.hits 12997608 # DTB hits +system.cpu0.dtb.misses 8934 # DTB misses +system.cpu0.dtb.accesses 13006542 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -946,125 +931,160 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30211154 # ITB inst hits -system.cpu0.itb.inst_misses 3603 # ITB inst misses +system.cpu0.itb.inst_hits 30500446 # ITB inst hits +system.cpu0.itb.inst_misses 3756 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2493 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2495 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 699 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2758 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2854 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30214757 # ITB inst accesses -system.cpu0.itb.hits 30211154 # DTB hits -system.cpu0.itb.misses 3603 # DTB misses -system.cpu0.itb.accesses 30214757 # DTB accesses -system.cpu0.numCycles 2627736532 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30504202 # ITB inst accesses +system.cpu0.itb.hits 30500446 # DTB hits +system.cpu0.itb.misses 3756 # DTB misses +system.cpu0.itb.accesses 30504202 # DTB accesses +system.cpu0.numCycles 2629256644 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29624937 # Number of instructions committed -system.cpu0.committedOps 37728426 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34074958 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4583 # Number of float alu accesses -system.cpu0.num_func_calls 1045164 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3935196 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34074958 # number of integer instructions -system.cpu0.num_fp_insts 4583 # number of float instructions -system.cpu0.num_int_register_reads 197582111 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36713164 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3288 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written -system.cpu0.num_mem_refs 13470170 # number of memory refs -system.cpu0.num_load_insts 7667939 # Number of load instructions -system.cpu0.num_store_insts 5802231 # Number of store instructions -system.cpu0.num_idle_cycles 2282002616.045546 # Number of idle cycles -system.cpu0.num_busy_cycles 345733915.954454 # Number of busy cycles -system.cpu0.not_idle_fraction 0.131571 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.868429 # Percentage of idle cycles -system.cpu0.Branches 5074688 # Number of branches fetched +system.cpu0.committedInsts 29876886 # Number of instructions committed +system.cpu0.committedOps 37981807 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34283991 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4842 # Number of float alu accesses +system.cpu0.num_func_calls 1058651 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3976280 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34283991 # number of integer instructions +system.cpu0.num_fp_insts 4842 # number of float instructions +system.cpu0.num_int_register_reads 198984803 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36984019 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3491 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1354 # number of times the floating registers were written +system.cpu0.num_mem_refs 13572889 # number of memory refs +system.cpu0.num_load_insts 7771976 # Number of load instructions +system.cpu0.num_store_insts 5800913 # Number of store instructions +system.cpu0.num_idle_cycles 2280913483.245505 # Number of idle cycles +system.cpu0.num_busy_cycles 348343160.754495 # Number of busy cycles +system.cpu0.not_idle_fraction 0.132487 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.867513 # Percentage of idle cycles +system.cpu0.Branches 5129174 # Number of branches fetched +system.cpu0.op_class::No_OpClass 12846 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 24984996 64.70% 64.73% # Class of executed instruction +system.cpu0.op_class::IntMult 44336 0.11% 64.85% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 930 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::MemRead 7771976 20.13% 84.98% # Class of executed instruction +system.cpu0.op_class::MemWrite 5800913 15.02% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 38615997 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856147 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.849495 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60652706 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856659 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.801458 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 20216402250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 158.742483 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 352.107012 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.310044 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.687709 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997753 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 83028 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 856182 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.863139 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60651276 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856694 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.796896 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 20196898250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 155.776297 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 355.086842 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.304251 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.693529 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997780 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62366026 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62366026 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29795008 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30857698 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60652706 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29795008 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30857698 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60652706 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29795008 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30857698 # number of overall hits -system.cpu0.icache.overall_hits::total 60652706 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 416146 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 440514 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856660 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 416146 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 440514 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856660 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7899020798 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7648829935 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15547850733 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7899020798 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7648829935 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15547850733 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90318421750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91762441000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182080862750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13218125626 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13022508499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26240634125 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103536547376 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104784949499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208321496875 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027528 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026897 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027205 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024995 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023998 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048462 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044947 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046712 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026433 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025657 # mshr miss rate for demand accesses +system.cpu0.dcache.writebacks::writebacks 596476 # number of writebacks +system.cpu0.dcache.writebacks::total 596476 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186473 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 182643 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369116 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 125422 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 125003 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250425 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6121 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5448 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11569 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 311895 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 307646 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619541 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 311895 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 307646 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619541 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2396807750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2338699250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4735507000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5342161454 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5370757779 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10712919233 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70030750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67311250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137342000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7738969204 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7709457029 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15448426233 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7738969204 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7709457029 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15448426233 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90834275250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91243928750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182078204000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13255943399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12983118997 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26239062396 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104090218649 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104227047747 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208317266396 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027699 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026717 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027204 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024872 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024120 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024491 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048873 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044468 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046695 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026488 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.026038 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026433 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025657 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026488 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026038 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12898.315945 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12791.659072 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12844.417008 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43959.059248 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42334.668852 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43152.714927 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.127695 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12303.165584 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11854.047866 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25587.270854 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24605.859777 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25094.866435 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25587.270854 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24605.859777 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25094.866435 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12853.376896 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12804.757094 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12829.319238 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42593.495990 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42965.031071 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42778.952712 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.063552 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12355.222100 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11871.553289 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24812.738915 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25059.506800 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24935.276653 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24812.738915 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25059.506800 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24935.276653 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1348,25 +1364,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7655819 # DTB read hits -system.cpu1.dtb.read_misses 7243 # DTB read misses -system.cpu1.dtb.write_hits 5681899 # DTB write hits -system.cpu1.dtb.write_misses 1828 # DTB write misses +system.cpu1.dtb.read_hits 7552227 # DTB read hits +system.cpu1.dtb.read_misses 6971 # DTB read misses +system.cpu1.dtb.write_hits 5683121 # DTB write hits +system.cpu1.dtb.write_misses 1859 # DTB write misses system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 740 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6711 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6603 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7663062 # DTB read accesses -system.cpu1.dtb.write_accesses 5683727 # DTB write accesses +system.cpu1.dtb.perms_faults 222 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7559198 # DTB read accesses +system.cpu1.dtb.write_accesses 5684980 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13337718 # DTB hits -system.cpu1.dtb.misses 9071 # DTB misses -system.cpu1.dtb.accesses 13346789 # DTB accesses +system.cpu1.dtb.hits 13235348 # DTB hits +system.cpu1.dtb.misses 8830 # DTB misses +system.cpu1.dtb.accesses 13244178 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1388,50 +1404,85 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 31298229 # ITB inst hits -system.cpu1.itb.inst_misses 3696 # ITB inst misses +system.cpu1.itb.inst_hits 31007524 # ITB inst hits +system.cpu1.itb.inst_misses 3606 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 740 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2898 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2820 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31301925 # ITB inst accesses -system.cpu1.itb.hits 31298229 # DTB hits -system.cpu1.itb.misses 3696 # DTB misses -system.cpu1.itb.accesses 31301925 # DTB accesses -system.cpu1.numCycles 2631652887 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 31011130 # ITB inst accesses +system.cpu1.itb.hits 31007524 # DTB hits +system.cpu1.itb.misses 3606 # DTB misses +system.cpu1.itb.accesses 31011130 # DTB accesses +system.cpu1.numCycles 2633285995 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30590318 # Number of instructions committed -system.cpu1.committedOps 38894351 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35148183 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5686 # Number of float alu accesses -system.cpu1.num_func_calls 1095318 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4014750 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35148183 # number of integer instructions -system.cpu1.num_fp_insts 5686 # number of float instructions -system.cpu1.num_int_register_reads 203876321 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37823170 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4205 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1482 # number of times the floating registers were written -system.cpu1.num_mem_refs 13931138 # number of memory refs -system.cpu1.num_load_insts 7996929 # Number of load instructions -system.cpu1.num_store_insts 5934209 # Number of store instructions -system.cpu1.num_idle_cycles 2293790821.520695 # Number of idle cycles -system.cpu1.num_busy_cycles 337862065.479305 # Number of busy cycles -system.cpu1.not_idle_fraction 0.128384 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.871616 # Percentage of idle cycles -system.cpu1.Branches 5235663 # Number of branches fetched +system.cpu1.committedInsts 30336967 # Number of instructions committed +system.cpu1.committedOps 38639043 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34937438 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5427 # Number of float alu accesses +system.cpu1.num_func_calls 1081754 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3973481 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34937438 # number of integer instructions +system.cpu1.num_fp_insts 5427 # number of float instructions +system.cpu1.num_int_register_reads 202463130 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37550545 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4002 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1426 # number of times the floating registers were written +system.cpu1.num_mem_refs 13827657 # number of memory refs +system.cpu1.num_load_insts 7892397 # Number of load instructions +system.cpu1.num_store_insts 5935260 # Number of store instructions +system.cpu1.num_idle_cycles 2291893093.755996 # Number of idle cycles +system.cpu1.num_busy_cycles 341392901.244004 # Number of busy cycles +system.cpu1.not_idle_fraction 0.129645 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.870355 # Percentage of idle cycles +system.cpu1.Branches 5180924 # Number of branches fetched +system.cpu1.op_class::No_OpClass 15672 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 25411566 64.66% 64.70% # Class of executed instruction +system.cpu1.op_class::IntMult 43588 0.11% 64.81% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1181 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::MemRead 7892397 20.08% 84.90% # Class of executed instruction +system.cpu1.op_class::MemWrite 5935260 15.10% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 39299664 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1450,10 +1501,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1783080197250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1783080197250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1783080197250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1783080197250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779915025250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1779915025250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779915025250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1779915025250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |