diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
| commit | cfb805cc71bd1c4b72691b69faa879663e548c11 (patch) | |
| tree | 4ef4be8b34eb3722e303546a96956b1adaa3315b /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing | |
| parent | 612f8f074fa1099cf70faf495d46cc647762a031 (diff) | |
| download | gem5-cfb805cc71bd1c4b72691b69faa879663e548c11.tar.xz | |
stats: update stats for ARMv8 changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing')
4 files changed, 1360 insertions, 1084 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index 6f15742b0..1d8001986 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,19 +96,21 @@ voltage_domain=system.voltage_domain [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -150,10 +162,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -161,6 +198,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -208,24 +246,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -233,6 +307,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -243,19 +318,21 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU -children=dtb isa itb tracer +children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -270,10 +347,34 @@ system=system tracer=system.cpu1.tracer workload= +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -281,6 +382,7 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -288,24 +390,59 @@ sys=system type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -313,6 +450,7 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -951,7 +1089,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr index 4dfb66c84..fdcb49ed7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr @@ -11,8 +11,42 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout index 25848b995..16dc9f3ee 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout @@ -1,8 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:31:08 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 19:11:44 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x6f57400 0x6f57400 + 0: system.cpu1.isa: ISA system set to: 0x6f57400 0x6f57400 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index e79723ba6..b41d3a6bf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,81 +1,81 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.629717 # Number of seconds simulated -sim_ticks 2629717216500 # Number of ticks simulated -final_tick 2629717216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.629734 # Number of seconds simulated +sim_ticks 2629733911500 # Number of ticks simulated +final_tick 2629733911500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 592417 # Simulator instruction rate (inst/s) -host_op_rate 753843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25873243563 # Simulator tick rate (ticks/s) -host_mem_usage 401372 # Number of bytes of host memory used -host_seconds 101.64 # Real time elapsed on the host -sim_insts 60212334 # Number of instructions simulated -sim_ops 76619433 # Number of ops (including micro ops) simulated +host_inst_rate 461706 # Simulator instruction rate (inst/s) +host_op_rate 587514 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20164609948 # Simulator tick rate (ticks/s) +host_mem_usage 422284 # Number of bytes of host memory used +host_seconds 130.41 # Real time elapsed on the host +sim_insts 60212552 # Number of instructions simulated +sim_ops 76619667 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 298016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4661584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 300040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4644312 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 406404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4399060 # Number of bytes read from this memory -system.physmem.bytes_read::total 134021512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 298016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 406404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3689984 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1527272 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1489008 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706264 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 404420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4416276 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 300040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 404420 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704460 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3689920 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1526984 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1489296 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706200 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 72871 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10900 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 72603 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6366 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 68770 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690901 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57656 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 381818 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 372252 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811726 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47250805 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 69039 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690912 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57655 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 381746 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 372324 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811725 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47250505 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 113326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1772656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 114095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1766077 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 154543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1672826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50964230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 113326 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 154543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267869 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1403187 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 580774 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 566224 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2550184 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1403187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47250805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 153787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1679362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50963900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 114095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 153787 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1403153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 580661 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 566330 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550144 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1403153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47250505 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 113326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2353430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 114095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2346738 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 154543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2239050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53514414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690901 # Number of read requests accepted -system.physmem.writeReqs 811726 # Number of write requests accepted -system.physmem.readBursts 15690901 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811726 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004215808 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 153787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2245692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53514044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690912 # Number of read requests accepted +system.physmem.writeReqs 811725 # Number of write requests accepted +system.physmem.readBursts 15690912 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811725 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004216512 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6837952 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134021512 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6706264 # Total written bytes from the system interface side +system.physmem.bytesWritten 6837440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134021496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706200 # Total written bytes from the system interface side system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 704883 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4518 # Number of requests that are neither read nor write +system.physmem.mergedWrBursts 704890 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980392 # Per bank write bursts system.physmem.perBankRdBursts::1 980205 # Per bank write bursts system.physmem.perBankRdBursts::2 980222 # Per bank write bursts @@ -88,60 +88,60 @@ system.physmem.perBankRdBursts::8 980615 # Pe system.physmem.perBankRdBursts::9 980431 # Per bank write bursts system.physmem.perBankRdBursts::10 979815 # Per bank write bursts system.physmem.perBankRdBursts::11 979558 # Per bank write bursts -system.physmem.perBankRdBursts::12 980154 # Per bank write bursts +system.physmem.perBankRdBursts::12 980153 # Per bank write bursts system.physmem.perBankRdBursts::13 980093 # Per bank write bursts -system.physmem.perBankRdBursts::14 980155 # Per bank write bursts +system.physmem.perBankRdBursts::14 980167 # Per bank write bursts system.physmem.perBankRdBursts::15 980109 # Per bank write bursts -system.physmem.perBankWrBursts::0 6731 # Per bank write bursts -system.physmem.perBankWrBursts::1 6599 # Per bank write bursts -system.physmem.perBankWrBursts::2 6610 # Per bank write bursts -system.physmem.perBankWrBursts::3 6672 # Per bank write bursts -system.physmem.perBankWrBursts::4 6746 # Per bank write bursts +system.physmem.perBankWrBursts::0 6735 # Per bank write bursts +system.physmem.perBankWrBursts::1 6596 # Per bank write bursts +system.physmem.perBankWrBursts::2 6612 # Per bank write bursts +system.physmem.perBankWrBursts::3 6671 # Per bank write bursts +system.physmem.perBankWrBursts::4 6747 # Per bank write bursts system.physmem.perBankWrBursts::5 7052 # Per bank write bursts -system.physmem.perBankWrBursts::6 7033 # Per bank write bursts -system.physmem.perBankWrBursts::7 6881 # Per bank write bursts -system.physmem.perBankWrBursts::8 7002 # Per bank write bursts -system.physmem.perBankWrBursts::9 6827 # Per bank write bursts -system.physmem.perBankWrBursts::10 6323 # Per bank write bursts -system.physmem.perBankWrBursts::11 6122 # Per bank write bursts -system.physmem.perBankWrBursts::12 6612 # Per bank write bursts -system.physmem.perBankWrBursts::13 6399 # Per bank write bursts +system.physmem.perBankWrBursts::6 7031 # Per bank write bursts +system.physmem.perBankWrBursts::7 6880 # Per bank write bursts +system.physmem.perBankWrBursts::8 6999 # Per bank write bursts +system.physmem.perBankWrBursts::9 6828 # Per bank write bursts +system.physmem.perBankWrBursts::10 6320 # Per bank write bursts +system.physmem.perBankWrBursts::11 6125 # Per bank write bursts +system.physmem.perBankWrBursts::12 6609 # Per bank write bursts +system.physmem.perBankWrBursts::13 6397 # Per bank write bursts system.physmem.perBankWrBursts::14 6618 # Per bank write bursts -system.physmem.perBankWrBursts::15 6616 # Per bank write bursts +system.physmem.perBankWrBursts::15 6615 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2629712785000 # Total gap between requests +system.physmem.totGap 2629729480000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6706 # Read request sizes (log2) +system.physmem.readPktSize::2 6718 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152163 # Read request sizes (log2) +system.physmem.readPktSize::6 152162 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754070 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57656 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1290849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1134741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1135188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3791353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2690884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2690157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2706986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 51561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 56279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57655 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1274921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1118631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1118848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3789956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2706257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2705513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2723130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 52826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 49 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -157,28 +157,28 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4975 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4687 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -189,299 +189,317 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90454 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11177.544033 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1030.436917 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16744.733089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23393 25.86% 25.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14737 16.29% 42.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2929 3.24% 45.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2185 2.42% 47.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1403 1.55% 49.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1153 1.27% 50.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 940 1.04% 51.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1175 1.30% 52.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 610 0.67% 53.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 557 0.62% 54.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 555 0.61% 54.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 601 0.66% 55.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 293 0.32% 55.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 323 0.36% 56.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 207 0.23% 56.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 643 0.71% 57.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 173 0.19% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 141 0.16% 57.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 139 0.15% 57.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 211 0.23% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 108 0.12% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2249 2.49% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 135 0.15% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 71 0.08% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 48 0.05% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 33 0.04% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 98 0.11% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 34 0.04% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 27 0.03% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 23 0.03% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 231 0.26% 61.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 24 0.03% 61.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 27 0.03% 61.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 30 0.03% 61.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 143 0.16% 61.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 12 0.01% 61.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 18 0.02% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 17 0.02% 61.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 86 0.10% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 22 0.02% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 12 0.01% 61.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 15 0.02% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 205 0.23% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 13 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 20 0.02% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 10 0.01% 62.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 404 0.45% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 18 0.02% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 8 0.01% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 8 0.01% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 21 0.02% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 11 0.01% 62.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 14 0.02% 62.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 16 0.02% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 82 0.09% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 9 0.01% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 15 0.02% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 35 0.04% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 129 0.14% 62.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 12 0.01% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 9 0.01% 62.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 7 0.01% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 283 0.31% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 7 0.01% 63.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 5 0.01% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 10 0.01% 63.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 6 0.01% 63.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 5 0.01% 63.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 11 0.01% 63.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 8 0.01% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 271 0.30% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 14 0.02% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 4 0.00% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 136 0.15% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 11 0.01% 63.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 341 0.38% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 2 0.00% 64.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 14 0.02% 64.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 4 0.00% 64.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 205 0.23% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 168 0.19% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 59 0.07% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 3 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 126 0.14% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 267 0.30% 65.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 256 0.28% 65.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 5 0.01% 65.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 65 0.07% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 454 0.50% 66.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 1 0.00% 66.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 9 0.01% 66.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 2 0.00% 66.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 192 0.21% 66.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 2 0.00% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 261 0.29% 66.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 193 0.21% 66.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 9 0.01% 66.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 455 0.50% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 1 0.00% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 64 0.07% 67.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 5 0.01% 67.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 257 0.28% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10183 1 0.00% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 265 0.29% 67.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 124 0.14% 68.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 4 0.00% 68.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 195 0.22% 68.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11207 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 336 0.37% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 123 0.14% 68.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 266 0.29% 69.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 267 0.30% 69.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 121 0.13% 69.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 75 0.08% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 4 0.00% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 387 0.43% 70.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 197 0.22% 70.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 78 0.09% 70.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13895 1 0.00% 70.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 129 0.14% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 206 0.23% 70.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 65 0.07% 70.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 65 0.07% 70.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 71 0.08% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 1 0.00% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 455 0.50% 71.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 66 0.07% 71.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 131 0.14% 71.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 128 0.14% 71.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 401 0.44% 72.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 130 0.14% 72.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 129 0.14% 72.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 68 0.08% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 460 0.51% 73.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17600-17607 1 0.00% 73.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 71 0.08% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 66 0.07% 73.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 64 0.07% 73.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 208 0.23% 73.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 128 0.14% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 77 0.09% 73.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 196 0.22% 74.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 1 0.00% 74.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 386 0.43% 74.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 3 0.00% 74.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 72 0.08% 74.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 120 0.13% 74.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 270 0.30% 74.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 265 0.29% 75.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 123 0.14% 75.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 334 0.37% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 195 0.22% 75.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21824-21831 1 0.00% 75.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 3 0.00% 76.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 127 0.14% 76.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 264 0.29% 76.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 1 0.00% 76.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 255 0.28% 76.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 5 0.01% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 65 0.07% 76.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 452 0.50% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 9 0.01% 77.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 192 0.21% 77.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 3 0.00% 77.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 259 0.29% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 1 0.00% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 193 0.21% 78.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 7 0.01% 78.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 454 0.50% 78.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 66 0.07% 78.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 5 0.01% 78.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 256 0.28% 78.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 266 0.29% 79.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 124 0.14% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 2 0.00% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 195 0.22% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 332 0.37% 79.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 123 0.14% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 266 0.29% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 267 0.30% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 122 0.13% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 74 0.08% 80.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 4 0.00% 80.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 387 0.43% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 194 0.21% 81.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 77 0.09% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 1 0.00% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 128 0.14% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 205 0.23% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 64 0.07% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 66 0.07% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 71 0.08% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 457 0.51% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 65 0.07% 82.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 130 0.14% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 128 0.14% 83.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 400 0.44% 83.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 128 0.14% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 135 0.15% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 65 0.07% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 456 0.50% 84.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 71 0.08% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 66 0.07% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 64 0.07% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 205 0.23% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 128 0.14% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 76 0.08% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 194 0.21% 85.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 386 0.43% 85.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 3 0.00% 85.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 73 0.08% 85.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 121 0.13% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 265 0.29% 86.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 265 0.29% 86.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 123 0.14% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 333 0.37% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 195 0.22% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 2 0.00% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 125 0.14% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 265 0.29% 87.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 256 0.28% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 5 0.01% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 65 0.07% 87.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 452 0.50% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 7 0.01% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 192 0.21% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 259 0.29% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 3 0.00% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 192 0.21% 89.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 9 0.01% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 452 0.50% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 64 0.07% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 5 0.01% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 255 0.28% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 264 0.29% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 126 0.14% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 3 0.00% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 194 0.21% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 335 0.37% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 123 0.14% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 264 0.29% 91.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 264 0.29% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 120 0.13% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 72 0.08% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 4 0.00% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 385 0.43% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 194 0.21% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 76 0.08% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 128 0.14% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 209 0.23% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 65 0.07% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 67 0.07% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 73 0.08% 93.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 459 0.51% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 3 0.00% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 69 0.08% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48448-48455 1 0.00% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 129 0.14% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 129 0.14% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5220 5.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90454 # Bytes accessed per row activation -system.physmem.totQLat 377144928750 # Total ticks spent queuing -system.physmem.totMemAccLat 474552728750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454360000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18953440000 # Total ticks spent accessing banks -system.physmem.avgQLat 24035.94 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1207.93 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 90412 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11182.734327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1029.544171 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16746.961445 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23519 26.01% 26.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14711 16.27% 42.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2935 3.25% 45.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2119 2.34% 47.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1367 1.51% 49.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1185 1.31% 50.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 943 1.04% 51.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1073 1.19% 52.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 614 0.68% 53.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 515 0.57% 54.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 541 0.60% 54.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 575 0.64% 55.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 297 0.33% 55.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 299 0.33% 56.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 230 0.25% 56.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 594 0.66% 56.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 170 0.19% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 148 0.16% 57.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 128 0.14% 57.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 277 0.31% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 134 0.15% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2231 2.47% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 229 0.25% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 52 0.06% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 35 0.04% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 49 0.05% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 107 0.12% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 29 0.03% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 27 0.03% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 27 0.03% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 349 0.39% 61.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 23 0.03% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 21 0.02% 61.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 26 0.03% 61.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 89 0.10% 61.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 16 0.02% 61.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 22 0.02% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 22 0.02% 61.76% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::48384-48391 73 0.08% 94.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 1 0.00% 94.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 66 0.07% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5357 5.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90412 # Bytes accessed per row activation +system.physmem.totQLat 377428295750 # Total ticks spent queuing +system.physmem.totMemAccLat 474604408250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454415000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18721697500 # Total ticks spent accessing banks +system.physmem.avgQLat 24053.99 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1193.16 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30243.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30247.14 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s @@ -492,13 +510,13 @@ system.physmem.busUtilRead 2.98 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing -system.physmem.readRowHits 15616330 # Number of row buffer hits during reads -system.physmem.writeRowHits 90931 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.readRowHits 15616374 # Number of row buffer hits during reads +system.physmem.writeRowHits 90932 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads system.physmem.writeRowHitRate 85.11 # Row buffer hit rate for writes -system.physmem.avgGap 159351.16 # Average gap between requests +system.physmem.avgGap 159352.08 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.39 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -511,259 +529,259 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54426353 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743636 # Transaction distribution -system.membus.trans_dist::ReadResp 16743636 # Transaction distribution +system.membus.throughput 54425977 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743649 # Transaction distribution +system.membus.trans_dist::ReadResp 16743649 # Transaction distribution system.membus.trans_dist::WriteReq 763424 # Transaction distribution system.membus.trans_dist::WriteResp 763424 # Transaction distribution -system.membus.trans_dist::Writeback 57656 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4518 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4518 # Transaction distribution -system.membus.trans_dist::ReadExReq 131342 # Transaction distribution -system.membus.trans_dist::ReadExResp 131342 # Transaction distribution +system.membus.trans_dist::Writeback 57655 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution +system.membus.trans_dist::ReadExReq 131340 # Transaction distribution +system.membus.trans_dist::ReadExResp 131340 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892570 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279449 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343496 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35343513 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471520 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18869661 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18869581 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143125917 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143125917 # Total data (bytes) +system.membus.tot_pkt_size::total 143125837 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143125837 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225680000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225677000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3756000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3756500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171618500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171612500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4990533473 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4990561725 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35075577250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35076949500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62046 # number of replacements -system.l2c.tags.tagsinuse 51605.865819 # Cycle average of tags in use -system.l2c.tags.total_refs 1699437 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127429 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.336344 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2574782383500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38213.733489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2749.245070 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3097.480060 # Average occupied blocks per requestor +system.l2c.tags.replacements 62045 # number of replacements +system.l2c.tags.tagsinuse 51605.891965 # Cycle average of tags in use +system.l2c.tags.total_refs 1699472 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127428 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.336723 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2574797983500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38210.959857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000702 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2799.685375 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3087.560110 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4271.539066 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3273.867246 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583095 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 4221.092196 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3286.593539 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583053 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.041950 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.047264 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.042720 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.047112 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.065179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.049955 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.064409 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050149 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.787443 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2132 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6483 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2131 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6484 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 56716 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17277508 # Number of tag accesses -system.l2c.tags.data_accesses 17277508 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9827 # number of ReadReq hits +system.l2c.tags.tag_accesses 17277894 # Number of tag accesses +system.l2c.tags.data_accesses 17277894 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 9810 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3607 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 412393 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 183168 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10051 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3578 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 432141 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 187290 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1242055 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596450 # number of Writeback hits -system.l2c.Writeback_hits::total 596450 # number of Writeback hits +system.l2c.ReadReq_hits::cpu0.inst 412170 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 183158 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10090 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3595 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 432364 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 187312 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1242106 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596455 # number of Writeback hits +system.l2c.Writeback_hits::total 596455 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57240 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57291 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114531 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9827 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::cpu0.data 57198 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57329 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114527 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9810 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3607 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 412393 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 240408 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10051 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3578 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 432141 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 244581 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356586 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9827 # number of overall hits +system.l2c.demand_hits::cpu0.inst 412170 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 240356 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10090 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3595 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 432364 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 244641 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356633 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9810 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3607 # number of overall hits -system.l2c.overall_hits::cpu0.inst 412393 # number of overall hits -system.l2c.overall_hits::cpu0.data 240408 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10051 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3578 # number of overall hits -system.l2c.overall_hits::cpu1.inst 432141 # number of overall hits -system.l2c.overall_hits::cpu1.data 244581 # number of overall hits -system.l2c.overall_hits::total 1356586 # number of overall hits +system.l2c.overall_hits::cpu0.inst 412170 # number of overall hits +system.l2c.overall_hits::cpu0.data 240356 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10090 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3595 # number of overall hits +system.l2c.overall_hits::cpu1.inst 432364 # number of overall hits +system.l2c.overall_hits::cpu1.data 244641 # number of overall hits +system.l2c.overall_hits::total 1356633 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4243 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5343 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 4274 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5319 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6349 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4883 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20821 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1353 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1530 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2883 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 68272 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 64705 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 132977 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 6318 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4908 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20822 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1344 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1536 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2880 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 68023 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 64953 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 132976 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 4243 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73615 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 4274 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73342 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6349 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 69588 # number of demand (read+write) misses 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uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -915,39 +933,39 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52790683 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471881 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471881 # Transaction distribution +system.toL2Bus.throughput 52790764 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471959 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471959 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763424 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763424 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596450 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2909 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2909 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247508 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247508 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725145 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753790 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20211 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50526 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549672 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54754616 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83791781 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28748 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79516 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138654661 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138654661 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 169908 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808598000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 596455 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2906 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2906 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247503 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247503 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725165 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753809 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20259 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50570 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549803 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54754656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83792621 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28816 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79604 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138655697 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138655697 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 169964 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808655500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865648250 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865656500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4421117527 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4421145525 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13024000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13055000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30647250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30669250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48159799 # Throughput (bytes/s) +system.iobus.throughput 48159493 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution @@ -1057,147 +1075,189 @@ system.iobus.reqLayer25.occupancy 15532032000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42583673750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42582472500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7421376 # DTB read hits -system.cpu0.dtb.read_misses 6854 # DTB read misses -system.cpu0.dtb.write_hits 5628030 # DTB write hits -system.cpu0.dtb.write_misses 1815 # DTB write misses -system.cpu0.dtb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7421892 # DTB read hits +system.cpu0.dtb.read_misses 6825 # DTB read misses +system.cpu0.dtb.write_hits 5624028 # DTB write hits +system.cpu0.dtb.write_misses 1832 # DTB write misses +system.cpu0.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 666 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6418 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 6408 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 151 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7428230 # DTB read accesses -system.cpu0.dtb.write_accesses 5629845 # DTB write accesses +system.cpu0.dtb.perms_faults 218 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7428717 # DTB read accesses +system.cpu0.dtb.write_accesses 5625860 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13049406 # DTB hits -system.cpu0.dtb.misses 8669 # DTB misses -system.cpu0.dtb.accesses 13058075 # DTB accesses -system.cpu0.itb.inst_hits 30610107 # ITB inst hits -system.cpu0.itb.inst_misses 3562 # ITB inst misses +system.cpu0.dtb.hits 13045920 # DTB hits +system.cpu0.dtb.misses 8657 # DTB misses +system.cpu0.dtb.accesses 13054577 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 30611798 # ITB inst hits +system.cpu0.itb.inst_misses 3559 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 666 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2748 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2782 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30613669 # ITB inst accesses -system.cpu0.itb.hits 30610107 # DTB hits -system.cpu0.itb.misses 3562 # DTB misses -system.cpu0.itb.accesses 30613669 # DTB accesses -system.cpu0.numCycles 2628235952 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30615357 # ITB inst accesses +system.cpu0.itb.hits 30611798 # DTB hits +system.cpu0.itb.misses 3559 # DTB misses +system.cpu0.itb.accesses 30615357 # DTB accesses +system.cpu0.numCycles 2628262709 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29990580 # Number of instructions committed -system.cpu0.committedOps 38158663 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34282971 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4584 # Number of float alu accesses -system.cpu0.num_func_calls 1059870 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3968282 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34282971 # number of integer instructions -system.cpu0.num_fp_insts 4584 # number of float instructions -system.cpu0.num_int_register_reads 196555242 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36964020 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3346 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1240 # number of times the floating registers were written -system.cpu0.num_mem_refs 13622094 # number of memory refs -system.cpu0.num_load_insts 7743834 # Number of load instructions -system.cpu0.num_store_insts 5878260 # Number of store instructions -system.cpu0.num_idle_cycles 2282805163.828333 # Number of idle cycles -system.cpu0.num_busy_cycles 345430788.171666 # Number of busy cycles -system.cpu0.not_idle_fraction 0.131431 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.868569 # Percentage of idle cycles +system.cpu0.committedInsts 29989968 # Number of instructions committed +system.cpu0.committedOps 38153430 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34435324 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4807 # Number of float alu accesses +system.cpu0.num_func_calls 1060090 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3967783 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34435324 # number of integer instructions +system.cpu0.num_fp_insts 4807 # number of float instructions +system.cpu0.num_int_register_reads 199674548 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37122022 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3633 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1176 # number of times the floating registers were written +system.cpu0.num_mem_refs 13619078 # number of memory refs +system.cpu0.num_load_insts 7744657 # Number of load instructions +system.cpu0.num_store_insts 5874421 # Number of store instructions +system.cpu0.num_idle_cycles 2288628005.429596 # Number of idle cycles +system.cpu0.num_busy_cycles 339634703.570404 # Number of busy cycles +system.cpu0.not_idle_fraction 0.129224 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.870776 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 856230 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.853093 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60649685 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 510.852804 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60649877 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 856742 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.791072 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 20173406250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 217.243034 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 293.610060 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.424303 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.573457 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997760 # Average percentage of cache occupancy +system.cpu0.icache.tags.avg_refs 70.791297 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 20177865250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 217.225698 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 293.627106 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.424269 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.573490 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997759 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62363171 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62363171 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 30192721 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30456964 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60649685 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30192721 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30456964 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60649685 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30192721 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30456964 # number of overall hits -system.cpu0.icache.overall_hits::total 60649685 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 417386 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 439357 # number of ReadReq misses +system.cpu0.icache.tags.tag_accesses 62363363 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62363363 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 30194610 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30455267 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60649877 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30194610 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30455267 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60649877 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 30194610 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30455267 # number of overall hits +system.cpu0.icache.overall_hits::total 60649877 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 417188 # number of ReadReq misses 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StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123208 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124411 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123361 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247772 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11823140 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11970437 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23793577 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11823140 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11970437 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23793577 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027230 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027178 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027204 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024775 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024203 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048296 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045152 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046732 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026167 # miss rate for demand accesses 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# average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27778.092379 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27010.562985 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 27393.462931 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1377,77 +1437,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596450 # number of writebacks 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+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2357134500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2382546250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4739680750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5582137379 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5356296355 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10938433734 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68828500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68170750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136999250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7939271879 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7738842605 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15678114484 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7939271879 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7738842605 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15678114484 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91425467750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90647011250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182072479000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13263386492 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12973041499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26236427991 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104688854242 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103620052749 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208308906991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027224 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027185 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027205 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024735 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024243 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024489 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048147 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.045313 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046736 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026147 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025930 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.026037 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026167 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026147 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025930 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026037 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12929.815885 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12762.909276 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12845.432194 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44044.222537 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43181.702661 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43618.712915 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11484.125665 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12261.324825 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11857.522239 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12916.725575 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12766.148261 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12840.591872 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44100.375887 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43254.890577 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43682.270741 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11490.567613 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12195.125224 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11830.677893 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25688.032870 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24926.939632 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25306.628752 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25688.032870 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24926.939632 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25306.628752 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1458,70 +1518,112 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7578699 # DTB read hits -system.cpu1.dtb.read_misses 7251 # DTB read misses -system.cpu1.dtb.write_hits 5604812 # DTB write hits -system.cpu1.dtb.write_misses 1846 # DTB write misses -system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7578222 # DTB read hits +system.cpu1.dtb.read_misses 7256 # DTB read misses +system.cpu1.dtb.write_hits 5608824 # DTB write hits +system.cpu1.dtb.write_misses 1858 # DTB write misses +system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 773 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6708 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6698 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7585950 # DTB read accesses -system.cpu1.dtb.write_accesses 5606658 # DTB write accesses +system.cpu1.dtb.perms_faults 234 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7585478 # DTB read accesses +system.cpu1.dtb.write_accesses 5610682 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13183511 # DTB hits -system.cpu1.dtb.misses 9097 # DTB misses -system.cpu1.dtb.accesses 13192608 # DTB accesses -system.cpu1.itb.inst_hits 30896338 # ITB inst hits -system.cpu1.itb.inst_misses 3789 # ITB inst misses +system.cpu1.dtb.hits 13187046 # DTB hits +system.cpu1.dtb.misses 9114 # DTB misses +system.cpu1.dtb.accesses 13196160 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 30894839 # ITB inst hits +system.cpu1.itb.inst_misses 3806 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 773 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2857 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2929 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30900127 # ITB inst accesses -system.cpu1.itb.hits 30896338 # DTB hits -system.cpu1.itb.misses 3789 # DTB misses -system.cpu1.itb.accesses 30900127 # DTB accesses -system.cpu1.numCycles 2631198481 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30898645 # ITB inst accesses +system.cpu1.itb.hits 30894839 # DTB hits +system.cpu1.itb.misses 3806 # DTB misses +system.cpu1.itb.accesses 30898645 # DTB accesses +system.cpu1.numCycles 2631205114 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30221754 # Number of instructions committed -system.cpu1.committedOps 38460770 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34602143 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5685 # Number of float alu accesses -system.cpu1.num_func_calls 1080538 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3981203 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34602143 # number of integer instructions -system.cpu1.num_fp_insts 5685 # number of float instructions -system.cpu1.num_int_register_reads 198301383 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37233535 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4147 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1540 # number of times the floating registers were written -system.cpu1.num_mem_refs 13778426 # number of memory refs -system.cpu1.num_load_insts 7920474 # Number of load instructions -system.cpu1.num_store_insts 5857952 # Number of store instructions -system.cpu1.num_idle_cycles 2292395060.642381 # Number of idle cycles -system.cpu1.num_busy_cycles 338803420.357619 # Number of busy cycles -system.cpu1.not_idle_fraction 0.128764 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.871236 # Percentage of idle cycles +system.cpu1.committedInsts 30222584 # Number of instructions committed +system.cpu1.committedOps 38466237 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34785148 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5462 # Number of float alu accesses +system.cpu1.num_func_calls 1080322 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3981720 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34785148 # number of integer instructions +system.cpu1.num_fp_insts 5462 # number of float instructions +system.cpu1.num_int_register_reads 201769035 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37410979 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3860 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1604 # number of times the floating registers were written +system.cpu1.num_mem_refs 13781482 # number of memory refs +system.cpu1.num_load_insts 7919681 # Number of load instructions +system.cpu1.num_store_insts 5861801 # Number of store instructions +system.cpu1.num_idle_cycles 2292298207.924829 # Number of idle cycles +system.cpu1.num_busy_cycles 338906906.075172 # Number of busy cycles +system.cpu1.not_idle_fraction 0.128803 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.871197 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1540,10 +1642,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1557221573750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1557221573750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557253805500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1557253805500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557253805500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1557253805500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |