diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-04-22 13:20:33 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-04-22 13:20:33 -0400 |
| commit | d69f904a18593f75efcb0555b2bd092574181160 (patch) | |
| tree | 0afd4c3ec943f0166c70bf7b62215f404465da2f /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing | |
| parent | 33ab8f735d0979ef68d7202d3adbf28f1ae2aceb (diff) | |
| download | gem5-d69f904a18593f75efcb0555b2bd092574181160.tar.xz | |
stats: Update stats for O3 switching fix.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini | 12 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt | 638 |
2 files changed, 327 insertions, 323 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index 8baae834f..0095c8976 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename=False @@ -19,14 +19,16 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 +panic_on_oops=true +panic_on_panic=true readfile=tests/halt.sh symbolfile= work_begin_ckpt_count=0 @@ -65,7 +67,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -91,6 +93,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu0.tracer @@ -214,6 +217,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=true system=system tracer=system.cpu1.tracer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 26ec1de8f..a80cc588c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,16 +1,28 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.610012 # Number of seconds simulated -sim_ticks 2610011893000 # Number of ticks simulated -final_tick 2610011893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2610011895000 # Number of ticks simulated +final_tick 2610011895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167893 # Simulator instruction rate (inst/s) -host_op_rate 213643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7278548305 # Simulator tick rate (ticks/s) -host_mem_usage 438276 # Number of bytes of host memory used -host_seconds 358.59 # Real time elapsed on the host +host_inst_rate 531747 # Simulator instruction rate (inst/s) +host_op_rate 676644 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23052454652 # Simulator tick rate (ticks/s) +host_mem_usage 397728 # Number of bytes of host memory used +host_seconds 113.22 # Real time elapsed on the host sim_insts 60204721 # Number of instructions simulated sim_ops 76610045 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory @@ -105,7 +117,7 @@ system.physmem.perBankWrReqs::14 50585 # Tr system.physmem.perBankWrReqs::15 51197 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2610007485000 # Total gap between requests +system.physmem.totGap 2610007487000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6679 # Categorize read packet sizes @@ -122,11 +134,11 @@ system.physmem.writePktSize::5 0 # Ca system.physmem.writePktSize::6 57385 # Categorize write packet sizes system.physmem.rdQLenPdf::0 1116599 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 960481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 974946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3652365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 974945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3652366 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2754414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2758655 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2734327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2758656 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2734326 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 61705 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 60367 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 111551 # What read queue length does an incoming req see @@ -184,14 +196,14 @@ system.physmem.wrQLenPdf::28 1 # Wh system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 338127152500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 432998718750 # Sum of mem lat for all requests +system.physmem.totQLat 338127200750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 432998808250 # Sum of mem lat for all requests system.physmem.totBusLat 77470020000 # Total cycles spent in databus access -system.physmem.totBankLat 17401546250 # Total cycles spent in bank access +system.physmem.totBankLat 17401587500 # Total cycles spent in bank access system.physmem.avgQLat 21823.10 # Average queueing delay per request -system.physmem.avgBankLat 1123.11 # Average bank access latency per request +system.physmem.avgBankLat 1123.12 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27946.21 # Average memory access latency +system.physmem.avgMemAccLat 27946.22 # Average memory access latency system.physmem.avgRdBW 379.93 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.90 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s @@ -205,31 +217,19 @@ system.physmem.writeRowHits 794097 # Nu system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.86 # Row buffer hit rate for writes system.physmem.avgGap 160069.31 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 61815 # number of replacements -system.l2c.tagsinuse 50922.556622 # Cycle average of tags in use +system.l2c.tagsinuse 50922.556971 # Cycle average of tags in use system.l2c.total_refs 1697645 # Total number of references to valid blocks. system.l2c.sampled_refs 127200 # Sample count of references to valid blocks. system.l2c.avg_refs 13.346266 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2558113997500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37911.407506 # Average occupied blocks per requestor +system.l2c.warmup_cycle 2558113998500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 37911.407860 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000184 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000643 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3494.638708 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3026.772490 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3494.638706 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3026.772488 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.inst 3500.625095 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2989.111997 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2989.111995 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.578482 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -240,12 +240,12 @@ system.l2c.occ_percent::cpu1.data 0.045610 # Av system.l2c.occ_percent::total 0.777017 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 10043 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3654 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 407564 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 186717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 407563 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 186718 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 9399 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 3346 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 436383 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 183761 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 436384 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 183760 # number of ReadReq hits system.l2c.ReadReq_hits::total 1240867 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 596298 # number of Writeback hits system.l2c.Writeback_hits::total 596298 # number of Writeback hits @@ -257,21 +257,21 @@ system.l2c.ReadExReq_hits::cpu1.data 58743 # nu system.l2c.ReadExReq_hits::total 114544 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 10043 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3654 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 407564 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 242518 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 407563 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 242519 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 9399 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 3346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 436383 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 242504 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 436384 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 242503 # number of demand (read+write) hits system.l2c.demand_hits::total 1355411 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 10043 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3654 # number of overall hits -system.l2c.overall_hits::cpu0.inst 407564 # number of overall hits -system.l2c.overall_hits::cpu0.data 242518 # number of overall hits +system.l2c.overall_hits::cpu0.inst 407563 # number of overall hits +system.l2c.overall_hits::cpu0.data 242519 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 9399 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 3346 # number of overall hits -system.l2c.overall_hits::cpu1.inst 436383 # number of overall hits -system.l2c.overall_hits::cpu1.data 242504 # number of overall hits +system.l2c.overall_hits::cpu1.inst 436384 # number of overall hits +system.l2c.overall_hits::cpu1.data 242503 # number of overall hits system.l2c.overall_hits::total 1355411 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses @@ -303,38 +303,38 @@ system.l2c.overall_misses::total 153560 # nu system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.inst 276276000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 281472500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 285306500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 251488000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1094694500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 281450000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 285328500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 251478000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1094684000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 249000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 205000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 454000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3062671000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3034678000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6097349000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3062643000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3034803500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6097446500 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 276276000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3344143500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 285306500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3286166000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7192043500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3344093000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 285328500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3286281500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 7192130500 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 276276000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3344143500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 285306500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3286166000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7192043500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3344093000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 285328500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3286281500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 7192130500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 10044 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 3656 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 412728 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 192005 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 412727 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 192006 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 9399 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 3346 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 441819 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 188322 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 441820 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 188321 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1261319 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 596298 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 596298 # number of Writeback accesses(hits+misses) @@ -346,21 +346,21 @@ system.l2c.ReadExReq_accesses::cpu1.data 125087 # nu system.l2c.ReadExReq_accesses::total 247652 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 10044 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 3656 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 412728 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 314570 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 412727 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 314571 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 9399 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 3346 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 441819 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 313409 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 441820 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 313408 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1508971 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 10044 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 3656 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 412728 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 314570 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 412727 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 314571 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 9399 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 3346 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 441819 # 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miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 41250 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53500.387297 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 53228.536309 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52484.639441 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 55138.785354 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 53525.058674 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 53224.281392 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52488.686534 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 55136.592852 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 53524.545277 # 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average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 46412.917060 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52484.639441 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 46346.040477 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 46835.396588 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 46412.216177 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52488.686534 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 46347.669417 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 46835.963141 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -455,46 +455,46 @@ system.l2c.overall_mshr_misses::cpu1.data 70905 # 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number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4517984886 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 4642435980 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 9160420866 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 4642436480 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9160421366 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209116116 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 88156392171 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 87704881505 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 176070389792 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 88156496171 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 87704707505 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 176070319792 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000100 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000547 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.012512 # mshr miss rate for ReadReq accesses @@ -511,44 +511,44 @@ system.l2c.ReadExReq_mshr_miss_rate::total 0.537480 # system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000100 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000547 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.012512 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.229049 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.229048 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012304 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.226238 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.226239 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.101765 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000100 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000547 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.012512 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.229049 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.229048 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012304 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.226238 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.226239 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.101765 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40958.833075 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40767.074130 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 39941.167403 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42647.842798 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 41014.983962 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40958.639427 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40762.913767 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 39945.214496 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42645.869546 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 41014.495013 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10028.778332 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # 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average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40958.833075 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33836.715664 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39941.167403 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33764.860094 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 34259.219816 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40958.639427 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33836.052948 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39945.214496 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33766.513716 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34259.809163 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -573,7 +573,7 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7403432 # DTB read hits +system.cpu0.dtb.read_hits 7403435 # DTB read hits system.cpu0.dtb.read_misses 6873 # DTB read misses system.cpu0.dtb.write_hits 5501198 # DTB write hits system.cpu0.dtb.write_misses 1842 # DTB write misses @@ -586,12 +586,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 225 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7410305 # DTB read accesses +system.cpu0.dtb.read_accesses 7410308 # DTB read accesses system.cpu0.dtb.write_accesses 5503040 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12904630 # DTB hits +system.cpu0.dtb.hits 12904633 # DTB hits system.cpu0.dtb.misses 8715 # DTB misses -system.cpu0.dtb.accesses 12913345 # DTB accesses +system.cpu0.dtb.accesses 12913348 # DTB accesses system.cpu0.itb.inst_hits 30303054 # ITB inst hits system.cpu0.itb.inst_misses 3598 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -613,26 +613,26 @@ system.cpu0.itb.inst_accesses 30306652 # IT system.cpu0.itb.hits 30303054 # DTB hits system.cpu0.itb.misses 3598 # DTB misses system.cpu0.itb.accesses 30306652 # DTB accesses -system.cpu0.numCycles 2668343003 # number of cpu cycles simulated +system.cpu0.numCycles 2668342955 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29632665 # Number of instructions committed -system.cpu0.committedOps 37682858 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33888275 # Number of integer alu accesses +system.cpu0.committedInsts 29632666 # Number of instructions committed +system.cpu0.committedOps 37682860 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33888276 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5192 # Number of float alu accesses system.cpu0.num_func_calls 1024744 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 3926833 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33888275 # number of integer instructions +system.cpu0.num_int_insts 33888276 # number of integer instructions system.cpu0.num_fp_insts 5192 # number of float instructions -system.cpu0.num_int_register_reads 194247306 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36521980 # number of times the integer registers were written +system.cpu0.num_int_register_reads 194247325 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36521977 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3842 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1352 # number of times the floating registers were written -system.cpu0.num_mem_refs 13487420 # number of memory refs -system.cpu0.num_load_insts 7732200 # Number of load instructions +system.cpu0.num_mem_refs 13487423 # number of memory refs +system.cpu0.num_load_insts 7732203 # Number of load instructions system.cpu0.num_store_insts 5755220 # Number of store instructions -system.cpu0.num_idle_cycles -6063478274.849866 # Number of idle cycles -system.cpu0.num_busy_cycles 8731821277.849865 # Number of busy cycles +system.cpu0.num_idle_cycles -6063478143.749568 # Number of idle cycles +system.cpu0.num_busy_cycles 8731821098.749567 # Number of busy cycles system.cpu0.not_idle_fraction 3.272376 # Percentage of non-idle cycles system.cpu0.idle_fraction -2.272376 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -643,38 +643,38 @@ system.cpu0.icache.total_refs 60642600 # To system.cpu0.icache.sampled_refs 856185 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 70.828851 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 18907162000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 150.590705 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 360.381607 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 150.590700 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 360.381612 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.294122 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::cpu1.inst 0.703870 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.997993 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29889508 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30753092 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu0.inst 29889509 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30753091 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60642600 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29889508 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30753092 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu0.inst 29889509 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30753091 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 60642600 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29889508 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30753092 # number of overall hits +system.cpu0.icache.overall_hits::cpu0.inst 29889509 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30753091 # number of overall hits system.cpu0.icache.overall_hits::total 60642600 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 413546 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 442639 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu0.inst 413545 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 442640 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 856185 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 413546 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 442639 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 413545 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 442640 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 856185 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 413546 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 442639 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 413545 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 442640 # number of overall misses system.cpu0.icache.overall_misses::total 856185 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5610148500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5995583000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11605731500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5610148500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 5995583000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11605731500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5610148500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 5995583000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11605731500 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5610135500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5995618000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11605753500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5610135500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 5995618000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11605753500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5610135500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 5995618000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11605753500 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 30303054 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu1.inst 31195731 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 61498785 # number of ReadReq accesses(hits+misses) @@ -693,15 +693,15 @@ system.cpu0.icache.demand_miss_rate::total 0.013922 # system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013647 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014189 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013922 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13565.960014 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13545.085273 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13555.167984 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13565.960014 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13545.085273 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13555.167984 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13565.960014 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13545.085273 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13555.167984 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13565.961383 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13545.133743 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13555.193679 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13565.961383 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13545.133743 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13555.193679 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13565.961383 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13545.133743 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13555.193679 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -710,24 +710,24 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 413546 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 442639 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 413545 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 442640 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 856185 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 413546 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 442639 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 413545 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 442640 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 856185 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 413546 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 442639 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 413545 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 442640 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 856185 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4783056500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5110305000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9893361500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4783056500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5110305000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9893361500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4783056500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5110305000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9893361500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4783045500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5110338000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9893383500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4783045500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5110338000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9893383500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4783045500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5110338000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9893383500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 298856500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 298856500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 298856500 # number of overall MSHR uncacheable cycles @@ -741,15 +741,15 @@ system.cpu0.icache.demand_mshr_miss_rate::total 0.013922 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013647 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014189 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013922 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11565.960014 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11545.085273 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11555.167984 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11565.960014 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11545.085273 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11555.167984 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11565.960014 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11545.085273 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11555.167984 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11565.961383 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11545.133743 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11555.193679 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11565.961383 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11545.133743 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11555.193679 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11565.961383 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11545.133743 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11555.193679 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency @@ -761,13 +761,13 @@ system.cpu0.dcache.total_refs 23658362 # To system.cpu0.dcache.sampled_refs 627978 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 37.673871 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 140.437193 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 371.475629 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu0.data 140.437195 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 371.475626 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.274291 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::cpu1.data 0.725538 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999830 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6510444 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6686709 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 6510445 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6686708 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 13197153 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 4886816 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 5087431 # number of WriteReq hits @@ -778,14 +778,14 @@ system.cpu0.dcache.LoadLockedReq_hits::total 236322 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 112519 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu1.data 135213 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247732 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11397260 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 11774140 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 11397261 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 11774139 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 23171400 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11397260 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 11774140 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 11397261 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 11774139 # number of overall hits system.cpu0.dcache.overall_hits::total 23171400 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 186238 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 182678 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 186239 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 182677 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 368916 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 123980 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu1.data 126580 # number of WriteReq misses @@ -793,29 +793,29 @@ system.cpu0.dcache.WriteReq_misses::total 250560 # n system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5767 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5644 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 11411 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 310218 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 309258 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 310219 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 309257 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 619476 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 310218 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 309258 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 310219 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 309257 # number of overall misses system.cpu0.dcache.overall_misses::total 619476 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2656146500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2591895000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5248041500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4024715000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4035571500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8060286500 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2656137500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2591872000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5248009500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4024689000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4035697500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8060386500 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 80055500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 75055500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 155111000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 6680861500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 6627466500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 13308328000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 6680861500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 6627466500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 13308328000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6696682 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6869387 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 6680826500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 6627569500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 13308396000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 6680826500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 6627569500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 13308396000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6696684 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6869385 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 13566069 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5010796 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 5214011 # number of WriteReq accesses(hits+misses) @@ -826,13 +826,13 @@ system.cpu0.dcache.LoadLockedReq_accesses::total 247733 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 112519 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 135213 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247732 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11707478 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12083398 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 11707480 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12083396 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 23790876 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11707478 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12083398 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11707480 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12083396 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 23790876 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027810 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027811 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026593 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.027194 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024743 # miss rate for WriteReq accesses @@ -841,27 +841,27 @@ system.cpu0.dcache.WriteReq_miss_rate::total 0.024505 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051254 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.041741 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046062 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026497 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026498 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025594 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.026038 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026497 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026498 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025594 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.026038 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14262.108163 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14188.325907 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14225.573030 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 32462.614938 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 31881.588719 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 32169.087245 # average WriteReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14261.983258 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14188.277670 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14225.486290 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 32462.405227 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 31882.584137 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 32169.486351 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13881.654240 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13298.281361 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13593.111910 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21536.021443 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21430.218458 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21483.201932 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21536.021443 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21430.218458 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21483.201932 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21535.839197 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21430.620811 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 21483.311702 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21535.839197 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21430.620811 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21483.311702 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -872,8 +872,8 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 596298 # number of writebacks system.cpu0.dcache.writebacks::total 596298 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186238 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 182678 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186239 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 182677 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 368916 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 123980 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 126580 # number of WriteReq MSHR misses @@ -881,41 +881,41 @@ system.cpu0.dcache.WriteReq_mshr_misses::total 250560 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5767 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5644 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11411 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 310218 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 309258 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 310219 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 309257 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 619476 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 310218 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 309258 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 310219 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 309257 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 619476 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2283670500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2226539000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4510209500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3776755000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3782411500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7559166500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2283659500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2226518000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4510177500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3776729000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3782537500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7559266500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68521500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63767500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 132289000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6060425500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6008950500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12069376000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6060425500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6008950500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12069376000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91364051500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90730862500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182094914000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9290730000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9409303500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6060388500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6009055500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12069444000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6060388500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6009055500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12069444000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91364168500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90730673500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182094842000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9290730500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9409303000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18700033500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100654781500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 100140166000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200794947500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027810 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100654899000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 100139976500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200794875500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027811 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027194 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024743 # mshr miss rate for WriteReq accesses @@ -924,27 +924,27 @@ system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051254 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041741 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046062 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026497 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026498 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025594 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.026038 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026497 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026498 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025594 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026038 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12262.108163 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12188.325907 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12225.573030 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30462.614938 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29881.588719 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30169.087245 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12261.983258 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12188.277670 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12225.486290 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30462.405227 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29882.584137 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30169.486351 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11881.654240 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11298.281361 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11593.111910 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19536.021443 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19430.218458 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19483.201932 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19536.021443 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19430.218458 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19483.201932 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19535.839197 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19430.620811 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19483.311702 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19535.839197 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19430.620811 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19483.311702 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -961,7 +961,7 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7594464 # DTB read hits +system.cpu1.dtb.read_hits 7594461 # DTB read hits system.cpu1.dtb.read_misses 6935 # DTB read misses system.cpu1.dtb.write_hits 5731015 # DTB write hits system.cpu1.dtb.write_misses 1760 # DTB write misses @@ -974,12 +974,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 227 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7601399 # DTB read accesses +system.cpu1.dtb.read_accesses 7601396 # DTB read accesses system.cpu1.dtb.write_accesses 5732775 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13325479 # DTB hits +system.cpu1.dtb.hits 13325476 # DTB hits system.cpu1.dtb.misses 8695 # DTB misses -system.cpu1.dtb.accesses 13334174 # DTB accesses +system.cpu1.dtb.accesses 13334171 # DTB accesses system.cpu1.itb.inst_hits 31195731 # ITB inst hits system.cpu1.itb.inst_misses 3619 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits @@ -1001,26 +1001,26 @@ system.cpu1.itb.inst_accesses 31199350 # IT system.cpu1.itb.hits 31195731 # DTB hits system.cpu1.itb.misses 3619 # DTB misses system.cpu1.itb.accesses 31199350 # DTB accesses -system.cpu1.numCycles 2551680783 # number of cpu cycles simulated +system.cpu1.numCycles 2551680835 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30572056 # Number of instructions committed -system.cpu1.committedOps 38927187 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34988620 # Number of integer alu accesses +system.cpu1.committedInsts 30572055 # Number of instructions committed +system.cpu1.committedOps 38927185 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34988619 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5077 # Number of float alu accesses system.cpu1.num_func_calls 1115365 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 4021820 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34988620 # number of integer instructions +system.cpu1.num_int_insts 34988619 # number of integer instructions system.cpu1.num_fp_insts 5077 # number of float instructions -system.cpu1.num_int_register_reads 200559310 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37663253 # number of times the integer registers were written +system.cpu1.num_int_register_reads 200559291 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37663256 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3651 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1428 # number of times the floating registers were written -system.cpu1.num_mem_refs 13910244 # number of memory refs -system.cpu1.num_load_insts 7929876 # Number of load instructions +system.cpu1.num_mem_refs 13910241 # number of memory refs +system.cpu1.num_load_insts 7929873 # Number of load instructions system.cpu1.num_store_insts 5980368 # Number of store instructions -system.cpu1.num_idle_cycles 10585260111.377636 # Number of idle cycles -system.cpu1.num_busy_cycles -8033579328.377636 # Number of busy cycles +system.cpu1.num_idle_cycles 10585260303.338047 # Number of idle cycles +system.cpu1.num_busy_cycles -8033579468.338046 # Number of busy cycles system.cpu1.not_idle_fraction -3.148348 # Percentage of non-idle cycles system.cpu1.idle_fraction 4.148348 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -1039,10 +1039,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1195947260006 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1195947260006 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1195947260006 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1195947260006 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1195947261004 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1195947261004 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1195947261004 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1195947261004 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |