diff options
| author | Steve Reinhardt <stever@gmail.com> | 2015-03-19 08:41:32 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2015-03-19 08:41:32 -0400 |
| commit | 1483496803f8a8618f62adc5439ce435359b36fe (patch) | |
| tree | a6134ff85d7e6e07e6d34293513f91b16ff94515 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | |
| parent | f1c3fda965dd4b28ab6b2e99f5f3210fa2089a17 (diff) | |
| download | gem5-1483496803f8a8618f62adc5439ce435359b36fe.tar.xz | |
stats: update Minor stats due to PF bug fix
A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5)
inadvertently fixed a bug in the Minor CPU model which caused it to treat
software prefetches as regular loads. Prior to this changeset, Minor
did an ad-hoc generation of memory commands that left out the PF check;
because it now uses the common code that the other CPU models use,
it generates prefetches properly. These stat changes reflect the fact
that the Minor model now issues SoftPFReqs.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 4902 |
1 files changed, 2463 insertions, 2439 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index f6bd584fc..ec3592c1e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.357291 # Number of seconds simulated -sim_ticks 47357290872500 # Number of ticks simulated -final_tick 47357290872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.397611 # Number of seconds simulated +sim_ticks 47397610926500 # Number of ticks simulated +final_tick 47397610926500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179609 # Simulator instruction rate (inst/s) -host_op_rate 211253 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9509351214 # Simulator tick rate (ticks/s) -host_mem_usage 764316 # Number of bytes of host memory used -host_seconds 4980.08 # Real time elapsed on the host -sim_insts 894465242 # Number of instructions simulated -sim_ops 1052057457 # Number of ops (including micro ops) simulated +host_inst_rate 110253 # Simulator instruction rate (inst/s) +host_op_rate 129665 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5829907242 # Simulator tick rate (ticks/s) +host_mem_usage 703216 # Number of bytes of host memory used +host_seconds 8130.08 # Real time elapsed on the host +sim_insts 896366789 # Number of instructions simulated +sim_ops 1054186264 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 141696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 131328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 8696576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13989464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 21378112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 133248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 113344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3297088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 7559072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 13082368 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 433472 # Number of bytes read from this memory -system.physmem.bytes_read::total 68955768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 8696576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3297088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11993664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79042240 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 107072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 78336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7782464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 12802520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15762560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 159744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 154688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3994240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12481056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 14503040 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 448448 # Number of bytes read from this memory +system.physmem.bytes_read::total 68274168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7782464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3994240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11776704 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79542656 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 79063056 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2214 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2052 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 135884 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 218607 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 334033 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 51517 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 118125 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 204412 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6773 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1077470 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1235035 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 79563472 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1673 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1224 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 121601 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 200061 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 246290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2496 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2417 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 62410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 195031 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 226610 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7007 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1066820 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1242854 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1237638 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 183638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 295403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 451422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 69622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 159618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 276248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9153 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1456075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 183638 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 69622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 253259 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1669062 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1245457 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 164195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 270109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 332560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 84271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 263327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 305987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1440456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 164195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 84271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1678200 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1669501 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1669062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2992 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 183638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 295842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 451422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 69622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 159618 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 276248 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3125576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1077470 # Number of read requests accepted -system.physmem.writeReqs 1907210 # Number of write requests accepted -system.physmem.readBursts 1077470 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1907210 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 68937984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20096 # Total number of bytes read from write queue -system.physmem.bytesWritten 118940800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 68955768 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 121915664 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 314 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 48739 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 118611 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 58565 # Per bank write bursts -system.physmem.perBankRdBursts::1 71236 # Per bank write bursts -system.physmem.perBankRdBursts::2 60619 # Per bank write bursts -system.physmem.perBankRdBursts::3 68763 # Per bank write bursts -system.physmem.perBankRdBursts::4 63623 # Per bank write bursts -system.physmem.perBankRdBursts::5 74242 # Per bank write bursts -system.physmem.perBankRdBursts::6 69161 # Per bank write bursts -system.physmem.perBankRdBursts::7 67695 # Per bank write bursts -system.physmem.perBankRdBursts::8 61029 # Per bank write bursts -system.physmem.perBankRdBursts::9 112215 # Per bank write bursts -system.physmem.perBankRdBursts::10 55292 # Per bank write bursts -system.physmem.perBankRdBursts::11 71140 # Per bank write bursts -system.physmem.perBankRdBursts::12 63760 # Per bank write bursts -system.physmem.perBankRdBursts::13 63951 # Per bank write bursts -system.physmem.perBankRdBursts::14 57537 # Per bank write bursts -system.physmem.perBankRdBursts::15 58328 # Per bank write bursts -system.physmem.perBankWrBursts::0 113661 # Per bank write bursts -system.physmem.perBankWrBursts::1 123588 # Per bank write bursts -system.physmem.perBankWrBursts::2 119813 # Per bank write bursts -system.physmem.perBankWrBursts::3 126847 # Per bank write bursts -system.physmem.perBankWrBursts::4 114977 # Per bank write bursts -system.physmem.perBankWrBursts::5 123724 # Per bank write bursts -system.physmem.perBankWrBursts::6 117451 # Per bank write bursts -system.physmem.perBankWrBursts::7 117840 # Per bank write bursts -system.physmem.perBankWrBursts::8 112656 # Per bank write bursts -system.physmem.perBankWrBursts::9 114020 # Per bank write bursts -system.physmem.perBankWrBursts::10 109420 # Per bank write bursts -system.physmem.perBankWrBursts::11 118853 # Per bank write bursts -system.physmem.perBankWrBursts::12 108855 # Per bank write bursts -system.physmem.perBankWrBursts::13 111956 # Per bank write bursts -system.physmem.perBankWrBursts::14 111151 # Per bank write bursts -system.physmem.perBankWrBursts::15 113638 # Per bank write bursts +system.physmem.bw_write::total 1678639 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1678200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 164195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 270548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 332560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 84271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 263327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 305987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3119095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1066820 # Number of read requests accepted +system.physmem.writeReqs 1912174 # Number of write requests accepted +system.physmem.readBursts 1066820 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1912174 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 68253568 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22912 # Total number of bytes read from write queue +system.physmem.bytesWritten 119234048 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 68274168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 122233360 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 358 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49121 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 113360 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 61922 # Per bank write bursts +system.physmem.perBankRdBursts::1 70972 # Per bank write bursts +system.physmem.perBankRdBursts::2 57667 # Per bank write bursts +system.physmem.perBankRdBursts::3 64982 # Per bank write bursts +system.physmem.perBankRdBursts::4 65050 # Per bank write bursts +system.physmem.perBankRdBursts::5 70572 # Per bank write bursts +system.physmem.perBankRdBursts::6 72322 # Per bank write bursts +system.physmem.perBankRdBursts::7 67337 # Per bank write bursts +system.physmem.perBankRdBursts::8 57787 # Per bank write bursts +system.physmem.perBankRdBursts::9 110760 # Per bank write bursts +system.physmem.perBankRdBursts::10 57283 # Per bank write bursts +system.physmem.perBankRdBursts::11 63297 # Per bank write bursts +system.physmem.perBankRdBursts::12 60054 # Per bank write bursts +system.physmem.perBankRdBursts::13 63124 # Per bank write bursts +system.physmem.perBankRdBursts::14 62259 # Per bank write bursts +system.physmem.perBankRdBursts::15 61074 # Per bank write bursts +system.physmem.perBankWrBursts::0 110998 # Per bank write bursts +system.physmem.perBankWrBursts::1 120192 # Per bank write bursts +system.physmem.perBankWrBursts::2 114368 # Per bank write bursts +system.physmem.perBankWrBursts::3 118573 # Per bank write bursts +system.physmem.perBankWrBursts::4 116138 # Per bank write bursts +system.physmem.perBankWrBursts::5 119482 # Per bank write bursts +system.physmem.perBankWrBursts::6 124701 # Per bank write bursts +system.physmem.perBankWrBursts::7 122822 # Per bank write bursts +system.physmem.perBankWrBursts::8 112747 # Per bank write bursts +system.physmem.perBankWrBursts::9 113706 # Per bank write bursts +system.physmem.perBankWrBursts::10 111725 # Per bank write bursts +system.physmem.perBankWrBursts::11 114999 # Per bank write bursts +system.physmem.perBankWrBursts::12 115986 # Per bank write bursts +system.physmem.perBankWrBursts::13 114347 # Per bank write bursts +system.physmem.perBankWrBursts::14 116931 # Per bank write bursts +system.physmem.perBankWrBursts::15 115317 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 260 # Number of times write queue was full causing retry -system.physmem.totGap 47357288950000 # Total gap between requests +system.physmem.numWrRetry 309 # Number of times write queue was full causing retry +system.physmem.totGap 47397609004000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1077428 # Read request sizes (log2) +system.physmem.readPktSize::6 1066778 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1904607 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 705573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 108235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 42943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 38392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 34676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26708 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 22131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 7359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1909571 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 706521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 49462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 37446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 32271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 29670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 27253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24519 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 21077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 5735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 743 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,169 +188,169 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 64765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 92305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 104587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 111564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 110175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 106822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 101643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 99926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 96867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 96399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 113990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 101913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 97920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 113164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 100658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 96398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 90928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 7132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 4155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 4227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 781 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1066280 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 176.199272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 107.583604 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 245.477591 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 681708 63.93% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 204893 19.22% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51569 4.84% 87.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24658 2.31% 90.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19159 1.80% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12349 1.16% 93.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8689 0.81% 94.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7706 0.72% 94.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 55549 5.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1066280 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 82344 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 13.080819 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 137.450182 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 82341 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 44683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 64606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 92963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 104605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 112793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 111359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 106848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 102432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 100351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 96443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 96232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 115397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 102859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 98750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 113669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 102100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 95328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 90958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 770 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1060336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 176.818458 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 107.808098 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 246.499626 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 676218 63.77% 63.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 204682 19.30% 83.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51639 4.87% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24739 2.33% 90.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18449 1.74% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11998 1.13% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8607 0.81% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7827 0.74% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 56177 5.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1060336 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 82745 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.888404 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 137.186201 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 82742 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 82344 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 82344 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.569343 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.983627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.346474 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 74619 90.62% 90.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 3701 4.49% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 1617 1.96% 97.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 776 0.94% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 389 0.47% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 290 0.35% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 467 0.57% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 184 0.22% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 57 0.07% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 20 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 62 0.08% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 36 0.04% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 12 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 4 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 2 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 5 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 3 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 10 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 13 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 9 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 24 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 82745 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 82745 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.515342 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.971264 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.554947 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 75024 90.67% 90.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 3669 4.43% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 1611 1.95% 97.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 792 0.96% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 419 0.51% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 279 0.34% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 435 0.53% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 203 0.25% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 68 0.08% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 22 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 73 0.09% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 36 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 10 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 7 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 4 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 7 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 9 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 7 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 11 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 22 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 7 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::592-607 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 82344 # Writes before turning the bus around for reads -system.physmem.totQLat 41096385470 # Total ticks spent queuing -system.physmem.totMemAccLat 61293060470 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5385780000 # Total ticks spent in databus transfers -system.physmem.avgQLat 38152.68 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::720-735 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 82745 # Writes before turning the bus around for reads +system.physmem.totQLat 40375015102 # Total ticks spent queuing +system.physmem.totMemAccLat 60371177602 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5332310000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37858.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 56902.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.51 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.46 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 56608.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.52 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.47 # Average write queue length when enqueuing -system.physmem.readRowHits 809420 # Number of row buffer hits during reads -system.physmem.writeRowHits 1059902 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.03 # Row buffer hit rate for writes -system.physmem.avgGap 15866789.39 # Average gap between requests -system.physmem.pageHitRate 63.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4185760320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2283897000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4164435600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6207198480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1197399382470 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27364022846250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31671411386760 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.775859 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45522011263316 # Time in different power states -system.physmem_0.memoryStateTime::REF 1581363940000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.99 # Average write queue length when enqueuing +system.physmem.readRowHits 803348 # Number of row buffer hits during reads +system.physmem.writeRowHits 1065807 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.21 # Row buffer hit rate for writes +system.physmem.avgGap 15910609.09 # Average gap between requests +system.physmem.pageHitRate 63.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4142388600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2260231875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4140419400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6138335520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3095781190320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1201204741230 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27384875125500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31698542432445 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.779401 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45556660870724 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582710220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 253913912184 # Time in different power states +system.physmem_0.memoryStateTime::ACT 258234748026 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3875316480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2114508000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4237256400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5835557520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1190113153695 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27370414275000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31669737933735 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.740522 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45532636458203 # Time in different power states -system.physmem_1.memoryStateTime::REF 1581363940000 # Time in different power states +system.physmem_1.actEnergy 3873751560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2113654125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4177906200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5934111840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3095781190320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1188231262785 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27396255369750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31696367246580 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.733509 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45575630122499 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582710220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 243288251797 # Time in different power states +system.physmem_1.memoryStateTime::ACT 239268979001 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -384,15 +384,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 151571686 # Number of BP lookups -system.cpu0.branchPred.condPredicted 107212809 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6769997 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 114323741 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 82790418 # Number of BTB hits +system.cpu0.branchPred.lookups 133516333 # Number of BP lookups +system.cpu0.branchPred.condPredicted 94941201 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6028887 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 100948341 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 73074204 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.417520 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17895403 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1177591 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.387722 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15498997 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1074405 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -423,61 +423,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 310912 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 310912 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11841 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90150 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 310912 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 310912 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 310912 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 101991 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 19193.830760 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17232.192163 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15084.416179 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 100737 98.77% 98.77% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1058 1.04% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 37 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 76 0.07% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 58 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 274493 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 274493 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8574 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74935 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 274493 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 274493 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 274493 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 83509 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 18665.041972 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 16952.057368 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 12810.377808 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 82824 99.18% 99.18% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 578 0.69% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 32 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 36 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 27 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 101991 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 83509 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 90150 88.39% 88.39% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11841 11.61% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 101991 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 310912 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 74935 89.73% 89.73% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8574 10.27% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 83509 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 274493 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 310912 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101991 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 274493 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 83509 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101991 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 412903 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 83509 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 358002 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 98035121 # DTB read hits -system.cpu0.dtb.read_misses 261233 # DTB read misses -system.cpu0.dtb.write_hits 86222704 # DTB write hits -system.cpu0.dtb.write_misses 49679 # DTB write misses +system.cpu0.dtb.read_hits 84777209 # DTB read hits +system.cpu0.dtb.read_misses 227212 # DTB read misses +system.cpu0.dtb.write_hits 75760151 # DTB write hits +system.cpu0.dtb.write_misses 47281 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 42277 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2349 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 10561 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 33980 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2153 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9225 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 12531 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 98296354 # DTB read accesses -system.cpu0.dtb.write_accesses 86272383 # DTB write accesses +system.cpu0.dtb.perms_faults 11068 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 85004421 # DTB read accesses +system.cpu0.dtb.write_accesses 75807432 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 184257825 # DTB hits -system.cpu0.dtb.misses 310912 # DTB misses -system.cpu0.dtb.accesses 184568737 # DTB accesses +system.cpu0.dtb.hits 160537360 # DTB hits +system.cpu0.dtb.misses 274493 # DTB misses +system.cpu0.dtb.accesses 160811853 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,185 +507,192 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 67664 # Table walker walks requested -system.cpu0.itb.walker.walksLong 67664 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 693 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59407 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 67664 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 67664 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 67664 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 60100 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 21688.993677 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 19128.313408 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17789.670668 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 55182 91.82% 91.82% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3533 5.88% 97.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 493 0.82% 98.52% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 740 1.23% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.03% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 25 0.04% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 48 0.08% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 24 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 15 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 60100 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 61212 # Table walker walks requested +system.cpu0.itb.walker.walksLong 61212 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 587 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52411 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 61212 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 61212 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 61212 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 52998 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 21062.649289 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 19099.820516 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 14417.313367 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 48615 91.73% 91.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3682 6.95% 98.68% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 228 0.43% 99.11% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 379 0.72% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 22 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 7 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 9 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 52998 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 59407 98.85% 98.85% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 693 1.15% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 60100 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 52411 98.89% 98.89% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 587 1.11% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 52998 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 67664 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 67664 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61212 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61212 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60100 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60100 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 127764 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 272362835 # ITB inst hits -system.cpu0.itb.inst_misses 67664 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52998 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52998 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 114210 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 238748421 # ITB inst hits +system.cpu0.itb.inst_misses 61212 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 29878 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24001 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 206888 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 196095 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 272430499 # ITB inst accesses -system.cpu0.itb.hits 272362835 # DTB hits -system.cpu0.itb.misses 67664 # DTB misses -system.cpu0.itb.accesses 272430499 # DTB accesses -system.cpu0.numCycles 1079786982 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 238809633 # ITB inst accesses +system.cpu0.itb.hits 238748421 # DTB hits +system.cpu0.itb.misses 61212 # DTB misses +system.cpu0.itb.accesses 238809633 # DTB accesses +system.cpu0.numCycles 949769690 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 504924574 # Number of instructions committed -system.cpu0.committedOps 592395738 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 49310302 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4906 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93635655345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.138511 # CPI: cycles per instruction -system.cpu0.ipc 0.467615 # IPC: instructions per cycle +system.cpu0.committedInsts 439719858 # Number of instructions committed +system.cpu0.committedOps 516807751 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 45409758 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 3855 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93846100118 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.159943 # CPI: cycles per instruction +system.cpu0.ipc 0.462975 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13863 # number of quiesce instructions executed -system.cpu0.tickCycles 807512344 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 272274638 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 6269899 # number of replacements -system.cpu0.dcache.tags.tagsinuse 502.388707 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 174903450 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6270410 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.893463 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 12790 # number of quiesce instructions executed +system.cpu0.tickCycles 712933683 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 236836007 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5519291 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.702778 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 152151321 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5519802 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.564634 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 5096417500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.388707 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981228 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.981228 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.702778 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938873 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.938873 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 207 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 371740852 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 371740852 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 90280740 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 90280740 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80064017 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80064017 # number of WriteReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 281235 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 281235 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1931472 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1931472 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1872190 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1872190 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 170344757 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 170344757 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 170344757 # number of overall hits -system.cpu0.dcache.overall_hits::total 170344757 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 4509015 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 4509015 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2541213 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2541213 # number of WriteReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 864871 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 864871 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 140737 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 140737 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 198480 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 198480 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 7050228 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 7050228 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 7050228 # number of overall misses -system.cpu0.dcache.overall_misses::total 7050228 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 66986292890 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 66986292890 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 47882988891 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 47882988891 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 35264024894 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 35264024894 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2028925085 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2028925085 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4179395855 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4179395855 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2760500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2760500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 114869281781 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 114869281781 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 114869281781 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 114869281781 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 94789755 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 94789755 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 82605230 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 82605230 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1146106 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1146106 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2072209 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2072209 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2070670 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2070670 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 177394985 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 177394985 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 177394985 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 177394985 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.047569 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.047569 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030763 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030763 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.754617 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.754617 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.067916 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.067916 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095853 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095853 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.039743 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.039743 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039743 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.039743 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.081182 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.081182 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18842.571989 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18842.571989 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40773.739545 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 40773.739545 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14416.429830 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14416.429830 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21057.012571 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21057.012571 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 323933952 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 323933952 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 77613049 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77613049 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 70091195 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 70091195 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268191 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 268191 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 249696 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 249696 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1731388 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1731388 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1698549 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1698549 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 147704244 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 147704244 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 147972435 # number of overall hits +system.cpu0.dcache.overall_hits::total 147972435 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3327173 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3327173 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2386267 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2386267 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 673594 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 673594 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 788040 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 788040 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148951 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 148951 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 180566 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 180566 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5713440 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5713440 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6387034 # number of overall misses +system.cpu0.dcache.overall_misses::total 6387034 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 50124059800 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 50124059800 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 46218650240 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 46218650240 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 32570768827 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32570768827 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2177391616 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2177391616 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3839424984 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3839424984 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3590500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3590500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 96342710040 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 96342710040 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 96342710040 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 96342710040 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 80940222 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 80940222 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 72477462 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 72477462 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 941785 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 941785 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1037736 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1037736 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1880339 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1880339 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1879115 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1879115 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 153417684 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 153417684 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 154359469 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 154359469 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041107 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.041107 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032924 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.032924 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.715231 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.715231 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.759384 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.759384 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079215 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079215 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.096091 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.096091 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037241 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.037241 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041378 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.041378 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15065.059677 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15065.059677 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19368.599675 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19368.599675 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41331.364940 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41331.364940 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14618.173869 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14618.173869 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21263.277605 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21263.277605 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16292.988224 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16292.988224 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16292.988224 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16292.988224 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16862.469903 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16862.469903 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15084.107904 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15084.107904 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -694,88 +701,96 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4374601 # number of writebacks -system.cpu0.dcache.writebacks::total 4374601 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 429861 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 429861 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1046667 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1046667 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 81 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 81 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 33 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 33 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 55 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 55 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1476528 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1476528 # 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number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 33958968357 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1816137650 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1816137650 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3868892109 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3868892109 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2341500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 80025073061 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 80025073061 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 80025073061 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 80025073061 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5766564749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5766564749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5473208250 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5473208250 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11239772999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11239772999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043034 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043034 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018093 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018093 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.754546 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.754546 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.067900 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.067900 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095826 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095826 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031420 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.031420 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031420 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031420 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13198.751645 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13198.751645 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17520.593206 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17520.593206 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39268.456339 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39268.456339 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12907.505472 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12907.505472 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19498.007353 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19498.007353 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3800112 # number of writebacks +system.cpu0.dcache.writebacks::total 3800112 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 429398 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 429398 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1005493 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1005493 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 83 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 83 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41403 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41403 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 51 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 51 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1434891 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1434891 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1434891 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1434891 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2897775 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2897775 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1380774 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1380774 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 667964 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 667964 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 787957 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 787957 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 107548 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 107548 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 180515 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 180515 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4278549 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4278549 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4946513 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4946513 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37570974686 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37570974686 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 24854865946 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 24854865946 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14971801156 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14971801156 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31379224673 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 31379224673 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1379388880 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1379388880 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3557992992 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3557992992 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2840500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2840500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 62425840632 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 62425840632 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 77397641788 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 77397641788 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5923264746 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5923264746 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5701581250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5701581250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11624845996 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11624845996 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035801 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035801 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019051 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019051 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.709253 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.709253 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759304 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.759304 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057196 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057196 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.096064 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.096064 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027888 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027888 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032045 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032045 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12965.456147 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12965.456147 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18000.676393 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18000.676393 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22414.083927 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22414.083927 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39823.524219 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39823.524219 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12825.797597 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12825.797597 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19710.234562 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19710.234562 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14357.621160 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14357.621160 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14357.621160 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14357.621160 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14590.423209 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14590.423209 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15646.909608 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15646.909608 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -783,57 +798,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 10307657 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.930132 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 261841431 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 10308169 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 25.401352 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 23262861250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930132 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 9444901 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.930140 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 229100961 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9445413 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.255261 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 24039613250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930140 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 249 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 554607398 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 554607398 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 261841431 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 261841431 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 261841431 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 261841431 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 261841431 # number of overall hits -system.cpu0.icache.overall_hits::total 261841431 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 10308179 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 10308179 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 10308179 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 10308179 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 10308179 # number of overall misses -system.cpu0.icache.overall_misses::total 10308179 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 103403812050 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 103403812050 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 103403812050 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 103403812050 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 103403812050 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 103403812050 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 272149610 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 272149610 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 272149610 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 272149610 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 272149610 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 272149610 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037877 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.037877 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037877 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.037877 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037877 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.037877 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10031.239470 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10031.239470 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10031.239470 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10031.239470 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10031.239470 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10031.239470 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 486538188 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 486538188 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 229100961 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 229100961 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 229100961 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 229100961 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 229100961 # number of overall hits +system.cpu0.icache.overall_hits::total 229100961 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9445422 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9445422 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9445422 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9445422 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9445422 # number of overall misses +system.cpu0.icache.overall_misses::total 9445422 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93680049293 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 93680049293 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 93680049293 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 93680049293 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 93680049293 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 93680049293 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 238546383 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 238546383 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 238546383 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 238546383 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 238546383 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 238546383 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039596 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.039596 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039596 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.039596 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039596 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.039596 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9918.037468 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9918.037468 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9918.037468 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9918.037468 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9918.037468 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9918.037468 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -842,238 +858,241 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10308179 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 10308179 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 10308179 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 10308179 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 10308179 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 10308179 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 93061406416 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 93061406416 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 93061406416 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 93061406416 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 93061406416 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 93061406416 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9445422 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9445422 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9445422 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9445422 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9445422 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9445422 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 84206359153 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 84206359153 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 84206359153 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 84206359153 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 84206359153 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 84206359153 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037877 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.037877 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.037877 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9027.919133 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9027.919133 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9027.919133 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039596 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039596 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039596 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.039596 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039596 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.039596 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8915.044680 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8915.044680 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8915.044680 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8915.044680 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8915.044680 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8915.044680 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 12908052 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 12916183 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7100 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7452732 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7456615 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 3365 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1498641 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 3094586 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16261.036528 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 17187399 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3110668 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.525308 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 953257 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2717195 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16004.441587 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 15093815 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2732791 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.523223 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 5822698500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6030.877634 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.708580 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 75.789449 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5140.303922 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2691.250303 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 2256.106640 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.368096 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004072 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004626 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.313739 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.164261 # 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Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 978 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3981 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4660 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3950 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.138428 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006287 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.836853 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 360310183 # 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average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34931.503009 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.184057 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26709.503385 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25473.948849 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 52502.734204 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43489.607650 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43489.607650 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20266.143903 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20266.143903 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.483112 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.483112 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1165000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1165000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39938.078665 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39938.078665 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29497.482424 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27348.089069 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29497.482424 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34037.079428 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1229,66 +1252,67 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 17791242 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 15586246 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31969 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31969 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 4374599 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1496771 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1185210 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 863337 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 459789 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 354172 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 478714 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1428335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1300035 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20720970 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18253192 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 368054 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1214499 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 40556715 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 663070976 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 695774006 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1328184 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4426744 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1364599910 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5020747 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 27005623 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.173372 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.378569 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 16517621 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14068332 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 33225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3800110 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1086057 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1148168 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 786224 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 477409 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 332434 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 482483 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1303516 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1171227 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18995457 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16182353 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 335795 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1061304 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 36574909 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 607854592 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 610383865 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1223600 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3866424 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1223328481 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4849156 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 24579773 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.184734 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.388082 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 22323591 82.66% 82.66% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 4682032 17.34% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 20039056 81.53% 81.53% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 4540717 18.47% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 27005623 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 16474086937 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 24579773 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14682015163 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 218344490 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 205334987 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 15570026567 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14272912820 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9017811583 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7968080178 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 202360718 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 183071466 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 661550198 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 578323929 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 120391711 # Number of BP lookups -system.cpu1.branchPred.condPredicted 86208358 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5520869 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 91435615 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 66348303 # Number of BTB hits +system.cpu1.branchPred.lookups 139172899 # Number of BP lookups +system.cpu1.branchPred.condPredicted 99233401 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6252869 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 105205307 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 76618629 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.562866 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 13861535 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 936317 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.827722 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16237430 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1026400 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1318,67 +1342,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 259478 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 259478 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8847 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78200 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 259478 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 259478 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 259478 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 87047 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 19103.472745 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17330.859199 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14131.069495 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 82878 95.21% 95.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3197 3.67% 98.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 459 0.53% 99.41% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 357 0.41% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 35 0.04% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 16 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 26 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 18 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 28 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 18 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 87047 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 492358444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 492358444 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 492358444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 78200 89.84% 89.84% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8847 10.16% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 87047 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259478 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 295412 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 295412 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11437 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91734 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 295412 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 295412 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 295412 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 103171 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19450.829041 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17494.566732 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15964.350233 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 101752 98.62% 98.62% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1198 1.16% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 37 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 80 0.08% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 73 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 103171 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1267166444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1267166444 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1267166444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 91734 88.91% 88.91% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11437 11.09% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 103171 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 295412 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259478 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87047 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 295412 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103171 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87047 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 346525 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103171 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 398583 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 76628852 # DTB read hits -system.cpu1.dtb.read_misses 212787 # DTB read misses -system.cpu1.dtb.write_hits 67332330 # DTB write hits -system.cpu1.dtb.write_misses 46691 # DTB write misses +system.cpu1.dtb.read_hits 90130445 # DTB read hits +system.cpu1.dtb.read_misses 246227 # DTB read misses +system.cpu1.dtb.write_hits 78064785 # DTB write hits +system.cpu1.dtb.write_misses 49185 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 32755 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 660 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6687 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 41873 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 864 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7939 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10091 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 76841639 # DTB read accesses -system.cpu1.dtb.write_accesses 67379021 # DTB write accesses +system.cpu1.dtb.perms_faults 11435 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 90376672 # DTB read accesses +system.cpu1.dtb.write_accesses 78113970 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 143961182 # DTB hits -system.cpu1.dtb.misses 259478 # DTB misses -system.cpu1.dtb.accesses 144220660 # DTB accesses +system.cpu1.dtb.hits 168195230 # DTB hits +system.cpu1.dtb.misses 295412 # DTB misses +system.cpu1.dtb.accesses 168490642 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1408,178 +1427,187 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 59975 # Table walker walks requested -system.cpu1.itb.walker.walksLong 59975 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 467 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50555 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 59975 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 59975 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 59975 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 51022 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 21947.479421 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 19426.626910 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 17730.380785 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 49865 97.73% 97.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1035 2.03% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.09% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 47 0.09% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 12 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 68039 # Table walker walks requested +system.cpu1.itb.walker.walksLong 68039 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 556 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57997 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 68039 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 68039 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 68039 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 58553 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 22020.763957 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19263.180418 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18942.782929 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 56928 97.22% 97.22% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1459 2.49% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 45 0.08% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 89 0.15% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 13 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 51022 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 491673944 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 491673944 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 491673944 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 50555 99.08% 99.08% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 467 0.92% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 51022 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 58553 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1266435944 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1266435944 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1266435944 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 57997 99.05% 99.05% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 556 0.95% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 58553 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59975 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59975 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68039 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68039 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51022 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51022 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 110997 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 214508261 # ITB inst hits -system.cpu1.itb.inst_misses 59975 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58553 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58553 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 126592 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 249268487 # ITB inst hits +system.cpu1.itb.inst_misses 68039 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 23598 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 30522 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 213038 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 226060 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 214568236 # ITB inst accesses -system.cpu1.itb.hits 214508261 # DTB hits -system.cpu1.itb.misses 59975 # DTB misses -system.cpu1.itb.accesses 214568236 # DTB accesses -system.cpu1.numCycles 819770260 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 249336526 # ITB inst accesses +system.cpu1.itb.hits 249268487 # DTB hits +system.cpu1.itb.misses 68039 # DTB misses +system.cpu1.itb.accesses 249336526 # DTB accesses +system.cpu1.numCycles 932637373 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 389540668 # Number of instructions committed -system.cpu1.committedOps 459661719 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 43651844 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5040 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93895466763 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.104454 # CPI: cycles per instruction -system.cpu1.ipc 0.475183 # IPC: instructions per cycle +system.cpu1.committedInsts 456646931 # Number of instructions committed +system.cpu1.committedOps 537378513 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 48077866 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5781 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93863478723 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.042360 # CPI: cycles per instruction +system.cpu1.ipc 0.489630 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5089 # number of quiesce instructions executed -system.cpu1.tickCycles 643812229 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 175958031 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 4705434 # number of replacements -system.cpu1.dcache.tags.tagsinuse 416.508572 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 136862260 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4705946 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.082837 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8379321114000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.508572 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.813493 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.813493 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 5811 # number of quiesce instructions executed +system.cpu1.tickCycles 738281563 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 194355810 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5504177 # number of replacements +system.cpu1.dcache.tags.tagsinuse 462.121005 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 159889231 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5504689 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.046006 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8380046591500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 462.121005 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.902580 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.902580 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 290353323 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 290353323 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 70292866 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 70292866 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 62721831 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 62721831 # number of WriteReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 37138 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 37138 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1710890 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1710890 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1626994 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1626994 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 133014697 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 133014697 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 133014697 # number of overall hits -system.cpu1.dcache.overall_hits::total 133014697 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3624776 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3624776 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2086736 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2086736 # number of WriteReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 382666 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 382666 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 105529 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 105529 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 188259 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 188259 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5711512 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5711512 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5711512 # number of overall misses -system.cpu1.dcache.overall_misses::total 5711512 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 50593739173 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 50593739173 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 36769582633 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 36769582633 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 10366896775 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 10366896775 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 1534806603 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 1534806603 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3974138991 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3974138991 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3324999 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3324999 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 87363321806 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 87363321806 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 87363321806 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 87363321806 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 73917642 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 73917642 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 64808567 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 64808567 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 419804 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 419804 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1816419 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1816419 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1815253 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1815253 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 138726209 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 138726209 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 138726209 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 138726209 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049038 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049038 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032198 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.032198 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.911535 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.911535 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.058097 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.058097 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103710 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103710 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041171 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.041171 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041171 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.041171 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13957.756058 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13957.756058 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17620.620257 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17620.620257 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27091.240860 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27091.240860 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14543.932028 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14543.932028 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21109.954855 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21109.954855 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 339217340 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 339217340 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 82545716 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 82545716 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 72881068 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 72881068 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 234096 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 234096 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 75438 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 75438 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1844359 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1844359 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1835233 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1835233 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 155426784 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 155426784 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 155660880 # number of overall hits +system.cpu1.dcache.overall_hits::total 155660880 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3601145 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3601145 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2300638 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2300638 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 662253 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 662253 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 453115 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 453115 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 186074 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 186074 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193760 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 193760 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5901783 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5901783 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6564036 # number of overall misses +system.cpu1.dcache.overall_misses::total 6564036 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55051091271 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 55051091271 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 39953352540 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 39953352540 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12827340347 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12827340347 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2834422928 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2834422928 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4003287927 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4003287927 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3321500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3321500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 95004443811 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 95004443811 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 95004443811 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 95004443811 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 86146861 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 86146861 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 75181706 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 75181706 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 896349 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 896349 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 528553 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 528553 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2030433 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2030433 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2028993 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2028993 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 161328567 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 161328567 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 162224916 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 162224916 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041802 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.041802 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030601 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030601 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.738834 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.738834 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.857274 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.857274 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091643 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091643 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095496 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095496 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036582 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.036582 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040463 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.040463 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15287.107648 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15287.107648 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17366.205609 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17366.205609 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28309.237935 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 28309.237935 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15232.772596 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15232.772596 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20661.064859 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20661.064859 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15296.005997 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15296.005997 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16097.583359 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16097.583359 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14473.480007 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14473.480007 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1588,88 +1616,96 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3043303 # number of writebacks -system.cpu1.dcache.writebacks::total 3043303 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 326021 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 326021 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 860988 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 860988 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 76 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 76 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 32 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 32 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 53 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1187009 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1187009 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1187009 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1187009 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3298755 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3298755 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1225748 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1225748 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 382590 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 382590 # 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number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20156955784 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9784547475 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 9784547475 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1375359879 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1375359879 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3682414982 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3682414982 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2828501 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2828501 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60785857868 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 60785857868 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60785857868 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 60785857868 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 684362251 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 684362251 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 814922500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 814922500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1499284751 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1499284751 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044627 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044627 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018913 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018913 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.911354 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.911354 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058080 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058080 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103680 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103680 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032615 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032615 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12316.435165 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12316.435165 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16444.616499 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16444.616499 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25574.498745 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25574.498745 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13036.957250 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13036.957250 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19565.874531 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19565.874531 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3506045 # number of writebacks +system.cpu1.dcache.writebacks::total 3506045 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 409825 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 409825 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 940543 # 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number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3191320 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3191320 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1360095 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1360095 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 661949 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 661949 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 453043 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 453043 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 140893 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 140893 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193713 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 193713 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4551415 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4551415 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5213364 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5213364 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42631813644 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42631813644 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22019784779 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22019784779 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13605448576 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13605448576 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12141090903 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12141090903 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1806083972 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1806083972 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3702335044 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3702335044 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2795500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2795500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 64651598423 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 64651598423 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 78257046999 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 78257046999 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 498907500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 498907500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 556628501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 556628501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1055536001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1055536001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037045 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037045 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.738495 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.738495 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.857138 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.857138 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069391 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069391 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095472 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095472 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028212 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028212 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032137 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032137 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13358.677176 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13358.677176 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16189.887309 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16189.887309 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20553.620560 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20553.620560 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26798.981340 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26798.981340 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12818.833952 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12818.833952 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19112.475900 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19112.475900 # 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average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1677,58 +1713,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 8513181 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.039853 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 205775695 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8513693 # 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Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 205775695 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 205775695 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 205775695 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 205775695 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 205775695 # number of overall hits -system.cpu1.icache.overall_hits::total 205775695 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8513694 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8513694 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8513694 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8513694 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8513694 # number of overall misses -system.cpu1.icache.overall_misses::total 8513694 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 84159322077 # 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average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9967.902763 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9967.902763 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9967.902763 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9967.902763 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1737,241 +1773,236 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8513694 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8513694 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8513694 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8513694 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8513694 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 8513694 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 75624287377 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 75624287377 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 75624287377 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 75624287377 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 75624287377 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 75624287377 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8552000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8552000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8552000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8552000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039730 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.039730 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.039730 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8882.664491 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8882.664491 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8882.664491 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9393087 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 9393087 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 9393087 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 9393087 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 9393087 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 9393087 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 84210400586 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 84210400586 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 84210400586 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 84210400586 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 84210400586 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 84210400586 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8117000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8117000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8117000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8117000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037718 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037718 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037718 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.037718 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037718 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.037718 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8965.146451 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8965.146451 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8965.146451 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8965.146451 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8965.146451 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8965.146451 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 10121407 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 10125724 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 3757 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7598599 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7600232 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 1400 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 1112844 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2221085 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13329.151476 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 13836589 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2237248 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.184647 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10494820402000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5280.158493 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 74.775550 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 82.006725 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3962.886937 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2390.470426 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1538.853345 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.322275 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004564 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005005 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.241875 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.145903 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.093924 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.813547 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2457 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13645 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 113 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 719 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 972 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 645 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 937 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4967 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4448 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3191 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.149963 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832825 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 282497183 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 282497183 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 472812 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141552 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 7799132 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2711848 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 11125344 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3043302 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3043302 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 157363 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 157363 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 71855 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 71855 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 32392 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 32392 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 766594 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 766594 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 472812 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141552 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 7799132 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3478442 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 11891938 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 472812 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141552 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 7799132 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3478442 # number of overall hits -system.cpu1.l2cache.overall_hits::total 11891938 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12653 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8998 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 714562 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 692201 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1428414 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 224018 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 224018 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 142871 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 142871 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 155808 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 155808 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 245850 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 245850 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12653 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8998 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 714562 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 938051 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1674264 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12653 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8998 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 714562 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 938051 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1674264 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 449558190 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 345348999 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 20635717509 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 20877681975 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 42308306673 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 229084267 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 229084267 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3047787464 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 3047787464 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3209370896 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3209370896 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2764497 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2764497 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9785037151 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 9785037151 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 449558190 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 345348999 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20635717509 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 30662719126 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 52093343824 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 449558190 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 345348999 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20635717509 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 30662719126 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 52093343824 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 485465 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150550 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 8513694 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3404049 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 12553758 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3043303 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3043303 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 381381 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 381381 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 214726 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 214726 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 188200 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 188200 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1012444 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1012444 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 485465 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150550 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 8513694 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4416493 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 13566202 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 485465 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150550 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 8513694 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4416493 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 13566202 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026064 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059768 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.083931 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.203346 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.113784 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.587386 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.587386 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.665364 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.665364 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.827885 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.827885 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 976472 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2525133 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 202 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 684 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 569 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 22 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 26 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1158 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2664 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5264 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5426 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.089722 # 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mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.665364 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.665364 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827885 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.827885 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.582696 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.582696 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.656981 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.656981 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784553 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.784553 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.236903 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.236903 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.210659 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.122848 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.210659 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207555 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207555 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.249486 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138603 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.249486 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191906 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 23524.613506 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23038.594142 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36143.355229 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30445.827572 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30445.827572 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19406.762982 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19406.762982 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14569.405435 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14569.405435 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 393582.833333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 393582.833333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31760.741811 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31760.741811 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24293.872687 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28557.983969 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186252 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26660.088082 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25037.672304 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46384.470766 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32812.266011 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32812.266011 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19486.318153 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19486.318153 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14796.710109 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14796.710109 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33792.425824 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33792.425824 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27982.771658 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26022.436146 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27982.771658 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31231.631271 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2131,63 +2158,63 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 15445485 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 12769085 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6630 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6630 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3043303 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1203167 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105360 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 381381 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 459466 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 345603 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 466676 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1177489 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1018273 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17027569 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13630896 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 329758 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1060916 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 32049139 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 544882176 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 508019480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1204400 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3883720 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1057989776 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5539420 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 22773399 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.231012 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.421480 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 16687989 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 14334572 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 4962 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4962 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3506045 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1053826 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1133141 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 451918 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 452249 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 341136 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 469204 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1304040 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1151075 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18786353 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15676887 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371904 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1206650 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 36041794 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 601163264 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 587975003 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349240 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4407712 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1194895219 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5002181 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 24473447 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.192626 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.394362 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 17512462 76.90% 76.90% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 5260937 23.10% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 19759234 80.74% 80.74% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 4714213 19.26% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 22773399 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 12190933688 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 24473447 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 13845201909 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 175938985 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 163397980 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 12781364350 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 14102728136 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7076644304 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8209870082 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 179556153 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 203661942 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 575808723 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 656138927 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40350 # Transaction distribution -system.iobus.trans_dist::ReadResp 40350 # Transaction distribution -system.iobus.trans_dist::WriteReq 136657 # Transaction distribution -system.iobus.trans_dist::WriteResp 29929 # Transaction distribution +system.iobus.trans_dist::ReadReq 40316 # Transaction distribution +system.iobus.trans_dist::ReadResp 40316 # Transaction distribution +system.iobus.trans_dist::WriteReq 136601 # Transaction distribution +system.iobus.trans_dist::WriteResp 29873 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47838 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47648 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2202,13 +2229,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122720 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231214 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231214 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122530 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231224 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231224 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354014 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47858 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47668 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2223,13 +2250,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155850 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338872 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155660 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496658 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36180000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2257,71 +2284,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 607629108 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607453407 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92794000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92660000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148521376 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148582123 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115588 # number of replacements -system.iocache.tags.tagsinuse 11.296723 # Cycle average of tags in use +system.iocache.tags.replacements 115592 # number of replacements +system.iocache.tags.tagsinuse 11.295153 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115604 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9128912382000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.841062 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.455661 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240066 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465979 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706045 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9129697263000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.412327 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.882827 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463270 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.242677 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705947 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040820 # Number of tag accesses -system.iocache.tags.data_accesses 1040820 # Number of data accesses +system.iocache.tags.tag_accesses 1040865 # Number of tag accesses +system.iocache.tags.data_accesses 1040865 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8879 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8916 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8884 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8921 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8879 # number of demand (read+write) misses -system.iocache.demand_misses::total 8919 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8884 # number of demand (read+write) misses +system.iocache.demand_misses::total 8924 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8879 # number of overall misses -system.iocache.overall_misses::total 8919 # number of overall misses +system.iocache.overall_misses::realview.ide 8884 # number of overall misses +system.iocache.overall_misses::total 8924 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1619625499 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1624820999 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1659251745 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1664447245 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19871885233 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19871885233 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19947928539 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19947928539 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1619625499 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1625189999 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1659251745 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1664816245 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1619625499 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1625189999 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1659251745 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1664816245 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8879 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8916 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8884 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8921 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8879 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8919 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8884 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8924 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8879 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8919 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8884 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8924 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2336,54 +2363,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182410.800653 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182236.540938 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186768.544012 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186576.308149 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186191.863738 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 186191.863738 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186904.360046 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186904.360046 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 182410.800653 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 182216.616100 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 186768.544012 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 186554.935567 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 182410.800653 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 182216.616100 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 110413 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 186768.544012 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 186554.935567 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 112960 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16202 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16486 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.814776 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.851874 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106678 # number of writebacks +system.iocache.writebacks::total 106678 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8879 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8916 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8884 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8921 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8879 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8919 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8884 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8924 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8879 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8919 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8884 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8924 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1156744203 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1160014703 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1196099891 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1199370391 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14321981281 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14321981281 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14397972639 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14397972639 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1156744203 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1160227703 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1196099891 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1199583391 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1156744203 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1160227703 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1196099891 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1199583391 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2398,563 +2425,560 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130278.657844 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 130104.834343 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134635.287145 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 134443.491873 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134191.414446 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134191.414446 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134903.424022 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134903.424022 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 130278.657844 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 130084.953806 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 134635.287145 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 134422.163940 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 130278.657844 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 130084.953806 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 134635.287145 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 134422.163940 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1509391 # number of replacements -system.l2c.tags.tagsinuse 64395.788312 # Cycle average of tags in use -system.l2c.tags.total_refs 5071928 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1569787 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.230966 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8741120000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 18420.928371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 254.564671 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 327.558520 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5783.699822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9967.407270 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17191.318601 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 126.325801 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 133.881896 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2759.726372 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3037.353013 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6393.023977 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.281081 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003884 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004998 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.088252 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.152091 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.262319 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001928 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002043 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042110 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.046346 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.097550 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.982602 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 14050 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 200 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 46146 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 182 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1105 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 12755 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::0 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1911 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4647 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 39226 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.214386 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.704132 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 65830537 # Number of tag accesses -system.l2c.tags.data_accesses 65830537 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 7044 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4822 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 775995 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 424099 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 575063 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6552 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4575 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 662903 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 363815 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 472407 # number of ReadReq hits -system.l2c.ReadReq_hits::total 3297275 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2504876 # number of Writeback hits -system.l2c.Writeback_hits::total 2504876 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 140601 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 125515 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 266116 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 34998 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 27403 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 62401 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 7236 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5610 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12846 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55428 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53807 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109235 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 7044 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4822 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 775995 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 479527 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 575063 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6552 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4575 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 662903 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 417622 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 472407 # number of demand (read+write) hits -system.l2c.demand_hits::total 3406510 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 7044 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4822 # number of overall hits -system.l2c.overall_hits::cpu0.inst 775995 # number of overall hits -system.l2c.overall_hits::cpu0.data 479527 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 575063 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6552 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4575 # number of overall hits -system.l2c.overall_hits::cpu1.inst 662903 # number of overall hits -system.l2c.overall_hits::cpu1.data 417622 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 472407 # number of overall hits -system.l2c.overall_hits::total 3406510 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2214 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2052 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 83747 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 137620 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 334397 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2082 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1771 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 51652 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 69122 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 204701 # number of ReadReq misses -system.l2c.ReadReq_misses::total 889358 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 476508 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 89488 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 565996 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 48344 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 44372 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 92716 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 10817 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 7620 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 18437 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 83374 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50998 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 134372 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2214 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2052 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 83747 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 220994 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 334397 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2082 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1771 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 51652 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 120120 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 204701 # number of demand (read+write) misses -system.l2c.demand_misses::total 1023730 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2214 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2052 # number of overall misses -system.l2c.overall_misses::cpu0.inst 83747 # number of overall misses -system.l2c.overall_misses::cpu0.data 220994 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 334397 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2082 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1771 # number of overall misses -system.l2c.overall_misses::cpu1.inst 51652 # number of overall misses -system.l2c.overall_misses::cpu1.data 120120 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 204701 # number of overall misses -system.l2c.overall_misses::total 1023730 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 196089257 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 182667757 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 7080624634 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 12249130737 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 43332889612 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 189088032 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 162443014 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4360864205 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 6107312919 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 26397681837 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 100258792004 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 50990906 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 47594001 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 98584907 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 312691152 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 283930496 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 596621648 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 58172655 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 50436899 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 108609554 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7528015770 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4219527160 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11747542930 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 196089257 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 182667757 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 7080624634 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 19777146507 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 43332889612 # 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number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 189088032 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 162443014 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4360864205 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 10326840079 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 26397681837 # number of overall miss cycles -system.l2c.overall_miss_latency::total 112006334934 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9258 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6874 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 859742 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 561719 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 909460 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 8634 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6346 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 714555 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 432937 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 677108 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 4186633 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2504876 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2504876 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 617109 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 215003 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 832112 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 83342 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 71775 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 155117 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 18053 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 13230 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 31283 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 138802 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 104805 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 243607 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9258 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6874 # 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miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.097409 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.244998 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.367687 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.241140 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.279073 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.072286 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.159658 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.302317 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.212428 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.772162 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.416217 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.680192 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.580068 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.618210 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.597717 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.599180 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.575964 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.589362 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.600669 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.486599 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.551593 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.239145 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.298516 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.097409 # 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miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.367687 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.241140 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.279073 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.072286 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.223378 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.302317 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.231078 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88567.866757 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 89019.374756 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84547.800327 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 89006.908422 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 129585.162582 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 90820.380403 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 91723.892716 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84427.789921 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 88355.558563 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 128957.268587 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 112731.646878 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 107.009549 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 531.847857 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 174.179512 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6468.044680 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6398.866312 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6434.937314 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5377.891744 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6619.015617 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5890.847426 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90292.126682 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82739.071336 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 87425.527119 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88567.866757 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89019.374756 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 84547.800327 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 89491.780352 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 129585.162582 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90820.380403 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 91723.892716 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 84427.789921 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 85971.029629 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 128957.268587 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 109410.034808 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88567.866757 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89019.374756 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 84547.800327 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 89491.780352 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 129585.162582 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90820.380403 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 91723.892716 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 84427.789921 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 85971.029629 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 128957.268587 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 109410.034808 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 12831 # number of cycles access was blocked +system.l2c.tags.replacements 1488066 # number of replacements +system.l2c.tags.tagsinuse 64457.051863 # Cycle average of tags in use +system.l2c.tags.total_refs 5017316 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1548603 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.239898 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8811587000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 16300.231028 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.590542 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 5.410855 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3923.984358 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5628.040249 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3900.550479 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 368.152358 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 516.465158 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4442.350927 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11307.713496 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 18045.562414 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.248722 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000284 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000083 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.059875 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.085877 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.059518 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005618 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.007881 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.067785 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.172542 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.275353 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983537 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10439 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 248 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49850 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 83 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 337 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10018 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 248 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1727 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4981 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 42979 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.159286 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003784 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.760651 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 65141561 # Number of tag accesses +system.l2c.tags.data_accesses 65141561 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6849 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4798 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 687325 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 588389 # 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mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.600669 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486599 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.551593 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.239145 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.298516 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097225 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.315451 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.367687 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.241140 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.279073 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.072003 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.223330 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.302314 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.230987 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.239145 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.298516 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097225 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.315451 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.367687 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.241140 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.279073 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.072003 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.223330 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.302314 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.230987 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75965.556007 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76423.364035 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72021.954300 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76466.442328 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117289.932798 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78213.480307 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79100.500282 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71922.634500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75811.991013 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116644.590951 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 100350.980614 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33488.206062 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31928.465258 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33241.599928 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17801.475985 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17778.410326 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17790.437228 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17783.190071 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17807.754199 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17793.342409 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77798.752969 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70220.005490 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 74922.402509 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75965.556007 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76423.364035 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72021.954300 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76969.112558 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117289.932798 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78213.480307 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79100.500282 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71922.634500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73437.350500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116644.590951 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 97011.980571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75965.556007 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76423.364035 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72021.954300 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76969.112558 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117289.932798 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78213.480307 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79100.500282 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71922.634500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73437.350500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116644.590951 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 97011.980571 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9843598251 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5293500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 788726501 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13825631002 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.176050 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.190900 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.212817 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.765143 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.484776 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.678929 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.600521 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.586709 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.593738 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.596623 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.586703 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.591741 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.575848 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.512878 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.547492 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.238947 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.232334 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.231370 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.238947 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.232334 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.231370 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80848.279354 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77016.382199 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 99617.771443 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33583.928144 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32063.710201 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33250.137211 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17840.886677 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17796.886334 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17819.536552 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17860.137471 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.412203 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17840.755008 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77480.654562 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72287.514629 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75289.979524 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79571.498531 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75673.036756 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 96426.453406 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79571.498531 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75673.036756 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 96426.453406 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2969,58 +2993,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 988965 # Transaction distribution -system.membus.trans_dist::ReadResp 988965 # Transaction distribution -system.membus.trans_dist::WriteReq 38599 # Transaction distribution -system.membus.trans_dist::WriteResp 38599 # Transaction distribution -system.membus.trans_dist::Writeback 1235035 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 669572 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 669572 # Transaction distribution -system.membus.trans_dist::UpgradeReq 443245 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 300309 # Transaction distribution -system.membus.trans_dist::UpgradeResp 118634 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution -system.membus.trans_dist::ReadExReq 147271 # Transaction distribution -system.membus.trans_dist::ReadExResp 130046 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122720 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 979077 # Transaction distribution +system.membus.trans_dist::ReadResp 979077 # Transaction distribution +system.membus.trans_dist::WriteReq 38187 # Transaction distribution +system.membus.trans_dist::WriteResp 38187 # Transaction distribution +system.membus.trans_dist::Writeback 1242854 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 666717 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 666717 # Transaction distribution +system.membus.trans_dist::UpgradeReq 428866 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 287024 # Transaction distribution +system.membus.trans_dist::UpgradeResp 113399 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution +system.membus.trans_dist::ReadExReq 145453 # Transaction distribution +system.membus.trans_dist::ReadExResp 128623 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122530 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26568 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5280771 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5430111 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5765953 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5227832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5375480 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336065 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336065 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5711545 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155660 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 176778952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 176989262 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14092480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14092480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191081742 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 645066 # Total snoops (count) -system.membus.snoop_fanout::samples 3693594 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 176401096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 176608212 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14106432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14106432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190714644 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 622043 # Total snoops (count) +system.membus.snoop_fanout::samples 3659684 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3693594 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3659684 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3693594 # Request fanout histogram -system.membus.reqLayer0.occupancy 110078000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3659684 # Request fanout histogram +system.membus.reqLayer0.occupancy 109555497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22086998 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20982498 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 11288947920 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 11300972211 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6557942197 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6484776493 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151922124 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151978377 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3064,45 +3088,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 5164890 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5157651 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38599 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38599 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2504876 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 938982 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 832112 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 498168 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 313155 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 811323 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 114 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 303337 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 303337 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8953428 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6273029 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15226457 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 302864374 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 197929240 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 500793614 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1680481 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9632863 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012020 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.108976 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5072106 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5064869 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38187 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38187 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2487202 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 936242 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 829317 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 482057 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 299353 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 781410 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 127 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 300573 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 300573 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8029813 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6984147 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15013960 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 269549433 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 226408539 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 495957972 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1618057 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9487188 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012211 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.109827 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9517074 98.80% 98.80% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115789 1.20% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9371339 98.78% 98.78% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115849 1.22% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9632863 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8806822228 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9487188 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8381122122 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2518500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2527500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5125474266 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4575963989 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4045471741 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4435446795 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |