diff options
author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
---|---|---|
committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
commit | 62b6ff22ec1f90014b1d0fc778014bdb38cc09ce (patch) | |
tree | 8dc7be3b13f98b2f6d082dc7424335d9ddfe764d /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | |
parent | 71a02f624e9c406ad37a1ed7030f98a36da6e59f (diff) | |
download | gem5-62b6ff22ec1f90014b1d0fc778014bdb38cc09ce.tar.xz |
stats: update for snoop filter tweak
--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 5512 |
1 files changed, 2767 insertions, 2745 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 7463dd4c7..3e87001d4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.535940 # Number of seconds simulated -sim_ticks 47535940136000 # Number of ticks simulated -final_tick 47535940136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.355903 # Number of seconds simulated +sim_ticks 47355903328000 # Number of ticks simulated +final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 200561 # Simulator instruction rate (inst/s) -host_op_rate 235891 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10615931561 # Simulator tick rate (ticks/s) -host_mem_usage 769436 # Number of bytes of host memory used -host_seconds 4477.79 # Real time elapsed on the host -sim_insts 898069628 # Number of instructions simulated -sim_ops 1056270581 # Number of ops (including micro ops) simulated +host_inst_rate 234942 # Simulator instruction rate (inst/s) +host_op_rate 276333 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12593783431 # Simulator tick rate (ticks/s) +host_mem_usage 765460 # Number of bytes of host memory used +host_seconds 3760.26 # Real time elapsed on the host +sim_insts 883443630 # Number of instructions simulated +sim_ops 1039082168 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 89728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 8161024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 14243656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 14782784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 150400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 127744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3048640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9523856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12507584 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 413056 # Number of bytes read from this memory -system.physmem.bytes_read::total 63147416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 8161024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3048640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11209664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75703424 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14160840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 16409728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 122112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 100992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3330560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9705936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 10452736 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 444224 # Number of bytes read from this memory +system.physmem.bytes_read::total 62549528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7567040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3330560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10897600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75633728 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 75724008 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 127516 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 222570 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 230981 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2350 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1996 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 47635 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 148823 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 195431 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 986704 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1182866 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 75654312 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2056 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1934 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 118235 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 221276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 256402 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 52040 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 151668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 163324 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6941 # Number of read requests responded to by this memory +system.physmem.num_reads::total 977362 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1181777 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1185440 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1888 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 171681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 299640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 310981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 200351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 263118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8689 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1328414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 171681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64133 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 235815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1592551 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1184351 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 159791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 299030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 346519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2579 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 70330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 204957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 220727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1320839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 159791 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 70330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 230121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1597134 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1592984 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1592551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 171681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 300073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 310981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 200351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 263118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8689 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2921398 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 986704 # Number of read requests accepted -system.physmem.writeReqs 1185440 # Number of write requests accepted -system.physmem.readBursts 986704 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1185440 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 63115328 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 33728 # Total number of bytes read from write queue -system.physmem.bytesWritten 75722560 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 63147416 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 75724008 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 527 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2258 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1597569 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1597134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 159791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 299465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 346519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 70330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 204957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 220727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2918408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 977362 # Number of read requests accepted +system.physmem.writeReqs 1184351 # Number of write requests accepted +system.physmem.readBursts 977362 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1184351 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 62527296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue +system.physmem.bytesWritten 75653504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62549528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 75654312 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 63842 # Per bank write bursts -system.physmem.perBankRdBursts::1 66317 # Per bank write bursts -system.physmem.perBankRdBursts::2 58522 # Per bank write bursts -system.physmem.perBankRdBursts::3 64863 # Per bank write bursts -system.physmem.perBankRdBursts::4 59095 # Per bank write bursts -system.physmem.perBankRdBursts::5 67998 # Per bank write bursts -system.physmem.perBankRdBursts::6 58322 # Per bank write bursts -system.physmem.perBankRdBursts::7 56006 # Per bank write bursts -system.physmem.perBankRdBursts::8 52486 # Per bank write bursts -system.physmem.perBankRdBursts::9 111449 # Per bank write bursts -system.physmem.perBankRdBursts::10 50777 # Per bank write bursts -system.physmem.perBankRdBursts::11 58061 # Per bank write bursts -system.physmem.perBankRdBursts::12 51458 # Per bank write bursts -system.physmem.perBankRdBursts::13 52890 # Per bank write bursts -system.physmem.perBankRdBursts::14 54883 # Per bank write bursts -system.physmem.perBankRdBursts::15 59208 # Per bank write bursts -system.physmem.perBankWrBursts::0 77123 # Per bank write bursts -system.physmem.perBankWrBursts::1 81948 # Per bank write bursts -system.physmem.perBankWrBursts::2 74623 # Per bank write bursts -system.physmem.perBankWrBursts::3 80009 # Per bank write bursts -system.physmem.perBankWrBursts::4 75007 # Per bank write bursts -system.physmem.perBankWrBursts::5 80611 # Per bank write bursts -system.physmem.perBankWrBursts::6 72005 # Per bank write bursts -system.physmem.perBankWrBursts::7 72012 # Per bank write bursts -system.physmem.perBankWrBursts::8 68266 # Per bank write bursts -system.physmem.perBankWrBursts::9 73887 # Per bank write bursts -system.physmem.perBankWrBursts::10 67546 # Per bank write bursts -system.physmem.perBankWrBursts::11 72517 # Per bank write bursts -system.physmem.perBankWrBursts::12 68786 # Per bank write bursts -system.physmem.perBankWrBursts::13 69993 # Per bank write bursts -system.physmem.perBankWrBursts::14 72865 # Per bank write bursts -system.physmem.perBankWrBursts::15 75967 # Per bank write bursts +system.physmem.perBankRdBursts::0 54912 # Per bank write bursts +system.physmem.perBankRdBursts::1 56908 # Per bank write bursts +system.physmem.perBankRdBursts::2 51582 # Per bank write bursts +system.physmem.perBankRdBursts::3 63469 # Per bank write bursts +system.physmem.perBankRdBursts::4 61411 # Per bank write bursts +system.physmem.perBankRdBursts::5 61841 # Per bank write bursts +system.physmem.perBankRdBursts::6 57272 # Per bank write bursts +system.physmem.perBankRdBursts::7 62841 # Per bank write bursts +system.physmem.perBankRdBursts::8 51834 # Per bank write bursts +system.physmem.perBankRdBursts::9 112088 # Per bank write bursts +system.physmem.perBankRdBursts::10 55237 # Per bank write bursts +system.physmem.perBankRdBursts::11 58857 # Per bank write bursts +system.physmem.perBankRdBursts::12 56745 # Per bank write bursts +system.physmem.perBankRdBursts::13 58205 # Per bank write bursts +system.physmem.perBankRdBursts::14 53859 # Per bank write bursts +system.physmem.perBankRdBursts::15 59928 # Per bank write bursts +system.physmem.perBankWrBursts::0 69820 # Per bank write bursts +system.physmem.perBankWrBursts::1 73385 # Per bank write bursts +system.physmem.perBankWrBursts::2 70846 # Per bank write bursts +system.physmem.perBankWrBursts::3 76844 # Per bank write bursts +system.physmem.perBankWrBursts::4 76655 # Per bank write bursts +system.physmem.perBankWrBursts::5 78828 # Per bank write bursts +system.physmem.perBankWrBursts::6 72793 # Per bank write bursts +system.physmem.perBankWrBursts::7 76848 # Per bank write bursts +system.physmem.perBankWrBursts::8 69899 # Per bank write bursts +system.physmem.perBankWrBursts::9 74878 # Per bank write bursts +system.physmem.perBankWrBursts::10 69893 # Per bank write bursts +system.physmem.perBankWrBursts::11 73658 # Per bank write bursts +system.physmem.perBankWrBursts::12 73258 # Per bank write bursts +system.physmem.perBankWrBursts::13 76164 # Per bank write bursts +system.physmem.perBankWrBursts::14 72361 # Per bank write bursts +system.physmem.perBankWrBursts::15 75956 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 44 # Number of times write queue was full causing retry -system.physmem.totGap 47535938023500 # Total gap between requests +system.physmem.numWrRetry 28 # Number of times write queue was full causing retry +system.physmem.totGap 47355901307500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 986674 # Read request sizes (log2) +system.physmem.readPktSize::6 977332 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1182866 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 668450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 115815 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 26396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 23877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 21311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1181777 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 653624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 118392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 26608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 24389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 21172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 19081 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 791 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,166 +188,174 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 51637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 64761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 71932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 72504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 73761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 76926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 74288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 75236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 82718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 73770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 68266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 65794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 26534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 50320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 57992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 63163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 65860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 68534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 70437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 72935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 73131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 75636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 78760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 75174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 74381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 78953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 69890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 64098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 135 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 984595 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.009629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 96.339121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 189.114371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 670707 68.12% 68.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 190612 19.36% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44448 4.51% 91.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20648 2.10% 94.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14900 1.51% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9763 0.99% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5507 0.56% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4424 0.45% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23586 2.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 984595 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61315 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.083617 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 159.391032 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61313 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 102 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 973522 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 141.938602 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 96.538228 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 191.263762 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 662821 68.08% 68.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 188353 19.35% 87.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 43865 4.51% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 19742 2.03% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14303 1.47% 95.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9443 0.97% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6391 0.66% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5216 0.54% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23388 2.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 973522 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 57494 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.992747 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 164.605284 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 57491 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61315 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61315 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.296502 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.510563 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.190386 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 48917 79.78% 79.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 5503 8.97% 88.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 3053 4.98% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1653 2.70% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 478 0.78% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 276 0.45% 97.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 266 0.43% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 90 0.15% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 261 0.43% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 71 0.12% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 38 0.06% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 55 0.09% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 246 0.40% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 32 0.05% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 47 0.08% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 108 0.18% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 156 0.25% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 24 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 11 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 57494 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 57494 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.560163 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.793170 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.728131 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49230 85.63% 85.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2347 4.08% 89.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 805 1.40% 91.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 601 1.05% 92.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 998 1.74% 93.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 486 0.85% 94.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 329 0.57% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 263 0.46% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 216 0.38% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 180 0.31% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 129 0.22% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 154 0.27% 96.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 478 0.83% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 131 0.23% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 143 0.25% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 111 0.19% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 107 0.19% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 71 0.12% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 85 0.15% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 71 0.12% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 101 0.18% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 73 0.13% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 62 0.11% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 52 0.09% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 38 0.07% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 47 0.08% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 26 0.05% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 37 0.06% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 49 0.09% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 22 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 8 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 12 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 6 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 8 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61315 # Writes before turning the bus around for reads -system.physmem.totQLat 31916274746 # Total ticks spent queuing -system.physmem.totMemAccLat 50407093496 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4930885000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32363.64 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 57494 # Writes before turning the bus around for reads +system.physmem.totQLat 32578317305 # Total ticks spent queuing +system.physmem.totMemAccLat 50896861055 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4884945000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33345.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51113.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.33 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.33 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52095.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing -system.physmem.readRowHits 734466 # Number of row buffer hits during reads -system.physmem.writeRowHits 450279 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.06 # Row buffer hit rate for writes -system.physmem.avgGap 21884340.09 # Average gap between requests -system.physmem.pageHitRate 54.61 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3920933520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2139398250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3860672400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3974430240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1203845511330 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27465556979250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31788114192270 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.717535 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45690953287273 # Time in different power states -system.physmem_0.memoryStateTime::REF 1587329380000 # Time in different power states +system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing +system.physmem.readRowHits 734277 # Number of row buffer hits during reads +system.physmem.writeRowHits 451275 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.18 # Row buffer hit rate for writes +system.physmem.avgGap 21906655.19 # Average gap between requests +system.physmem.pageHitRate 54.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3752269920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2047369500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3667786200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3862203120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1180767055500 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27377781027000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31664935054200 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.658673 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45545161867023 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581317660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 257656491727 # Time in different power states +system.physmem_0.memoryStateTime::ACT 229423166977 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3522604680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1922056125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3831445800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3692478960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1196085851100 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27472363698750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31786234402695 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.677991 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45702273449121 # Time in different power states -system.physmem_1.memoryStateTime::REF 1587329380000 # Time in different power states +system.physmem_1.actEnergy 3607556400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1968408750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3952673400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3797714160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1177905490200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27380291180250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31664580366120 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.651183 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45549316476567 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581317660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 246336261879 # Time in different power states +system.physmem_1.memoryStateTime::ACT 225268560933 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -378,22 +386,22 @@ system.realview.nvmem.bw_total::total 28 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 146462396 # Number of BP lookups -system.cpu0.branchPred.condPredicted 102364881 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6839955 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 108739004 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75372629 # Number of BTB hits +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 145452632 # Number of BP lookups +system.cpu0.branchPred.condPredicted 102233764 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6537956 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 107843095 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75495824 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 69.315173 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17612403 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1195732 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 3915449 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2665463 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1249986 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 447212 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 70.005246 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17327542 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1162135 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 3835403 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2658726 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1176677 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 420775 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -424,62 +432,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 302048 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 302048 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10564 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84260 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 302048 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 302048 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 302048 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 94824 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22896.634818 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21259.302446 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 17613.215135 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 93928 99.06% 99.06% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 167 0.18% 99.23% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 600 0.63% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 32 0.03% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 34 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 94824 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 84260 88.86% 88.86% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10564 11.14% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 94824 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302048 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 298304 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 298304 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10716 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85635 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 298304 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 298304 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 298304 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 96351 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22754.257870 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21300.315388 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14215.969550 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 95122 98.72% 98.72% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1073 1.11% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 26 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 56 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 56 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 96351 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 734209704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 734209704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 734209704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 85635 88.88% 88.88% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10716 11.12% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 96351 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 298304 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302048 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94824 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 298304 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96351 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94824 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 396872 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96351 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 394655 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 94909868 # DTB read hits -system.cpu0.dtb.read_misses 253021 # DTB read misses -system.cpu0.dtb.write_hits 83284387 # DTB write hits -system.cpu0.dtb.write_misses 49027 # DTB write misses +system.cpu0.dtb.read_hits 93899745 # DTB read hits +system.cpu0.dtb.read_misses 250404 # DTB read misses +system.cpu0.dtb.write_hits 82108561 # DTB write hits +system.cpu0.dtb.write_misses 47900 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 38313 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2113 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 10577 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 39156 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2185 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 10307 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10792 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 95162889 # DTB read accesses -system.cpu0.dtb.write_accesses 83333414 # DTB write accesses +system.cpu0.dtb.perms_faults 10956 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 94150149 # DTB read accesses +system.cpu0.dtb.write_accesses 82156461 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 178194255 # DTB hits -system.cpu0.dtb.misses 302048 # DTB misses -system.cpu0.dtb.accesses 178496303 # DTB accesses +system.cpu0.dtb.hits 176008306 # DTB hits +system.cpu0.dtb.misses 298304 # DTB misses +system.cpu0.dtb.accesses 176306610 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -509,885 +516,876 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 66529 # Table walker walks requested -system.cpu0.itb.walker.walksLong 66529 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 603 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54822 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 66529 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 66529 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 66529 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 55425 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25786.567433 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23469.117152 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 20785.804114 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 51379 92.70% 92.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3140 5.67% 98.37% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 12 0.02% 98.39% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.39% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 536 0.97% 99.36% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 270 0.49% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 8 0.01% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 15 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 29 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 55425 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54822 98.91% 98.91% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 603 1.09% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 55425 # Table walker page sizes translated +system.cpu0.itb.walker.walks 65048 # Table walker walks requested +system.cpu0.itb.walker.walksLong 65048 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 515 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52970 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 65048 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 65048 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 65048 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 53485 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25497.494625 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23453.450778 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17328.133028 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 49469 92.49% 92.49% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2789 5.21% 97.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 9 0.02% 97.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 1088 2.03% 99.76% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 53485 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 733487204 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 733487204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 733487204 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 52970 99.04% 99.04% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 515 0.96% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 53485 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66529 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66529 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65048 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65048 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55425 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55425 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 121954 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 260612167 # ITB inst hits -system.cpu0.itb.inst_misses 66529 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53485 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53485 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 118533 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 259203584 # ITB inst hits +system.cpu0.itb.inst_misses 65048 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 27578 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 28333 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 178681 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 171713 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 260678696 # ITB inst accesses -system.cpu0.itb.hits 260612167 # DTB hits -system.cpu0.itb.misses 66529 # DTB misses -system.cpu0.itb.accesses 260678696 # DTB accesses -system.cpu0.numCycles 1099930824 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 259268632 # ITB inst accesses +system.cpu0.itb.hits 259203584 # DTB hits +system.cpu0.itb.misses 65048 # DTB misses +system.cpu0.itb.accesses 259268632 # DTB accesses +system.cpu0.numCycles 1023758481 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 487305462 # Number of instructions committed -system.cpu0.committedOps 572197777 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 47186623 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4440 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93972724601 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.257169 # CPI: cycles per instruction -system.cpu0.ipc 0.443033 # IPC: instructions per cycle +system.cpu0.committedInsts 483101155 # Number of instructions committed +system.cpu0.committedOps 567019823 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 47457065 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4178 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93688785177 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.119139 # CPI: cycles per instruction +system.cpu0.ipc 0.471890 # IPC: instructions per cycle system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 396450876 69.29% 69.29% # Class of committed instruction -system.cpu0.op_class_0::IntMult 1302433 0.23% 69.51% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 64217 0.01% 69.52% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 76920 0.01% 69.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.op_class_0::MemRead 91382938 15.97% 85.51% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 82920392 14.49% 100.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 393333975 69.37% 69.37% # Class of committed instruction +system.cpu0.op_class_0::IntMult 1298911 0.23% 69.60% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 62117 0.01% 69.61% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 39633 0.01% 69.62% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction +system.cpu0.op_class_0::MemRead 90520623 15.96% 85.58% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 81764563 14.42% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 572197777 # Class of committed instruction +system.cpu0.op_class_0::total 567019823 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13277 # number of quiesce instructions executed -system.cpu0.tickCycles 780613530 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 319317294 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5972011 # number of replacements -system.cpu0.dcache.tags.tagsinuse 508.033077 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 169168179 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5972523 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.324408 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.033077 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992252 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.992252 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 13020 # number of quiesce instructions executed +system.cpu0.tickCycles 768761843 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 254996638 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 6026209 # number of replacements +system.cpu0.dcache.tags.tagsinuse 478.505782 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 166971566 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6026721 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.705209 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 5039130000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.505782 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934582 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.934582 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 388 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 359361260 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 359361260 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 87043361 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 87043361 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 77242749 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 77242749 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 305030 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 305030 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 287060 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 287060 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877481 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1877481 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1849167 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1849167 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 164573170 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 164573170 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 164878200 # number of overall hits -system.cpu0.dcache.overall_hits::total 164878200 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3693348 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3693348 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2460225 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2460225 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 661742 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 661742 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 847892 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 847892 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173543 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 173543 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200600 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 200600 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 7001465 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 7001465 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 7663207 # number of overall misses -system.cpu0.dcache.overall_misses::total 7663207 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 64125292500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 64125292500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62047058000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 62047058000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 51167444000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 51167444000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2860725000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2860725000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5699610500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5699610500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5746000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5746000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 177339794500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 177339794500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 177339794500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 177339794500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 90736709 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 90736709 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 79702974 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 79702974 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 966772 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 966772 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1134952 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1134952 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2051024 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2051024 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2049767 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2049767 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 171574635 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 171574635 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 172541407 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 172541407 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040704 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.040704 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030867 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030867 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.684486 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.684486 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.747073 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.747073 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084613 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084613 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097865 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097865 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040807 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.040807 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.044414 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.044414 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17362.374870 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17362.374870 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25220.074587 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25220.074587 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60346.652640 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60346.652640 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16484.243098 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16484.243098 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28412.814058 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28412.814058 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 355154483 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 355154483 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 85976696 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 85976696 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 76051356 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 76051356 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300861 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 300861 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 281214 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 281214 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1915398 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1915398 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1894723 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1894723 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 162309266 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 162309266 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 162610127 # number of overall hits +system.cpu0.dcache.overall_hits::total 162610127 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3729679 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3729679 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2481919 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2481919 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 681303 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 681303 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 827220 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 827220 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 176003 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 176003 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195484 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 7038818 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 7038818 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 7720121 # number of overall misses +system.cpu0.dcache.overall_misses::total 7720121 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57503024000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 57503024000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 50806938500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 50806938500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 27591387500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 27591387500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2577956500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2577956500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4885048500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4885048500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3405000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3405000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 135901350000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 135901350000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 135901350000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 135901350000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 89706375 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 89706375 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 78533275 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 78533275 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 982164 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 982164 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1108434 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1108434 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2091401 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2091401 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2090207 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2090207 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 169348084 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 169348084 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 170330248 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 170330248 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041577 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.041577 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031603 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.031603 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.693675 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.693675 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.746296 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.746296 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084156 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084156 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.093524 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.093524 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041564 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.041564 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045324 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045324 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15417.687152 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15417.687152 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20470.828621 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20470.828621 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33354.352530 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33354.352530 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.230445 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.230445 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24989.505535 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24989.505535 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25328.955369 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25328.955369 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23141.720496 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23141.720496 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19307.410704 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19307.410704 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17603.525903 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17603.525903 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5972043 # number of writebacks -system.cpu0.dcache.writebacks::total 5972043 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444932 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 444932 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1012331 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1012331 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 90 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 90 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46565 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46565 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 65 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457353 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1457353 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457353 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1457353 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3248416 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3248416 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1447894 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1447894 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 660170 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 660170 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 847802 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 847802 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126978 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126978 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200535 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 200535 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5544112 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5544112 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6204282 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6204282 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31552 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31552 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31148 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31148 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62700 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62700 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50756784000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50756784000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36350818500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36350818500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16579433500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16579433500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 50311370000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 50311370000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1783759500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1783759500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5494928000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5494928000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5416500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5416500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 137418972500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 137418972500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 153998406000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 153998406000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6041391000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6041391000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6041391000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6041391000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018166 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018166 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.682860 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.682860 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746994 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746994 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061910 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097833 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097833 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032313 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032313 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035958 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.035958 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15625.087427 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15625.087427 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25105.994292 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25105.994292 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25113.885060 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25113.885060 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59343.301856 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59343.301856 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14047.783868 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14047.783868 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27401.341412 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27401.341412 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 6026220 # number of writebacks +system.cpu0.dcache.writebacks::total 6026220 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 447326 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 447326 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1020420 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1020420 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 73 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 73 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44988 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44988 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1467819 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1467819 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1467819 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1467819 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3282353 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3282353 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1461499 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1461499 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 679841 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 679841 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 827147 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 827147 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 131015 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 131015 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195417 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 195417 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5570999 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5570999 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6250840 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6250840 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31702 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62927 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45702695000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45702695000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29281044500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29281044500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14665959000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14665959000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 26759895500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26759895500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1703041500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1703041500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4687173500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4687173500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3267500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3267500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 101743635000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 101743635000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116409594000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 116409594000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6136923000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6136923000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6136923000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6136923000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036590 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036590 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018610 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018610 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.692187 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.692187 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746230 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746230 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062645 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062645 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093492 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093492 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032897 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032897 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036698 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.036698 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13923.759876 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13923.759876 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20034.939812 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20034.939812 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21572.630953 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21572.630953 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32352.043228 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32352.043228 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12998.828378 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12998.828378 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23985.495121 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23985.495121 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24786.471215 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24786.471215 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24821.309863 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24821.309863 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191474.106237 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191474.106237 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96353.923445 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96353.923445 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 10516028 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.897153 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 249911266 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 10516540 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 23.763640 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 33054279000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897153 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999799 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18263.086208 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18263.086208 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18623.032104 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18623.032104 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193581.572141 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193581.572141 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97524.480748 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97524.480748 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 9817579 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.932451 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 249208397 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9818091 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 25.382572 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 22021065000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932451 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 531372181 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 531372181 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 249911266 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 249911266 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 249911266 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 249911266 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 249911266 # number of overall hits -system.cpu0.icache.overall_hits::total 249911266 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 10516550 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 10516550 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 10516550 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 10516550 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 10516550 # number of overall misses -system.cpu0.icache.overall_misses::total 10516550 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 109481334000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 109481334000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 109481334000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 109481334000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 109481334000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 109481334000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 260427816 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 260427816 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 260427816 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 260427816 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 260427816 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 260427816 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040382 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.040382 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040382 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.040382 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040382 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.040382 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10410.384965 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10410.384965 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10410.384965 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10410.384965 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10410.384965 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10410.384965 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 527871096 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 527871096 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 249208397 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 249208397 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 249208397 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 249208397 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 249208397 # number of overall hits +system.cpu0.icache.overall_hits::total 249208397 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9818101 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9818101 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9818101 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9818101 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9818101 # number of overall misses +system.cpu0.icache.overall_misses::total 9818101 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 99002118000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 99002118000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 99002118000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 99002118000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 99002118000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 99002118000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 259026498 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 259026498 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 259026498 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 259026498 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 259026498 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 259026498 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037904 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.037904 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037904 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.037904 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037904 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.037904 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10083.632059 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10083.632059 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10083.632059 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10083.632059 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 10516028 # number of writebacks -system.cpu0.icache.writebacks::total 10516028 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10516550 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 10516550 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 10516550 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 10516550 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 10516550 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 10516550 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 104223059500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 104223059500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 104223059500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 104223059500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 104223059500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 104223059500 # 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average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8036343 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8037705 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 1205 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.writebacks::writebacks 9817579 # number of writebacks +system.cpu0.icache.writebacks::total 9817579 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9818101 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9818101 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9818101 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9818101 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9818101 # 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number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 94093068000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4837195500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4837195500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4837195500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 4837195500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037904 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.037904 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037904 # 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average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92491.166179 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8242304 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8243665 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 1198 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1038823 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2850300 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16126.746563 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 26039957 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2866458 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.084367 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 8707838500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15278.163009 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 75.302883 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 76.950246 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 696.330425 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.932505 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004596 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004697 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.042501 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984298 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1240 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14860 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 522 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 622 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 73 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 43 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1092 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5314 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7823 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 536 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.075684 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.906982 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 554897291 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 554897291 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 569819 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 172472 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 742291 # 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number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8465 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 724175 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1288143 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 2033082 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12299 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8465 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 724175 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1288143 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 828377 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2861459 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 84001 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 115226 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 290829500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 661622000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38426708957 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38426708957 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5314605493 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5314605493 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3216326998 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3216326998 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2770000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2770000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11196985497 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11196985497 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20080949000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20080949000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 29451947493 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 29451947493 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 20309675000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 20309675000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 290829500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20080949000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 40648932990 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 61391503990 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 290829500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20080949000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 40648932990 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38426708957 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 99818212947 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4418803500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5883144500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10301948000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418803500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5883144500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10301948000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027711 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998585 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998585 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997627 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997627 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.224517 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.224517 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071267 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254730 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254730 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728290 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728290 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.125137 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.222469 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.222469 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073759 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248813 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248813 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.737239 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.737239 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128085 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.174585 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35899.796364 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56710.263890 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29958.038116 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29958.038116 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19875.340328 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19875.340328 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 994400 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 994400 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58388.867967 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58388.867967 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33267.758218 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35913.269977 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35913.269977 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70950.838813 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70950.838813 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37874.691491 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43209.493938 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183468.464757 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152454.084735 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92325.311005 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111164.795799 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 33857668 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 17264460 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3128 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2263959 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2263472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 487 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 924227 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 15578589 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31149 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31148 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5528357 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 12594701 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 3060195 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1058289 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 483217 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361321 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 533499 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1230571 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1205955 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10516550 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5115631 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 898497 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 845557 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 31653744 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19358528 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 379556 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1223236 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 52615064 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1349432640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 724409976 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1445984 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4653440 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 2079942040 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7567377 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 25314697 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.102016 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.302732 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.180273 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 31863.899056 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46387.947706 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20687.367869 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20687.367869 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16459.293479 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16459.293479 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 461666.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461666.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41499.673832 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41499.673832 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27729.414851 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28921.697098 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28921.697098 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33385.840298 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33385.840298 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30196.275404 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34883.677504 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185576.446281 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122640.778086 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93491.577542 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89406.453405 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 32574371 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16625689 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2229520 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2229086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 913111 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14927613 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5591471 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 11901739 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2979875 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1058098 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 473129 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352230 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 525861 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1247048 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1223348 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9818101 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5127973 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 875849 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 825149 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29558377 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19506589 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370132 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1208276 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 50643374 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1260030528 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 732739948 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1405536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4588864 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1998764876 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7447074 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 24526103 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.104449 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.305900 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 22732690 89.80% 89.80% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2581520 10.20% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 487 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 21964812 89.56% 89.56% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2560857 10.44% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 434 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 25314697 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 33752723480 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 24526103 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 32454354981 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 205163062 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 208052919 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 15856801952 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14809077024 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8551593856 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8648892723 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 198848419 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 194486906 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 641675758 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 634782270 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 127453033 # Number of BP lookups -system.cpu1.branchPred.condPredicted 91217282 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5663830 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 96224557 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 67852361 # Number of BTB hits +system.cpu1.branchPred.lookups 123875539 # Number of BP lookups +system.cpu1.branchPred.condPredicted 88073767 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5721607 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 93465185 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 65276742 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 70.514600 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 14431851 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 916644 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3338859 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2197659 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1141200 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 412569 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 69.840703 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 14217829 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 926540 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3290763 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2135700 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1155063 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 419705 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1417,64 +1415,61 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 261031 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 261031 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9619 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80662 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 261031 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 261031 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 261031 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 90281 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23808.564371 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21471.713865 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 22312.583155 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 88920 98.49% 98.49% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 187 0.21% 98.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 992 1.10% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 43 0.05% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 45 0.05% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 26 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 33 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 21 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 90281 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1786242352 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1786242352 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1786242352 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 80662 89.35% 89.35% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9619 10.65% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 90281 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261031 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 255224 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 255224 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8861 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76574 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 255224 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 255224 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 255224 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 85435 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22815.538128 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21300.261475 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14551.493747 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 84387 98.77% 98.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 897 1.05% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 42 0.05% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 51 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 31 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 85435 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -788977056 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -788977056 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -788977056 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 76574 89.63% 89.63% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8861 10.37% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 85435 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 255224 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261031 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90281 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 255224 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85435 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90281 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 351312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85435 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 340659 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 80497438 # DTB read hits -system.cpu1.dtb.read_misses 213464 # DTB read misses -system.cpu1.dtb.write_hits 70911031 # DTB write hits -system.cpu1.dtb.write_misses 47567 # DTB write misses +system.cpu1.dtb.read_hits 78594683 # DTB read hits +system.cpu1.dtb.read_misses 208094 # DTB read misses +system.cpu1.dtb.write_hits 69544419 # DTB write hits +system.cpu1.dtb.write_misses 47130 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37751 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1110 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7072 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 35846 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 839 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11967 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 80710902 # DTB read accesses -system.cpu1.dtb.write_accesses 70958598 # DTB write accesses +system.cpu1.dtb.perms_faults 11450 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 78802777 # DTB read accesses +system.cpu1.dtb.write_accesses 69591549 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 151408469 # DTB hits -system.cpu1.dtb.misses 261031 # DTB misses -system.cpu1.dtb.accesses 151669500 # DTB accesses +system.cpu1.dtb.hits 148139102 # DTB hits +system.cpu1.dtb.misses 255224 # DTB misses +system.cpu1.dtb.accesses 148394326 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1504,864 +1499,883 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 64962 # Table walker walks requested -system.cpu1.itb.walker.walksLong 64962 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 549 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55482 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 64962 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 64962 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 64962 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 56031 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27185.022577 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24059.100661 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 24848.225124 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 54737 97.69% 97.69% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1140 2.03% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 44 0.08% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 63 0.11% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 56031 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1785244852 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1785244852 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1785244852 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 55482 99.02% 99.02% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 549 0.98% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 56031 # Table walker page sizes translated +system.cpu1.itb.walker.walks 62177 # Table walker walks requested +system.cpu1.itb.walker.walksLong 62177 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54596 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 62177 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 62177 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 62177 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 55226 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25650.988665 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23787.605646 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 16059.408850 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 49961 90.47% 90.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 4236 7.67% 98.14% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 9 0.02% 98.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 906 1.64% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 28 0.05% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 55226 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -789630556 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -789630556 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -789630556 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54596 98.86% 98.86% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 630 1.14% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55226 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64962 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64962 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62177 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62177 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56031 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56031 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 120993 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 225980528 # ITB inst hits -system.cpu1.itb.inst_misses 64962 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55226 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55226 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 117403 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 219337574 # ITB inst hits +system.cpu1.itb.inst_misses 62177 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26783 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25383 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 166792 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 167002 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 226045490 # ITB inst accesses -system.cpu1.itb.hits 225980528 # DTB hits -system.cpu1.itb.misses 64962 # DTB misses -system.cpu1.itb.accesses 226045490 # DTB accesses -system.cpu1.numCycles 884296043 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 219399751 # ITB inst accesses +system.cpu1.itb.hits 219337574 # DTB hits +system.cpu1.itb.misses 62177 # DTB misses +system.cpu1.itb.accesses 219399751 # DTB accesses +system.cpu1.numCycles 838096745 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 410764166 # Number of instructions committed -system.cpu1.committedOps 484072804 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 46607969 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5245 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 94188329171 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.152807 # CPI: cycles per instruction -system.cpu1.ipc 0.464510 # IPC: instructions per cycle +system.cpu1.committedInsts 400342475 # Number of instructions committed +system.cpu1.committedOps 472062345 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 44700411 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5381 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93874475142 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.093449 # CPI: cycles per instruction +system.cpu1.ipc 0.477681 # IPC: instructions per cycle system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 334821764 69.17% 69.17% # Class of committed instruction -system.cpu1.op_class_0::IntMult 956339 0.20% 69.37% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 55233 0.01% 69.38% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 37353 0.01% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::MemRead 77588616 16.03% 85.41% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 70613457 14.59% 100.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 326101667 69.08% 69.08% # Class of committed instruction +system.cpu1.op_class_0::IntMult 925373 0.20% 69.28% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 54057 0.01% 69.29% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 72329 0.02% 69.30% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction +system.cpu1.op_class_0::MemRead 75664367 16.03% 85.33% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 69244510 14.67% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 484072804 # Class of committed instruction +system.cpu1.op_class_0::total 472062345 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5362 # number of quiesce instructions executed -system.cpu1.tickCycles 676945147 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 207350896 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5011869 # number of replacements -system.cpu1.dcache.tags.tagsinuse 436.764256 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 143763031 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5012381 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.681585 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8498279834500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 436.764256 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.853055 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.853055 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 305397096 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 305397096 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 73662807 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 73662807 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 66040616 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 66040616 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 200864 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 200864 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 33950 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 33950 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1678906 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1678906 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1638259 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1638259 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 139737373 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 139737373 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 139938237 # number of overall hits -system.cpu1.dcache.overall_hits::total 139938237 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3193197 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3193197 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2277873 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2277873 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 648992 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 648992 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 409957 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 409957 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159945 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 159945 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199493 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 199493 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5881027 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5881027 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6530019 # number of overall misses -system.cpu1.dcache.overall_misses::total 6530019 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52208022500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 52208022500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51224639500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 51224639500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 14899741000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 14899741000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2555092000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2555092000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5532212500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5532212500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5344000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5344000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 118332403000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 118332403000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 118332403000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 118332403000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 76856004 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 76856004 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 68318489 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 68318489 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 849856 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 849856 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 443907 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 443907 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1838851 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1838851 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837752 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1837752 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 145618400 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 145618400 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 146468256 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 146468256 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041548 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.041548 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033342 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.033342 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.763649 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.763649 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.923520 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.923520 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086981 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086981 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108553 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108553 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040387 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.040387 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044583 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044583 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16349.765611 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16349.765611 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22487.926017 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22487.926017 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36344.643463 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36344.643463 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.816343 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.816343 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27731.361501 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27731.361501 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5498 # number of quiesce instructions executed +system.cpu1.tickCycles 657140254 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 180956491 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 4810857 # number of replacements +system.cpu1.dcache.tags.tagsinuse 458.623346 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 140763490 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4811366 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.256450 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8377530544000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.623346 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895749 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.895749 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 298669128 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 298669128 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 72030058 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 72030058 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 64877267 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 64877267 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 197389 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 197389 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 40268 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 40268 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1587155 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1587155 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1543611 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1543611 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 136947593 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 136947593 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 137144982 # number of overall hits +system.cpu1.dcache.overall_hits::total 137144982 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3077185 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3077185 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2162319 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2162319 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 609138 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 609138 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 415243 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 415243 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150447 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 150447 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 192941 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 192941 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5654747 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5654747 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6263885 # number of overall misses +system.cpu1.dcache.overall_misses::total 6263885 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46366444000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 46366444000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40662976500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 40662976500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10070349000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10070349000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2311960000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2311960000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4775235000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4775235000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2623000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2623000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 97099769500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 97099769500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 97099769500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 97099769500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 75107243 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 75107243 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 67039586 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 67039586 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 806527 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 806527 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 455511 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 455511 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1737602 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1737602 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1736552 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1736552 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 142602340 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 142602340 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 143408867 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 143408867 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040971 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.040971 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032254 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032254 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.755261 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.755261 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.911598 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.911598 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086583 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086583 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111106 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.111106 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039654 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.039654 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043679 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043679 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15067.811653 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15067.811653 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18805.262545 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18805.262545 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24251.700811 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24251.700811 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15367.272196 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15367.272196 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24749.716234 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24749.716234 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20121.043995 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20121.043995 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18121.295359 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18121.295359 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17171.372919 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17171.372919 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15501.524932 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15501.524932 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5011891 # number of writebacks -system.cpu1.dcache.writebacks::total 5011891 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 367321 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 367321 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 943211 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 943211 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40165 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40165 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 85 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 85 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310590 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1310590 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310590 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1310590 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2825876 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2825876 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1334662 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1334662 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 648629 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 648629 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 409899 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 409899 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119780 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119780 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199408 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 199408 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4570437 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4570437 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5219066 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5219066 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7337 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7337 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7641 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14978 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14978 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41329046000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41329046000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30034339000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30034339000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15914789000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15914789000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14484285500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14484285500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1714801500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1714801500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5327664500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5327664500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4914500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4914500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 85847670500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 85847670500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101762459500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 101762459500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 919733500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 919733500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 919733500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 919733500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036768 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036768 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019536 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019536 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.763222 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.763222 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.923389 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.923389 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065139 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065139 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108506 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108506 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031386 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031386 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14625.215685 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14625.215685 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22503.329682 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22503.329682 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24536.042946 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24536.042946 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35336.230388 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35336.230388 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14316.258975 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14316.258975 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26717.406022 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26717.406022 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 4810864 # number of writebacks +system.cpu1.dcache.writebacks::total 4810864 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 357052 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 357052 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 892415 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 892415 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40665 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40665 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1249541 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1249541 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1249541 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1249541 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2720133 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2720133 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1269904 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1269904 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 608760 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 608760 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 415169 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 415169 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 109782 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 109782 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 192883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4405206 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4405206 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5013966 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5013966 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6941 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14221 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36972803500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36972803500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23335803000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23335803000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13834846000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13834846000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9650155000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9650155000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1512082000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1512082000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4580259000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4580259000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2341500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69958761500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 69958761500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83793607500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 83793607500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 837242500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 837242500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 837242500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 837242500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036217 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036217 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018943 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018943 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754792 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.754792 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.911436 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.911436 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063180 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063180 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111072 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111072 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030892 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030892 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034963 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034963 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13592.277841 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13592.277841 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18376.037086 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18376.037086 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22726.273080 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22726.273080 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23243.919946 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23243.919946 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13773.496566 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13773.496566 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23746.307347 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23746.307347 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18783.252127 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18783.252127 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19498.212803 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19498.212803 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125355.526782 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125355.526782 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 61405.628255 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 61405.628255 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 8449872 # number of replacements -system.cpu1.icache.tags.tagsinuse 506.781387 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 217357255 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8450384 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.721583 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8379180185000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.781387 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989807 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.989807 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15880.928497 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15880.928497 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16712.041426 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16712.041426 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120622.748883 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120622.748883 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 58873.672738 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 58873.672738 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 8744967 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.224680 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 210419103 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8745479 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 24.060329 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8367967785000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.224680 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990673 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990673 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 365 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 460065662 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 460065662 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 217357255 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 217357255 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 217357255 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 217357255 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 217357255 # number of overall hits -system.cpu1.icache.overall_hits::total 217357255 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8450384 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8450384 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8450384 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8450384 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8450384 # number of overall misses -system.cpu1.icache.overall_misses::total 8450384 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 88216596500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 88216596500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 88216596500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 88216596500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 88216596500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 88216596500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 225807639 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 225807639 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 225807639 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 225807639 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 225807639 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 225807639 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037423 # 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average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 139978.494624 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7137751 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7137894 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 127 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 83895435000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 83895435000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 83895435000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 83895435000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 83895435000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 83895435000 # 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average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90860.215054 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6641051 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6641093 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 36 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 851890 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2314380 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13359.571881 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 21237271 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2330274 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 9.113637 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10056444277000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12441.859609 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 52.856295 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.323629 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 805.532348 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.759391 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003226 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003621 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.049166 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.815404 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1023 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14801 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 326 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 596 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id +system.cpu1.l2cache.prefetcher.pfSpanPage 796339 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2218428 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13419.558556 # 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Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 643 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5454 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8033 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 613 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062439 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004272 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903381 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 455510636 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 455510636 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 505028 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 167261 # 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average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19197.135951 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 897199.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 897199.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44069.998428 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44069.998428 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29828.373467 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31486.407700 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31486.407700 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45586.717224 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45586.717224 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32740.287687 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37793.329747 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117341.079460 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117524.293405 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 57479.736948 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57939.453255 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 27757324 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14199775 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1809 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096264 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095922 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 342 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 778911 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 12918528 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 7641 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7641 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342023 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 10300458 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2852323 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 992320 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 439929 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 359269 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 498097 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1135001 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1111432 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8450384 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4652967 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 462443 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 408042 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25350826 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16287327 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370687 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1094902 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 43103742 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1081622336 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 628052039 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1412064 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4140800 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1715227239 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6782222 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 21311973 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.112849 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.316459 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186208 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 31037.609644 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35918.637723 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20808.816504 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20808.816504 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16224.436051 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16224.436051 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500874.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500874.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32120.644676 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32120.644676 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26735.574243 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26815.018004 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26815.018004 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26186.131086 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26186.131086 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27558.035864 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29846.821834 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112606.396773 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112213.107762 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 54961.043527 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 55142.308230 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 27911552 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14263179 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 2035614 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2035313 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 755700 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13030335 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 7280 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7280 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4134671 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 10529340 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2783515 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 903944 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 426493 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348519 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 477830 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1080105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1057121 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8745479 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4495606 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 466229 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 413447 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26236111 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15633953 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 355051 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1069038 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 43294153 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1119394496 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 601463021 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1354416 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4048968 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1726260901 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6529606 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 21121122 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.110367 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.313393 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 18907277 88.72% 88.72% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2404354 11.28% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 342 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 18790338 88.96% 88.96% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2330483 11.03% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 301 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 21311973 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 27584218481 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 21121122 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 27750114484 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 185839513 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 177306545 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 12678955503 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13121677843 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7484332893 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7163335235 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 194250357 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 185802393 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 577391819 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 563017795 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40390 # Transaction distribution -system.iobus.trans_dist::ReadResp 40390 # Transaction distribution -system.iobus.trans_dist::WriteReq 136973 # Transaction distribution -system.iobus.trans_dist::WriteResp 136973 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40337 # Transaction distribution +system.iobus.trans_dist::ReadResp 40337 # Transaction distribution +system.iobus.trans_dist::WriteReq 136616 # Transaction distribution +system.iobus.trans_dist::WriteResp 136616 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47664 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2372,15 +2386,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122924 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231722 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231722 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122598 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231228 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231228 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354726 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353906 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47684 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2391,103 +2405,103 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155939 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155705 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338928 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338928 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42523001 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496719 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 43180502 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25802501 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25595502 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36398001 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36402501 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568577386 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569469754 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92938000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148162000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147924000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115843 # number of replacements -system.iocache.tags.tagsinuse 11.310828 # Cycle average of tags in use +system.iocache.tags.replacements 115611 # number of replacements +system.iocache.tags.tagsinuse 11.284790 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115859 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115627 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9138959017000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.826637 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.484190 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239165 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.467762 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706927 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9167417766000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.418888 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.865902 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463681 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.241619 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705299 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043106 # Number of tag accesses -system.iocache.tags.data_accesses 1043106 # Number of data accesses +system.iocache.tags.tag_accesses 1040883 # Number of tag accesses +system.iocache.tags.data_accesses 1040883 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115861 # number of demand (read+write) misses -system.iocache.demand_misses::total 115901 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115614 # number of demand (read+write) misses +system.iocache.demand_misses::total 115654 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115861 # number of overall misses -system.iocache.overall_misses::total 115901 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1651659585 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1656859085 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115614 # number of overall misses +system.iocache.overall_misses::total 115654 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1668794518 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1673992518 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13563940301 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13563940301 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15215599886 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15221168386 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15215599886 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15221168386 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12857701236 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12857701236 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14526495754 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14532062754 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14526495754 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14532062754 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115861 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115901 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115614 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115654 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115861 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115901 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115614 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115654 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2501,53 +2515,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186060.559311 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185871.559906 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 187800.418411 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 187604.227054 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126784.755674 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126784.755674 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131329.051397 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131329.051397 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32764 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120471.677873 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120471.677873 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125651.190223 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125651.190223 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33480 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3385 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3531 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.679173 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.481733 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106951 # number of writebacks -system.iocache.writebacks::total 106951 # number of writebacks +system.iocache.writebacks::writebacks 106695 # number of writebacks +system.iocache.writebacks::total 106695 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115861 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115901 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115614 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115654 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115861 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115901 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1207809585 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1211159085 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115614 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115654 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1224494518 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1227842518 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8208491858 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8208491858 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9416301443 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9419869943 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9416301443 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9419869943 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7512769435 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7512769435 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8737263953 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8740830953 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8737263953 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8740830953 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2561,637 +2575,644 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136060.559311 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 135871.559906 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137800.418411 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 137604.227054 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76726.350277 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76726.350277 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency -system.l2c.tags.replacements 1387428 # number of replacements -system.l2c.tags.tagsinuse 63551.257518 # Cycle average of tags in use -system.l2c.tags.total_refs 6641936 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1448331 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.585924 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 22018.288167 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 94.707462 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 112.653017 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5422.209579 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6394.892392 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5645.972820 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 238.578829 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 322.014833 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3724.645789 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6574.117531 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13003.177099 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.335972 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001445 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001719 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.082736 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.097578 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.086151 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003640 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004914 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056834 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.100313 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.198413 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.969715 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10329 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 221 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50353 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 518 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 2097 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 7705 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 212 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2461 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13754 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 33762 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.157608 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003372 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.768326 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 81054625 # Number of tag accesses -system.l2c.tags.data_accesses 81054625 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2804232 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2804232 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 166858 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 141079 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 307937 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43211 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 40746 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 83957 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 52655 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 61293 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113948 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6392 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4086 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 674086 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 617640 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 331682 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 7229 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5312 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 633543 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 593468 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 330392 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3203830 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 133432 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 138176 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 271608 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6392 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4086 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 674086 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 670295 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 331682 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 7229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5312 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 633543 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 654761 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 330392 # number of demand (read+write) hits -system.l2c.demand_hits::total 3317778 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6392 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4086 # number of overall hits -system.l2c.overall_hits::cpu0.inst 674086 # number of overall hits -system.l2c.overall_hits::cpu0.data 670295 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 331682 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 7229 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5312 # number of overall hits -system.l2c.overall_hits::cpu1.inst 633543 # number of overall hits -system.l2c.overall_hits::cpu1.data 654761 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 330392 # number of overall hits -system.l2c.overall_hits::total 3317778 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 63565 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 62220 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 125785 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 13487 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 11849 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 25336 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 80559 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50978 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 131537 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1402 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 75397 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 144871 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 231057 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2351 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1996 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 47759 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 100866 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 195589 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 802834 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 470568 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 95260 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 565828 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1546 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1402 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 75397 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 225430 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 231057 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2351 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1996 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 47759 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 151844 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 195589 # number of demand (read+write) misses -system.l2c.demand_misses::total 934371 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1546 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1402 # number of overall misses -system.l2c.overall_misses::cpu0.inst 75397 # number of overall misses -system.l2c.overall_misses::cpu0.data 225430 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 231057 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2351 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1996 # number of overall misses -system.l2c.overall_misses::cpu1.inst 47759 # number of overall misses -system.l2c.overall_misses::cpu1.data 151844 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 195589 # number of overall misses -system.l2c.overall_misses::total 934371 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 1159828500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1086354500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2246183000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 232119500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 209371000 # 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number of demand (read+write) accesses -system.l2c.demand_accesses::total 4252149 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 7938 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5488 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 749483 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 895725 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 562739 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9580 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7308 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 681302 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 806605 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 525981 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4252149 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.275862 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.306052 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.290013 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.237874 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.225288 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.231817 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.604734 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.454062 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.535825 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.194759 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.255466 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.100599 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.189992 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.410594 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.245407 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.273125 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.070100 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.145270 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.371856 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.200375 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.779086 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.408078 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.675667 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.194759 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.255466 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.100599 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.251673 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.410594 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.245407 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.273125 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.070100 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.188251 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.371856 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.219741 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.194759 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.255466 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.100599 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.251673 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.410594 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.245407 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.273125 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.070100 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.188251 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.371856 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.219741 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18246.338394 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17459.892318 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 17857.320030 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17210.610217 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17669.929952 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 17425.422324 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138407.477749 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133341.617953 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 136444.171602 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141076.649418 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141094.507846 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134468.002706 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139588.703053 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139710.974054 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140691.132265 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134669.842333 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141082.936768 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 156018.317530 # average ReadSharedReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 369.897656 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1578.138778 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::total 573.311148 # average InvalidateReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141076.649418 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141094.507846 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 134468.002706 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 139166.583862 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139710.974054 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140691.132265 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 134669.842333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 138483.973684 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 153262.747812 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141076.649418 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141094.507846 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 134468.002706 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 139166.583862 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139710.974054 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140691.132265 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 134669.842333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 138483.973684 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 153262.747812 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 971 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.738204 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.738204 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency +system.l2c.tags.replacements 1371243 # number of replacements +system.l2c.tags.tagsinuse 63411.869664 # Cycle average of tags in use +system.l2c.tags.total_refs 6460055 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1430877 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.514752 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7876910500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 21329.379338 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 243.549056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 346.213430 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5332.164924 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9972.711960 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14780.287325 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 85.709675 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 92.474711 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3611.694384 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3808.494767 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3809.190093 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.325461 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003716 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.005283 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081362 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.152172 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.225529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001308 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001411 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.055110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.058113 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058124 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.967588 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 9222 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50157 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 98 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 408 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 8708 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1961 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5894 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 42105 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.140717 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.765335 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 79235647 # Number of tag accesses +system.l2c.tags.data_accesses 79235647 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 2747527 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2747527 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 170119 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 132427 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 302546 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 41747 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 38038 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 79785 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 52086 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59057 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 111143 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6348 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3788 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 658119 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 620329 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 316694 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6918 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5196 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 620556 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 563518 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 312616 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 3114082 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 130339 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 134354 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 264693 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6348 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3788 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 658119 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 672415 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 316694 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6918 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5196 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 620556 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 622575 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 312616 # number of demand (read+write) hits +system.l2c.demand_hits::total 3225225 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6348 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3788 # number of overall hits +system.l2c.overall_hits::cpu0.inst 658119 # number of overall hits +system.l2c.overall_hits::cpu0.data 672415 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 316694 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6918 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5196 # number of overall hits +system.l2c.overall_hits::cpu1.inst 620556 # number of overall hits +system.l2c.overall_hits::cpu1.data 622575 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 312616 # number of overall hits +system.l2c.overall_hits::total 3225225 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 63896 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 60301 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 124197 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 12467 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 11210 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 23677 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 80795 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 51109 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 131904 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2056 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1934 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 66055 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 143274 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 256484 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1908 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1578 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 52043 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 103878 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 163476 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 792686 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 465421 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 95414 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 560835 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2056 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1934 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 66055 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 224069 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 256484 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1908 # 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average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73559.456325 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73575.702400 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128404.792537 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123335.036761 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 126439.976478 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124515.989087 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129589.310186 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 143274.851193 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124515.989087 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129165.978772 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 164766.720913 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129716.605957 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130685.882265 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124743.086118 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128482.179649 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 143274.851193 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165462.983424 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99350.240900 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129888.689437 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83264.562249 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48660.123998 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 91156.141469 # average overall mshr uncacheable latency -system.membus.trans_dist::ReadReq 91289 # Transaction distribution -system.membus.trans_dist::ReadResp 902614 # Transaction distribution -system.membus.trans_dist::WriteReq 38789 # Transaction distribution -system.membus.trans_dist::WriteResp 38789 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1182866 # Transaction distribution -system.membus.trans_dist::CleanEvict 259673 # Transaction distribution -system.membus.trans_dist::UpgradeReq 445486 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 315870 # Transaction distribution +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.273042 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.312881 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.291035 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.229959 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.227623 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.608025 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.463927 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.542710 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.187612 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.155621 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.202847 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.781222 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.415262 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.679365 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.249927 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.199302 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.222752 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.249927 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.199302 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.222752 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21610.225883 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21647.742077 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21628.441009 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24617.068902 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24607.448617 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24612.514128 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79236.339662 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72651.227338 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 76684.798346 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79699.783619 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81643.583511 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98118.647459 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20918.654291 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20760.842224 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20891.805966 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167570.579301 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94623.649229 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102107.944449 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84420.399908 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46177.192630 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 71756.492357 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3789204 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2296931 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 91033 # Transaction distribution +system.membus.trans_dist::ReadResp 892432 # Transaction distribution +system.membus.trans_dist::WriteReq 38505 # Transaction distribution +system.membus.trans_dist::WriteResp 38505 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1181777 # Transaction distribution +system.membus.trans_dist::CleanEvict 252869 # Transaction distribution +system.membus.trans_dist::UpgradeReq 437143 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 308404 # Transaction distribution system.membus.trans_dist::UpgradeResp 22 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 143483 # Transaction distribution -system.membus.trans_dist::ReadExResp 126149 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 811325 # Transaction distribution -system.membus.trans_dist::InvalidateReq 668729 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122924 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 143945 # Transaction distribution +system.membus.trans_dist::ReadExResp 126263 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 801399 # Transaction distribution +system.membus.trans_dist::InvalidateReq 663637 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122598 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27208 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4633500 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4783684 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5021882 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155939 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26474 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4585882 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4735006 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4973212 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155705 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 131613504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 131825183 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7257920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 139083103 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 621301 # Total snoops (count) -system.membus.snoop_fanout::samples 3957559 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 130931136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 131141113 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7272704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 138413817 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 608511 # Total snoops (count) +system.membus.snoop_fanout::samples 2484071 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012278 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.110125 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3957559 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2453571 98.77% 98.77% # Request fanout histogram +system.membus.snoop_fanout::1 30500 1.23% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3957559 # Request fanout histogram -system.membus.reqLayer0.occupancy 105148497 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2484071 # Request fanout histogram +system.membus.reqLayer0.occupancy 105594995 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22946496 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22316500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8356686345 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8304045809 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5285705581 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5231778477 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45456154 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45499333 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3245,53 +3266,54 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 12610950 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6824430 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2134576 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 142334 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 128133 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 14201 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 91291 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4901304 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38789 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38789 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3987141 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 3034318 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 743952 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 399827 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1143779 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302895 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302895 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4817262 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 944420 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 837436 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10209362 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8295779 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18505141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250153960 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 205145975 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 455299935 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3080857 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8841930 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.362342 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.484007 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 12326432 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6670511 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2086069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 130580 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 118652 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 11928 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 91035 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4782322 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38505 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38505 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3822609 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2941580 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 730122 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 388189 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1118311 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 299700 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 299700 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4691812 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 853093 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 825528 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10130133 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7962376 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18092509 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250257116 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194861853 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 445118969 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2830390 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8463866 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.368667 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.485356 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5652330 63.93% 63.93% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3175399 35.91% 99.84% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 14201 0.16% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5355444 63.27% 63.27% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3096494 36.58% 99.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 11928 0.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8841930 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9598709952 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8463866 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9400124055 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2569910 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2566916 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4696248682 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4651836575 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4118726891 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3960751843 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |