diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | |
parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 4969 |
1 files changed, 2479 insertions, 2490 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index f7aa432dd..f6bd584fc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.355615 # Number of seconds simulated -sim_ticks 47355615197500 # Number of ticks simulated -final_tick 47355615197500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.357291 # Number of seconds simulated +sim_ticks 47357290872500 # Number of ticks simulated +final_tick 47357290872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119180 # Simulator instruction rate (inst/s) -host_op_rate 140167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6305360463 # Simulator tick rate (ticks/s) -host_mem_usage 747912 # Number of bytes of host memory used -host_seconds 7510.37 # Real time elapsed on the host -sim_insts 895084962 # Number of instructions simulated -sim_ops 1052703090 # Number of ops (including micro ops) simulated +host_inst_rate 179609 # Simulator instruction rate (inst/s) +host_op_rate 211253 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9509351214 # Simulator tick rate (ticks/s) +host_mem_usage 764316 # Number of bytes of host memory used +host_seconds 4980.08 # Real time elapsed on the host +sim_insts 894465242 # Number of instructions simulated +sim_ops 1052057457 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 106496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 83264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 8104128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10821016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 17557952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 158592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 147776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3589696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10178208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 16399360 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 427968 # Number of bytes read from this memory -system.physmem.bytes_read::total 67574456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 8104128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3589696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11693824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78266240 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 141696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 131328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 8696576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13989464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 21378112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 133248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 113344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3297088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 7559072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 13082368 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 433472 # Number of bytes read from this memory +system.physmem.bytes_read::total 68955768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 8696576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3297088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11993664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79042240 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 78287056 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1664 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1301 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 126627 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 169100 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 274343 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2478 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2309 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 159049 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 256240 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6687 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1055887 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1222910 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 79063056 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2214 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2052 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 135884 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 218607 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 334033 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 51517 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 118125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 204412 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6773 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1077470 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1235035 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1225513 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 171133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 228505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 370768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 75803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 214931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 346302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1426958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 171133 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 75803 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 246936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1652734 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1237638 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 183638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 295403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 451422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 69622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 159618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 276248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1456075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 183638 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 69622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 253259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1669062 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1653174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1652734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 171133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 228945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 370768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 75803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 214931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 346302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3080131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1055887 # Number of read requests accepted -system.physmem.writeReqs 1888199 # Number of write requests accepted -system.physmem.readBursts 1055887 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1888199 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 67557888 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue -system.physmem.bytesWritten 120408192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 67574456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 120698960 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6789 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 114993 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 58784 # Per bank write bursts -system.physmem.perBankRdBursts::1 68771 # Per bank write bursts -system.physmem.perBankRdBursts::2 59130 # Per bank write bursts -system.physmem.perBankRdBursts::3 67531 # Per bank write bursts -system.physmem.perBankRdBursts::4 66855 # Per bank write bursts -system.physmem.perBankRdBursts::5 75133 # Per bank write bursts -system.physmem.perBankRdBursts::6 65903 # Per bank write bursts -system.physmem.perBankRdBursts::7 67407 # Per bank write bursts -system.physmem.perBankRdBursts::8 54196 # Per bank write bursts -system.physmem.perBankRdBursts::9 110706 # Per bank write bursts -system.physmem.perBankRdBursts::10 54461 # Per bank write bursts -system.physmem.perBankRdBursts::11 64104 # Per bank write bursts -system.physmem.perBankRdBursts::12 57097 # Per bank write bursts -system.physmem.perBankRdBursts::13 66166 # Per bank write bursts -system.physmem.perBankRdBursts::14 60751 # Per bank write bursts -system.physmem.perBankRdBursts::15 58597 # Per bank write bursts -system.physmem.perBankWrBursts::0 116651 # Per bank write bursts -system.physmem.perBankWrBursts::1 125865 # Per bank write bursts -system.physmem.perBankWrBursts::2 118664 # Per bank write bursts -system.physmem.perBankWrBursts::3 124773 # Per bank write bursts -system.physmem.perBankWrBursts::4 121001 # Per bank write bursts -system.physmem.perBankWrBursts::5 125597 # Per bank write bursts -system.physmem.perBankWrBursts::6 113710 # Per bank write bursts -system.physmem.perBankWrBursts::7 116980 # Per bank write bursts -system.physmem.perBankWrBursts::8 110183 # Per bank write bursts -system.physmem.perBankWrBursts::9 114411 # Per bank write bursts -system.physmem.perBankWrBursts::10 109841 # Per bank write bursts -system.physmem.perBankWrBursts::11 116847 # Per bank write bursts -system.physmem.perBankWrBursts::12 116927 # Per bank write bursts -system.physmem.perBankWrBursts::13 118874 # Per bank write bursts -system.physmem.perBankWrBursts::14 112844 # Per bank write bursts -system.physmem.perBankWrBursts::15 118210 # Per bank write bursts +system.physmem.bw_write::total 1669501 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1669062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 183638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 295842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 451422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 69622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 159618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 276248 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3125576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1077470 # Number of read requests accepted +system.physmem.writeReqs 1907210 # Number of write requests accepted +system.physmem.readBursts 1077470 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1907210 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 68937984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20096 # Total number of bytes read from write queue +system.physmem.bytesWritten 118940800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 68955768 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 121915664 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 314 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 48739 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 118611 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 58565 # Per bank write bursts +system.physmem.perBankRdBursts::1 71236 # Per bank write bursts +system.physmem.perBankRdBursts::2 60619 # Per bank write bursts +system.physmem.perBankRdBursts::3 68763 # Per bank write bursts +system.physmem.perBankRdBursts::4 63623 # Per bank write bursts +system.physmem.perBankRdBursts::5 74242 # Per bank write bursts +system.physmem.perBankRdBursts::6 69161 # Per bank write bursts +system.physmem.perBankRdBursts::7 67695 # Per bank write bursts +system.physmem.perBankRdBursts::8 61029 # Per bank write bursts +system.physmem.perBankRdBursts::9 112215 # Per bank write bursts +system.physmem.perBankRdBursts::10 55292 # Per bank write bursts +system.physmem.perBankRdBursts::11 71140 # Per bank write bursts +system.physmem.perBankRdBursts::12 63760 # Per bank write bursts +system.physmem.perBankRdBursts::13 63951 # Per bank write bursts +system.physmem.perBankRdBursts::14 57537 # Per bank write bursts +system.physmem.perBankRdBursts::15 58328 # Per bank write bursts +system.physmem.perBankWrBursts::0 113661 # Per bank write bursts +system.physmem.perBankWrBursts::1 123588 # Per bank write bursts +system.physmem.perBankWrBursts::2 119813 # Per bank write bursts +system.physmem.perBankWrBursts::3 126847 # Per bank write bursts +system.physmem.perBankWrBursts::4 114977 # Per bank write bursts +system.physmem.perBankWrBursts::5 123724 # Per bank write bursts +system.physmem.perBankWrBursts::6 117451 # Per bank write bursts +system.physmem.perBankWrBursts::7 117840 # Per bank write bursts +system.physmem.perBankWrBursts::8 112656 # Per bank write bursts +system.physmem.perBankWrBursts::9 114020 # Per bank write bursts +system.physmem.perBankWrBursts::10 109420 # Per bank write bursts +system.physmem.perBankWrBursts::11 118853 # Per bank write bursts +system.physmem.perBankWrBursts::12 108855 # Per bank write bursts +system.physmem.perBankWrBursts::13 111956 # Per bank write bursts +system.physmem.perBankWrBursts::14 111151 # Per bank write bursts +system.physmem.perBankWrBursts::15 113638 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 47355613259000 # Total gap between requests +system.physmem.numWrRetry 260 # Number of times write queue was full causing retry +system.physmem.totGap 47357288950000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1055845 # Read request sizes (log2) +system.physmem.readPktSize::6 1077428 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1885596 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 695873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 103690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 49130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 41556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 38114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 34076 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 21396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 5411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1904607 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 705573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 108235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 42943 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 38392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 34676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 22131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,179 +188,169 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 41751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 61472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 87023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 107335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 120415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 125723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 127870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 127803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 120389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 118443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 115533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 109052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 105629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 105973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 96497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 93321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 90489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 85925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1046123 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 179.678328 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 108.587927 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 250.922876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 666099 63.67% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 200536 19.17% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50293 4.81% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24222 2.32% 89.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 17786 1.70% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12328 1.18% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8853 0.85% 93.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7558 0.72% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 58448 5.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1046123 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 79224 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 13.323930 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 140.057237 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 79222 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 44576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 64765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 92305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 104587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 111564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 110175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 106822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 101643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 99926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 96867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 96399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 113990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 101913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 97920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 113164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 100658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 96398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 90928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 4155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 4227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 781 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1066280 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 176.199272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 107.583604 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 245.477591 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 681708 63.93% 63.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 204893 19.22% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51569 4.84% 87.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24658 2.31% 90.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19159 1.80% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12349 1.16% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8689 0.81% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7706 0.72% 94.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 55549 5.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1066280 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 82344 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.080819 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 137.450182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 82341 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 79224 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 79224 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.747576 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.323530 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.901705 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 65925 83.21% 83.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 5556 7.01% 90.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 2071 2.61% 92.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 1166 1.47% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 1087 1.37% 95.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 456 0.58% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 393 0.50% 96.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 290 0.37% 97.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 329 0.42% 97.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 179 0.23% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 294 0.37% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 101 0.13% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 139 0.18% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 103 0.13% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 155 0.20% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 83 0.10% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 89 0.11% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 58 0.07% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 57 0.07% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 65 0.08% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 66 0.08% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 81 0.10% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 58 0.07% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 58 0.07% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 69 0.09% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 72 0.09% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 57 0.07% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 44 0.06% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 31 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 21 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 22 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 15 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 7 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::280-287 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-295 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::296-303 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-311 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::312-319 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-327 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::328-335 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-343 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::344-351 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-359 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::360-367 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-375 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::376-383 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-391 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::456-463 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-503 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 79224 # Writes before turning the bus around for reads -system.physmem.totQLat 39480003252 # Total ticks spent queuing -system.physmem.totMemAccLat 59272353252 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5277960000 # Total ticks spent in databus transfers -system.physmem.avgQLat 37400.82 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 82344 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 82344 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.569343 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.983627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.346474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 74619 90.62% 90.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 3701 4.49% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 1617 1.96% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 776 0.94% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 389 0.47% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 290 0.35% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 467 0.57% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 184 0.22% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 57 0.07% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 20 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 62 0.08% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 36 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 12 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 2 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 5 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 10 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 13 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 9 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 24 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 82344 # Writes before turning the bus around for reads +system.physmem.totQLat 41096385470 # Total ticks spent queuing +system.physmem.totMemAccLat 61293060470 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5385780000 # Total ticks spent in databus transfers +system.physmem.avgQLat 38152.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 56150.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.54 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.43 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 56902.68 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.51 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 797783 # Number of row buffer hits during reads -system.physmem.writeRowHits 1093063 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.10 # Row buffer hit rate for writes -system.physmem.avgGap 16084996.59 # Average gap between requests -system.physmem.pageHitRate 64.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4126437000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2251528125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4130209200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6241801680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1193820708150 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27366157608000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31669766818395 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.764772 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45525574397500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1581308040000 # Time in different power states +system.physmem.avgWrQLen 25.47 # Average write queue length when enqueuing +system.physmem.readRowHits 809420 # Number of row buffer hits during reads +system.physmem.writeRowHits 1059902 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.03 # Row buffer hit rate for writes +system.physmem.avgGap 15866789.39 # Average gap between requests +system.physmem.pageHitRate 63.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4185760320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2283897000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4164435600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6207198480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1197399382470 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27364022846250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31671411386760 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.775859 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45522011263316 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581363940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 248732168750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 253913912184 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3782252880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2063729250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4103353800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5949527760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1183965961905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27374802122250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31667705474085 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.721243 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45539970549502 # Time in different power states -system.physmem_1.memoryStateTime::REF 1581308040000 # Time in different power states +system.physmem_1.actEnergy 3875316480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2114508000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4237256400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5835557520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1190113153695 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27370414275000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31669737933735 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.740522 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45532636458203 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581363940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 234336016748 # Time in different power states +system.physmem_1.memoryStateTime::ACT 243288251797 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -394,15 +384,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 131272413 # Number of BP lookups -system.cpu0.branchPred.condPredicted 92904470 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6038757 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 98925935 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 71271707 # Number of BTB hits +system.cpu0.branchPred.lookups 151571686 # Number of BP lookups +system.cpu0.branchPred.condPredicted 107212809 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6769997 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 114323741 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 82790418 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.045523 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15434878 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1076370 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.417520 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17895403 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1177591 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -433,67 +423,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 271399 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 271399 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8182 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72706 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 271399 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 271399 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 271399 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 80888 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 17168.766430 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 15272.701717 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 12980.054286 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 77350 95.63% 95.63% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2802 3.46% 99.09% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 370 0.46% 99.55% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 250 0.31% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 18 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 21 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 23 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 80888 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 644436704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 644436704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 644436704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 72706 89.88% 89.88% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 8182 10.12% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 80888 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 271399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 310912 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 310912 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11841 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90150 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 310912 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 310912 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 310912 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 101991 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 19193.830760 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17232.192163 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15084.416179 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 100737 98.77% 98.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1058 1.04% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 37 0.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 76 0.07% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 58 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 101991 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 90150 88.39% 88.39% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11841 11.61% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 101991 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 310912 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 271399 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 80888 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 310912 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101991 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 80888 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 352287 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101991 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 412903 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 83830376 # DTB read hits -system.cpu0.dtb.read_misses 224800 # DTB read misses -system.cpu0.dtb.write_hits 74836136 # DTB write hits -system.cpu0.dtb.write_misses 46599 # DTB write misses +system.cpu0.dtb.read_hits 98035121 # DTB read hits +system.cpu0.dtb.read_misses 261233 # DTB read misses +system.cpu0.dtb.write_hits 86222704 # DTB write hits +system.cpu0.dtb.write_misses 49679 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 31986 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8713 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 42277 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2349 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 10561 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10302 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 84055176 # DTB read accesses -system.cpu0.dtb.write_accesses 74882735 # DTB write accesses +system.cpu0.dtb.perms_faults 12531 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 98296354 # DTB read accesses +system.cpu0.dtb.write_accesses 86272383 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 158666512 # DTB hits -system.cpu0.dtb.misses 271399 # DTB misses -system.cpu0.dtb.accesses 158937911 # DTB accesses +system.cpu0.dtb.hits 184257825 # DTB hits +system.cpu0.dtb.misses 310912 # DTB misses +system.cpu0.dtb.accesses 184568737 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -523,185 +507,185 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 59516 # Table walker walks requested -system.cpu0.itb.walker.walksLong 59516 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51758 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 59516 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 59516 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 59516 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 52388 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 19494.417176 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 17354.171367 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 14602.329148 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 48500 92.58% 92.58% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3085 5.89% 98.47% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 277 0.53% 99.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 436 0.83% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 31 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 67664 # Table walker walks requested +system.cpu0.itb.walker.walksLong 67664 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 693 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59407 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 67664 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 67664 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 67664 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 60100 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 21688.993677 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 19128.313408 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17789.670668 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 55182 91.82% 91.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3533 5.88% 97.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 493 0.82% 98.52% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 740 1.23% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.03% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 25 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 48 0.08% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 24 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 15 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 52388 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 643764704 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 643764704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 643764704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 51758 98.80% 98.80% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 630 1.20% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 52388 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 60100 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 59407 98.85% 98.85% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 693 1.15% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 60100 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59516 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59516 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 67664 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 67664 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52388 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52388 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 111904 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 234493726 # ITB inst hits -system.cpu0.itb.inst_misses 59516 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60100 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60100 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 127764 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 272362835 # ITB inst hits +system.cpu0.itb.inst_misses 67664 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 22765 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 29878 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 197741 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 206888 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 234553242 # ITB inst accesses -system.cpu0.itb.hits 234493726 # DTB hits -system.cpu0.itb.misses 59516 # DTB misses -system.cpu0.itb.accesses 234553242 # DTB accesses -system.cpu0.numCycles 936626399 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 272430499 # ITB inst accesses +system.cpu0.itb.hits 272362835 # DTB hits +system.cpu0.itb.misses 67664 # DTB misses +system.cpu0.itb.accesses 272430499 # DTB accesses +system.cpu0.numCycles 1079786982 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 433367687 # Number of instructions committed -system.cpu0.committedOps 509515701 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 43981618 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 3754 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93775213530 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.161274 # CPI: cycles per instruction -system.cpu0.ipc 0.462690 # IPC: instructions per cycle +system.cpu0.committedInsts 504924574 # Number of instructions committed +system.cpu0.committedOps 592395738 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 49310302 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4906 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93635655345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.138511 # CPI: cycles per instruction +system.cpu0.ipc 0.467615 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 12643 # number of quiesce instructions executed -system.cpu0.tickCycles 703108983 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 233517416 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5387052 # number of replacements -system.cpu0.dcache.tags.tagsinuse 501.034252 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 150576282 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5387564 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.948862 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4951668000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.034252 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978583 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.978583 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 320066517 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 320066517 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77114778 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77114778 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69351990 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69351990 # number of WriteReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 251432 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 251432 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1745310 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1745310 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1668274 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1668274 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 146466768 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 146466768 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 146466768 # number of overall hits -system.cpu0.dcache.overall_hits::total 146466768 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3852692 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3852692 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2255601 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2255601 # number of WriteReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 766100 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 766100 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 104059 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 104059 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 180014 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 180014 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6108293 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6108293 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6108293 # number of overall misses -system.cpu0.dcache.overall_misses::total 6108293 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54452724607 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54452724607 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 41906959422 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 41906959422 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 27296991314 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 27296991314 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 1502404735 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 1502404735 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3769027814 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3769027814 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2840500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2840500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 96359684029 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 96359684029 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 96359684029 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 96359684029 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 80967470 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 80967470 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 71607591 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 71607591 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1017532 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1017532 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1849369 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1849369 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1848288 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1848288 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 152575061 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 152575061 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 152575061 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 152575061 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.047583 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.047583 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031499 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.031499 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.752900 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.752900 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056267 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056267 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097395 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097395 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040035 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.040035 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040035 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.040035 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14133.682269 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14133.682269 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18579.065811 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18579.065811 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 35631.107315 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 35631.107315 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14438.008582 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14438.008582 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20937.414946 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20937.414946 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 13863 # number of quiesce instructions executed +system.cpu0.tickCycles 807512344 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 272274638 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 6269899 # number of replacements +system.cpu0.dcache.tags.tagsinuse 502.388707 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 174903450 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6270410 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.893463 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 5096417500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.388707 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981228 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.981228 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 371740852 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 371740852 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 90280740 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 90280740 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80064017 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80064017 # number of WriteReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 281235 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 281235 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1931472 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1931472 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1872190 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1872190 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 170344757 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 170344757 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 170344757 # number of overall hits +system.cpu0.dcache.overall_hits::total 170344757 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 4509015 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 4509015 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2541213 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2541213 # number of WriteReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 864871 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 864871 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 140737 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 140737 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 198480 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 198480 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 7050228 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 7050228 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 7050228 # number of overall misses +system.cpu0.dcache.overall_misses::total 7050228 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 66986292890 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 66986292890 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 47882988891 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 47882988891 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 35264024894 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 35264024894 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2028925085 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2028925085 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4179395855 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4179395855 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2760500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2760500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 114869281781 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 114869281781 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 114869281781 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 114869281781 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 94789755 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 94789755 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 82605230 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 82605230 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1146106 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1146106 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2072209 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2072209 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2070670 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2070670 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 177394985 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 177394985 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 177394985 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 177394985 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.047569 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.047569 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030763 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.030763 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.754617 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.754617 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.067916 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.067916 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095853 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095853 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.039743 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.039743 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039743 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.039743 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.081182 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.081182 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18842.571989 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18842.571989 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40773.739545 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 40773.739545 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14416.429830 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14416.429830 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21057.012571 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21057.012571 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # 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number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -710,88 +694,88 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3733142 # number of writebacks -system.cpu0.dcache.writebacks::total 3733142 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 361487 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 361487 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 935411 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 935411 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 100 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 100 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 34 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1296898 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1296898 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1296898 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1296898 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3491205 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3491205 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1320190 # 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number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42113152704 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42113152704 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22270249828 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22270249828 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 25755951436 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 25755951436 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1293404753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1293404753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3399276642 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3399276642 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2291500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2291500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 64383402532 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 64383402532 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 64383402532 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 64383402532 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5824362996 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5824362996 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5586865743 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5586865743 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11411228739 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11411228739 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043119 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043119 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.752802 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.752802 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056249 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056249 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097359 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097359 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.031535 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031535 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12062.641038 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12062.641038 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16868.973275 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16868.973275 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33623.957488 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 33623.957488 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12433.595318 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12433.595318 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18890.432416 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18890.432416 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 4374601 # number of writebacks +system.cpu0.dcache.writebacks::total 4374601 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 429861 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 429861 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1046667 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1046667 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 81 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 81 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 33 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 33 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 55 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 55 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1476528 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1476528 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1476528 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1476528 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 4079154 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 4079154 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1494546 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1494546 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 864790 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 864790 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140704 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140704 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 198425 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 198425 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5573700 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5573700 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5573700 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5573700 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 53839740568 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 53839740568 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26185332493 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26185332493 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 33958968357 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 33958968357 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1816137650 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1816137650 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3868892109 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3868892109 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2341500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 80025073061 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 80025073061 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 80025073061 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 80025073061 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5766564749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5766564749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5473208250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5473208250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11239772999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11239772999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043034 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043034 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018093 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018093 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.754546 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.754546 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.067900 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.067900 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031420 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.031420 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031420 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031420 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13198.751645 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13198.751645 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17520.593206 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17520.593206 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39268.456339 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39268.456339 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12907.505472 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12907.505472 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19498.007353 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19498.007353 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14357.621160 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14357.621160 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14357.621160 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14357.621160 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -799,58 +783,57 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 9463678 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.932976 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 224826074 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9464190 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 23.755448 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 21621868750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932976 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999869 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 10307657 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.930132 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 261841431 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 10308169 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 25.401352 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 23262861250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930132 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 478044747 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 478044747 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 224826074 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 224826074 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 224826074 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 224826074 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 224826074 # number of overall hits -system.cpu0.icache.overall_hits::total 224826074 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9464200 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9464200 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9464200 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9464200 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9464200 # number of overall misses -system.cpu0.icache.overall_misses::total 9464200 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93878607487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 93878607487 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 93878607487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 93878607487 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 93878607487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 93878607487 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 234290274 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 234290274 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 234290274 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 234290274 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 234290274 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 234290274 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040395 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.040395 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040395 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.040395 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040395 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.040395 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9919.338928 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9919.338928 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9919.338928 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9919.338928 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 554607398 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 554607398 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 261841431 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 261841431 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 261841431 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 261841431 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 261841431 # number of overall hits +system.cpu0.icache.overall_hits::total 261841431 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 10308179 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 10308179 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 10308179 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 10308179 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 10308179 # number of overall misses +system.cpu0.icache.overall_misses::total 10308179 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 103403812050 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 103403812050 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 103403812050 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 103403812050 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 103403812050 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 103403812050 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 272149610 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 272149610 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 272149610 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 272149610 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 272149610 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 272149610 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037877 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.037877 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037877 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.037877 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037877 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.037877 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10031.239470 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10031.239470 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10031.239470 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10031.239470 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10031.239470 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10031.239470 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -859,383 +842,384 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9464200 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9464200 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9464200 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9464200 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9464200 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9464200 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 79648587963 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 79648587963 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 79648587963 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 79648587963 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 79648587963 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 79648587963 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713229500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 4713229500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040395 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.040395 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.040395 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8415.776079 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8415.776079 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8415.776079 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10308179 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 10308179 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 10308179 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 10308179 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 10308179 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 10308179 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 93061406416 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 93061406416 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 93061406416 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 93061406416 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 93061406416 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 93061406416 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037877 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.037877 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.037877 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9027.919133 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9027.919133 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9027.919133 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 11128158 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 11136239 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7035 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 12908052 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 12916183 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7100 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1270201 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2736028 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16197.540138 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15248127 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2752162 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.540418 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5578143500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4129.920995 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 42.114006 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 24.266127 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 6921.151423 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2517.491382 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 2562.596205 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.252070 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002570 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001481 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.422434 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.153655 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.156408 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.988619 # 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Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1002 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2423 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4868 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5129 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.153748 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.826660 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 319708402 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 319708402 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 463342 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 138212 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 8698965 # 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average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26938.772911 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44997.202450 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 44997.202450 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43674.769924 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43674.769924 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20418.408310 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20418.408310 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15115.924084 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15115.924084 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 389899.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 389899.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41290.896998 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41290.896998 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32716.022553 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28945.720413 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32716.022553 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44997.202450 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34931.503009 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1245,69 +1229,66 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 16482247 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 13994677 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33105 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33105 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3733141 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1450559 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1135277 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 764525 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 439100 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 331866 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 445825 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1265717 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1135924 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19032980 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15771109 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 324159 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1044893 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 36173141 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 609055296 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 597396947 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1171600 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3801480 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1211425323 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5254625 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 24752436 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.199831 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.399873 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 17791242 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 15586246 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31969 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31969 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 4374599 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1496771 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1185210 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 863337 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 459789 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 354172 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 478714 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1428335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1300035 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20720970 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18253192 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 368054 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1214499 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 40556715 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 663070976 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 695774006 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1328184 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4426744 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1364599910 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5020747 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 27005623 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.173372 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.378569 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 19806132 80.02% 80.02% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 4946304 19.98% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 22323591 82.66% 82.66% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 4682032 17.34% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 24752436 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14477877088 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 27005623 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 16474086937 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 203336996 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 218344490 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14303799012 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 15570026567 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7760036291 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9017811583 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 177959354 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 202360718 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 570171512 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 661550198 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 141025153 # Number of BP lookups -system.cpu1.branchPred.condPredicted 100933183 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6236213 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 106937612 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 78176713 # Number of BTB hits +system.cpu1.branchPred.lookups 120391711 # Number of BP lookups +system.cpu1.branchPred.condPredicted 86208358 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5520869 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91435615 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 66348303 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.104974 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16283768 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1021605 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.562866 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 13861535 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 936317 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1337,61 +1318,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 298651 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 298651 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11560 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94332 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 298651 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 298651 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 298651 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 105892 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 17805.770634 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 15803.828904 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14966.928967 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 104531 98.71% 98.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1148 1.08% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 61 0.06% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 63 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 105892 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1172907556 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1172907556 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1172907556 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 94332 89.08% 89.08% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11560 10.92% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 105892 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 298651 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 259478 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 259478 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8847 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78200 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 259478 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 259478 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 259478 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 87047 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19103.472745 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17330.859199 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14131.069495 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 82878 95.21% 95.21% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3197 3.67% 98.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 459 0.53% 99.41% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 357 0.41% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 35 0.04% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 16 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 26 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 18 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 28 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 18 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 87047 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 492358444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 492358444 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 492358444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 78200 89.84% 89.84% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8847 10.16% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 87047 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259478 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 298651 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105892 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259478 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87047 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105892 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 404543 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87047 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 346525 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 90905034 # DTB read hits -system.cpu1.dtb.read_misses 248418 # DTB read misses -system.cpu1.dtb.write_hits 78767149 # DTB write hits -system.cpu1.dtb.write_misses 50233 # DTB write misses +system.cpu1.dtb.read_hits 76628852 # DTB read hits +system.cpu1.dtb.read_misses 212787 # DTB read misses +system.cpu1.dtb.write_hits 67332330 # DTB write hits +system.cpu1.dtb.write_misses 46691 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 43819 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 923 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8321 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 32755 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 660 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6687 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 12272 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91153452 # DTB read accesses -system.cpu1.dtb.write_accesses 78817382 # DTB write accesses +system.cpu1.dtb.perms_faults 10091 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 76841639 # DTB read accesses +system.cpu1.dtb.write_accesses 67379021 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 169672183 # DTB hits -system.cpu1.dtb.misses 298651 # DTB misses -system.cpu1.dtb.accesses 169970834 # DTB accesses +system.cpu1.dtb.hits 143961182 # DTB hits +system.cpu1.dtb.misses 259478 # DTB misses +system.cpu1.dtb.accesses 144220660 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1421,179 +1408,178 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 67610 # Table walker walks requested -system.cpu1.itb.walker.walksLong 67610 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 497 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58418 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 67610 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 67610 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 67610 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 58915 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 20253.386778 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 17562.612185 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 17511.554701 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 57403 97.43% 97.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1356 2.30% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 66 0.11% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 56 0.10% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 59975 # Table walker walks requested +system.cpu1.itb.walker.walksLong 59975 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 467 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50555 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 59975 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 59975 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 59975 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 51022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21947.479421 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19426.626910 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17730.380785 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 49865 97.73% 97.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1035 2.03% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.09% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 47 0.09% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 12 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 58915 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1173450056 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1173450056 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1173450056 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 58418 99.16% 99.16% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 497 0.84% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 58915 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 51022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 491673944 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 491673944 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 491673944 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 50555 99.08% 99.08% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 467 0.92% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 51022 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67610 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 67610 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59975 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59975 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58915 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58915 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 126525 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 252933263 # ITB inst hits -system.cpu1.itb.inst_misses 67610 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51022 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51022 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 110997 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 214508261 # ITB inst hits +system.cpu1.itb.inst_misses 59975 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31594 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 23598 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 222493 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 213038 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 253000873 # ITB inst accesses -system.cpu1.itb.hits 252933263 # DTB hits -system.cpu1.itb.misses 67610 # DTB misses -system.cpu1.itb.accesses 253000873 # DTB accesses -system.cpu1.numCycles 943783669 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 214568236 # ITB inst accesses +system.cpu1.itb.hits 214508261 # DTB hits +system.cpu1.itb.misses 59975 # DTB misses +system.cpu1.itb.accesses 214568236 # DTB accesses +system.cpu1.numCycles 819770260 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 461717275 # Number of instructions committed -system.cpu1.committedOps 543187389 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 49256164 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5826 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93768369123 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.044073 # CPI: cycles per instruction -system.cpu1.ipc 0.489219 # IPC: instructions per cycle +system.cpu1.committedInsts 389540668 # Number of instructions committed +system.cpu1.committedOps 459661719 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 43651844 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5040 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93895466763 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.104454 # CPI: cycles per instruction +system.cpu1.ipc 0.475183 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5890 # number of quiesce instructions executed -system.cpu1.tickCycles 748189458 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 195594211 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5624476 # number of replacements -system.cpu1.dcache.tags.tagsinuse 426.107402 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 161270449 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5624987 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.670368 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8377201144000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.107402 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832241 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.832241 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 342291215 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 342291215 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 83489779 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 83489779 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 73474609 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 73474609 # number of WriteReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 71990 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 71990 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1908367 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1908367 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1854336 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1854336 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 156964388 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 156964388 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 156964388 # number of overall hits -system.cpu1.dcache.overall_hits::total 156964388 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 4311289 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 4311289 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2366929 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2366929 # number of WriteReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 476593 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 476593 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 141331 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 141331 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193852 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 193852 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 6678218 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 6678218 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6678218 # number of overall misses -system.cpu1.dcache.overall_misses::total 6678218 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 60722587231 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 60722587231 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 38093191666 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 38093191666 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11613108236 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11613108236 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 1977833980 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 1977833980 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3982712056 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3982712056 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2357000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2357000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 98815778897 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 98815778897 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 98815778897 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 98815778897 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 87801068 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 87801068 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 75841538 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 75841538 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 548583 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 548583 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2049698 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2049698 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2048188 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2048188 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 163642606 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 163642606 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 163642606 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 163642606 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049103 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049103 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031209 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.031209 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.868771 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.868771 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.068952 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.068952 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040810 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.040810 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040810 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040810 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14084.555044 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14084.555044 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16093.930856 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16093.930856 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 24366.929930 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 24366.929930 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13994.339388 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13994.339388 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20545.117182 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20545.117182 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5089 # number of quiesce instructions executed +system.cpu1.tickCycles 643812229 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 175958031 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 4705434 # number of replacements +system.cpu1.dcache.tags.tagsinuse 416.508572 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 136862260 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4705946 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.082837 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8379321114000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.508572 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.813493 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.813493 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 290353323 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 290353323 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 70292866 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 70292866 # 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number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3974138991 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3324999 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3324999 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 87363321806 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 87363321806 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 87363321806 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 87363321806 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 73917642 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 73917642 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 64808567 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 64808567 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 419804 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 419804 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1816419 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1816419 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1815253 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1815253 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 138726209 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 138726209 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 138726209 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 138726209 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049038 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049038 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032198 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032198 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.911535 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.911535 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.058097 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.058097 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103710 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103710 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041171 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.041171 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041171 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.041171 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13957.756058 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13957.756058 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17620.620257 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17620.620257 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27091.240860 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27091.240860 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14543.932028 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14543.932028 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21109.954855 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21109.954855 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14796.728543 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14796.728543 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15296.005997 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15296.005997 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1602,88 +1588,88 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3711348 # number of writebacks -system.cpu1.dcache.writebacks::total 3711348 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 397792 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 397792 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 970938 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 970938 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 60 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 60 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 47 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 47 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 68 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 68 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1368730 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1368730 # 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mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044572 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018407 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018407 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.868662 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.868662 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068929 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068929 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094612 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094612 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032446 # 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average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11987.433099 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18496.990954 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18496.990954 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3043303 # number of writebacks +system.cpu1.dcache.writebacks::total 3043303 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 326021 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 326021 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 860988 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 860988 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 76 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 76 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 32 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 32 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 53 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1187009 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1187009 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1187009 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1187009 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3298755 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3298755 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1225748 # 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number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40628902084 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40628902084 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20156955784 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20156955784 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9784547475 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 9784547475 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1375359879 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1375359879 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3682414982 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3682414982 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2828501 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2828501 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60785857868 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 60785857868 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60785857868 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 60785857868 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 684362251 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 684362251 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 814922500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 814922500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1499284751 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1499284751 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044627 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044627 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018913 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018913 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.911354 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.911354 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058080 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058080 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103680 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103680 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.032615 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032615 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12316.435165 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12316.435165 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16444.616499 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16444.616499 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25574.498745 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25574.498745 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13036.957250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13036.957250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19565.874531 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19565.874531 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # 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average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1691,58 +1677,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 9215030 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.228865 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 243489253 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9215542 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 26.421588 # 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average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9885.171123 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9885.171123 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9885.171123 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9885.171123 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1751,242 +1737,241 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9215542 # 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number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8552000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8552000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8552000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039730 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.039730 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.039730 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8882.664491 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8882.664491 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8882.664491 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 11995647 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 12001276 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 4903 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 10121407 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 10125724 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 3757 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 1360052 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2569302 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13533.660217 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 15700970 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2584965 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.073958 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9611078525000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5526.220513 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 77.627317 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 76.256480 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3620.154380 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2817.959604 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1415.441924 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.337294 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004738 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004654 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.220957 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.171995 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086392 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.826029 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2491 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13080 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 600 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1302 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 576 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 72 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4875 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5316 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2499 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.152039 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.798340 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 321109712 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 321109712 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 544517 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158528 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 8400098 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 3278512 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 12381655 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3711345 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3711345 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 202419 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 202419 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 77280 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 77280 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 41809 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 41809 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 939119 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 939119 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 544517 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 158528 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 8400098 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 4217631 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 13320774 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 544517 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 158528 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 8400098 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 4217631 # number of overall hits -system.cpu1.l2cache.overall_hits::total 13320774 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12561 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8870 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 815444 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 775983 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1612858 # number of ReadReq misses +system.cpu1.l2cache.prefetcher.pfSpanPage 1112844 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2221085 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13329.151476 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 13836589 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2237248 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.184647 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 10494820402000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5280.158493 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 74.775550 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 82.006725 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3962.886937 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2390.470426 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1538.853345 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.322275 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004564 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005005 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.241875 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.145903 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.093924 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.813547 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2457 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13645 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 113 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 719 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 972 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 645 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 937 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4967 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4448 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3191 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.149963 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832825 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 282497183 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 282497183 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 472812 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141552 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 7799132 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 2711848 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 11125344 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3043302 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3043302 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 157363 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 157363 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 71855 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 71855 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 32392 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 32392 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 766594 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 766594 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 472812 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141552 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 7799132 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3478442 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 11891938 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 472812 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141552 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 7799132 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3478442 # number of overall hits +system.cpu1.l2cache.overall_hits::total 11891938 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12653 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8998 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 714562 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 692201 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1428414 # number of ReadReq misses system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 272843 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 272843 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 137034 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 137034 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 151974 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 151974 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 244121 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 244121 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12561 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8870 # 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mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.200339 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.200339 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.193066 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.121764 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.193066 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.236903 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.236903 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.210659 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.122848 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.210659 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.189778 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24608.899371 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22693.811450 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39997.101782 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26038.478163 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 26038.478163 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16876.429733 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16876.429733 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13661.751912 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13661.751912 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1461500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1461500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30747.372117 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30747.372117 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26047.861530 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23726.811542 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26047.861530 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29557.889053 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191906 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 23524.613506 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23038.594142 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36143.355229 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30445.827572 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30445.827572 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19406.762982 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19406.762982 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14569.405435 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14569.405435 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 393582.833333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 393582.833333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31760.741811 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31760.741811 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24293.872687 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28557.983969 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2146,66 +2131,63 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 16597851 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 14230777 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5242 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5242 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3711346 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1418597 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1143341 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 475262 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 452039 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 340076 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 470072 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 15445485 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 12769085 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6630 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6630 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3043303 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1203167 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105360 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 381381 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 459466 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 345603 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 466676 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1342662 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1189275 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18431264 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16132557 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 369420 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1220438 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 36153679 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 589800448 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 609347251 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1339184 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4456624 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1204943507 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5386490 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 25000724 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.203488 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.402593 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1177489 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1018273 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17027569 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13630896 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 329758 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1060916 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 32049139 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 544882176 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 508019480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1204400 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3883720 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1057989776 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5539420 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 22773399 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.231012 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.421480 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 19913365 79.65% 79.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 5087359 20.35% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 17512462 76.90% 76.90% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 5260937 23.10% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 25000724 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 14152090513 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 22773399 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 12190933688 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 175296997 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 175938985 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13837074197 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 12781364350 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8360530852 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7076644304 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 202402154 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 179556153 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 663973984 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 575808723 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40424 # Transaction distribution -system.iobus.trans_dist::ReadResp 40424 # Transaction distribution -system.iobus.trans_dist::WriteReq 136766 # Transaction distribution -system.iobus.trans_dist::WriteResp 30038 # Transaction distribution +system.iobus.trans_dist::ReadReq 40350 # Transaction distribution +system.iobus.trans_dist::ReadResp 40350 # Transaction distribution +system.iobus.trans_dist::WriteReq 136657 # Transaction distribution +system.iobus.trans_dist::WriteResp 29929 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48186 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47838 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2220,13 +2202,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123068 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231232 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231232 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122720 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231214 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231214 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48206 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354014 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47858 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2241,13 +2223,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156198 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338944 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338944 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338872 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497228 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36614000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2275,71 +2257,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1043031468 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607629108 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92794000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179210230 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148521376 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115597 # number of replacements -system.iocache.tags.tagsinuse 11.297216 # Cycle average of tags in use +system.iocache.tags.replacements 115588 # number of replacements +system.iocache.tags.tagsinuse 11.296723 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115604 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9126956441000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.841188 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.456028 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240074 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466002 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706076 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9128912382000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.841062 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.455661 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240066 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465979 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706045 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040901 # Number of tag accesses -system.iocache.tags.data_accesses 1040901 # Number of data accesses +system.iocache.tags.tag_accesses 1040820 # Number of tag accesses +system.iocache.tags.data_accesses 1040820 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8888 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8925 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8879 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8916 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8888 # number of demand (read+write) misses -system.iocache.demand_misses::total 8928 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8879 # number of demand (read+write) misses +system.iocache.demand_misses::total 8919 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8888 # number of overall misses -system.iocache.overall_misses::total 8928 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5659000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1934548608 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1940207608 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28977416630 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28977416630 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6016000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1934548608 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1940564608 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6016000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1934548608 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1940564608 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8879 # number of overall misses +system.iocache.overall_misses::total 8919 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1619625499 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1624820999 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19871885233 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19871885233 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1619625499 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1625189999 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1619625499 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1625189999 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8888 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8925 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8879 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8916 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8888 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8928 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8879 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8919 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8888 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8928 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8879 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8919 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2353,55 +2335,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152945.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 217658.484248 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217390.208179 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271507.164287 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271507.164287 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 150400 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217357.146953 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 150400 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217357.146953 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 228934 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182410.800653 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182236.540938 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186191.863738 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186191.863738 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182410.800653 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 182216.616100 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 182410.800653 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 182216.616100 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110413 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27737 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16202 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.253740 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.814776 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8888 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8925 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8879 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8916 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8888 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8928 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8879 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8919 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8888 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8928 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3735000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1472256614 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1475991614 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427107084 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427107084 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3936000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1472256614 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1476192614 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3936000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1472256614 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1476192614 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8879 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8919 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1156744203 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1160014703 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14321981281 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14321981281 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1156744203 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1160227703 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1156744203 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1160227703 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2415,558 +2397,564 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100945.945946 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165645.433618 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 165377.211653 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219502.914737 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219502.914737 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130278.657844 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 130104.834343 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134191.414446 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134191.414446 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 130278.657844 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 130084.953806 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 130278.657844 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 130084.953806 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1473453 # number of replacements -system.l2c.tags.tagsinuse 64480.086956 # Cycle average of tags in use -system.l2c.tags.total_refs 5089807 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1533812 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.318403 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8003493500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 16627.933383 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.809416 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 10.076521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4159.600580 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3523.314031 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5733.726218 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 373.789781 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 460.262003 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3670.846899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10690.974499 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 19215.753624 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.253722 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000211 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063470 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.053762 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.087490 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005704 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.007023 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.163131 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.293209 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983888 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 14505 # Occupied blocks per task id +system.l2c.tags.replacements 1509391 # number of replacements +system.l2c.tags.tagsinuse 64395.788312 # Cycle average of tags in use +system.l2c.tags.total_refs 5071928 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1569787 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.230966 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8741120000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 18420.928371 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 254.564671 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 327.558520 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5783.699822 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9967.407270 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17191.318601 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 126.325801 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 133.881896 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2759.726372 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3037.353013 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6393.023977 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.281081 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003884 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004998 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.088252 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.152091 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.262319 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001928 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.002043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.046346 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.097550 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.982602 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 14050 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 200 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 45654 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 147 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 696 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 13662 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1737 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4894 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 38831 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.221329 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_blocks::1024 46146 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 182 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1105 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 12755 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::0 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1911 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4647 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 39226 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.214386 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.696625 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 65568567 # Number of tag accesses -system.l2c.tags.data_accesses 65568567 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6731 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4742 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 690690 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 361152 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 521850 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6817 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4499 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 759258 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 428313 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 530462 # number of ReadReq hits -system.l2c.ReadReq_hits::total 3314514 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2491671 # number of Writeback hits -system.l2c.Writeback_hits::total 2491671 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 125819 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 140505 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 266324 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 29765 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 32403 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 62168 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5875 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6386 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12261 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56397 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53337 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109734 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6731 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4742 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 690690 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 417549 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 521850 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6817 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4499 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 759258 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 481650 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 530462 # number of demand (read+write) hits -system.l2c.demand_hits::total 3424248 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6731 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4742 # number of overall hits -system.l2c.overall_hits::cpu0.inst 690690 # number of overall hits -system.l2c.overall_hits::cpu0.data 417549 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 521850 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6817 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4499 # number of overall hits -system.l2c.overall_hits::cpu1.inst 759258 # number of overall hits -system.l2c.overall_hits::cpu1.data 481650 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 530462 # number of overall hits -system.l2c.overall_hits::total 3424248 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1664 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1301 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 74535 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 94558 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 274703 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2478 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2309 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 56185 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 106038 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 256515 # number of ReadReq misses -system.l2c.ReadReq_misses::total 870286 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 435530 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 123517 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 559047 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 44959 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 45474 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 90433 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 8261 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 9038 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 17299 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76639 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 55158 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 131797 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1664 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1301 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 74535 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 171197 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 274703 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2478 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2309 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 56185 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 161196 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 256515 # number of demand (read+write) misses -system.l2c.demand_misses::total 1002083 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1664 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1301 # number of overall misses -system.l2c.overall_misses::cpu0.inst 74535 # number of overall misses -system.l2c.overall_misses::cpu0.data 171197 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 274703 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2478 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2309 # number of overall misses -system.l2c.overall_misses::cpu1.inst 56185 # number of overall misses -system.l2c.overall_misses::cpu1.data 161196 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 256515 # number of overall misses -system.l2c.overall_misses::total 1002083 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 138961746 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 111055248 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 5745942443 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 7810089637 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 202393999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 185177500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4301130982 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 8460963468 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 95981532857 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 36612963 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 35758482 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116644.590951 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 97011.980571 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2981,57 +2969,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 969598 # Transaction distribution -system.membus.trans_dist::ReadResp 969598 # Transaction distribution -system.membus.trans_dist::WriteReq 38347 # Transaction distribution -system.membus.trans_dist::WriteResp 38347 # Transaction distribution -system.membus.trans_dist::Writeback 1222910 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 662686 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 662686 # Transaction distribution -system.membus.trans_dist::UpgradeReq 426453 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 285961 # Transaction distribution -system.membus.trans_dist::UpgradeResp 115017 # Transaction distribution -system.membus.trans_dist::ReadExReq 144468 # Transaction distribution -system.membus.trans_dist::ReadExResp 127604 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123068 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 988965 # Transaction distribution +system.membus.trans_dist::ReadResp 988965 # Transaction distribution +system.membus.trans_dist::WriteReq 38599 # Transaction distribution +system.membus.trans_dist::WriteResp 38599 # Transaction distribution +system.membus.trans_dist::Writeback 1235035 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 669572 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 669572 # Transaction distribution +system.membus.trans_dist::UpgradeReq 443245 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 300309 # Transaction distribution +system.membus.trans_dist::UpgradeResp 118634 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution +system.membus.trans_dist::ReadExReq 147271 # Transaction distribution +system.membus.trans_dist::ReadExResp 130046 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122720 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5176712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5324942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335765 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335765 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5660707 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156198 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26568 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5280771 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5430111 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335842 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335842 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5765953 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155850 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50220 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174186440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 174394182 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14086976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14086976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 188481158 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 617229 # Total snoops (count) -system.membus.snoop_fanout::samples 3621307 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 176778952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 176989262 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14092480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14092480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191081742 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 645066 # Total snoops (count) +system.membus.snoop_fanout::samples 3693594 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3621307 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3693594 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3621307 # Request fanout histogram -system.membus.reqLayer0.occupancy 109998990 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3693594 # Request fanout histogram +system.membus.reqLayer0.occupancy 110078000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 34484 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20906994 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22086998 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 18632739306 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 11288947920 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10660858032 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6557942197 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187340770 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151922124 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3075,45 +3064,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 5129422 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5122206 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38347 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38347 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2491671 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 932101 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 825371 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 481339 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 298222 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 779561 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298688 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298688 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8006212 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7112719 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15118931 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267664595 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231600691 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 499265286 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1616950 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9541409 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012122 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.109429 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5164890 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5157651 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38599 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38599 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2504876 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 938982 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 832112 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 498168 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 313155 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 811323 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 114 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 303337 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 303337 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8953428 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6273029 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15226457 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 302864374 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 197929240 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 500793614 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1680481 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9632863 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012020 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.108976 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9425751 98.79% 98.79% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115658 1.21% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9517074 98.80% 98.80% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115789 1.20% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9541409 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 18624671874 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9632863 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8806822228 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7692000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2518500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 12569931680 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5125474266 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 12640622488 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4045471741 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |