stats: changes due to recent changesets.

1 files changed, 713 insertions, 541 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
index 3b8bb2577..f7aa432dd 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
@@ -4,22 +4,24 @@ sim_seconds                                 47.355615                       # Nu
 sim_ticks                                47355615197500                       # Number of ticks simulated
 final_tick                               47355615197500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 178863                       # Simulator instruction rate (inst/s)
-host_op_rate                                   210359                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9462962325                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 759628                       # Number of bytes of host memory used
-host_seconds                                  5004.31                       # Real time elapsed on the host
+host_inst_rate                                 119180                       # Simulator instruction rate (inst/s)
+host_op_rate                                   140167                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6305360463                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 747912                       # Number of bytes of host memory used
+host_seconds                                  7510.37                       # Real time elapsed on the host
 sim_insts                                   895084962                       # Number of instructions simulated
 sim_ops                                    1052703090                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker       106496                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker        83264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst         18925144                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          8104128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         10821016                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.l2cache.prefetcher     17557952                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker       158592                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker       147776                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst         13767904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3589696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         10178208                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.l2cache.prefetcher     16399360                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide        427968                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             67574456                       # Number of bytes read from this memory
@@ -27,30 +29,34 @@ system.physmem.bytes_inst_read::cpu0.inst      8104128                       # N
 system.physmem.bytes_inst_read::cpu1.inst      3589696                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total        11693824                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks     78266240                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.inst         20812                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.inst             4                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         20812                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          78287056                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker         1664                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker         1301                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            295727                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            126627                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            169100                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.l2cache.prefetcher       274343                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker         2478                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker         2309                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst            215138                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             56089                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            159049                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.l2cache.prefetcher       256240                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide           6687                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total               1055887                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks         1222910                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.inst             2602                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.inst                1                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             2602                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1225513                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker          2249                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker          1758                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              399639                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              171133                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              228505                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.l2cache.prefetcher       370768                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker          3349                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker          3121                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              290734                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               75803                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              214931                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.l2cache.prefetcher       346302                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide             9037                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::total                 1426958                       # Total read bandwidth from this memory (bytes/s)
@@ -58,17 +64,19 @@ system.physmem.bw_inst_read::cpu0.inst         171133                       # In
 system.physmem.bw_inst_read::cpu1.inst          75803                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total             246936                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::writebacks           1652734                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.inst                439                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.inst                  0                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                439                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total                1653174                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::writebacks           1652734                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker         2249                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker         1758                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             400078                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             171133                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             228945                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.l2cache.prefetcher       370768                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker         3349                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker         3121                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             290734                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              75803                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             214931                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.l2cache.prefetcher       346302                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide            9037                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                3080131                       # Total bandwidth to/from this memory (bytes/s)
@@ -354,23 +362,31 @@ system.physmem_1.memoryStateTime::REF    1581308040000                       # T
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT    234336016748                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.bytes_read::cpu0.inst          740                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst          584                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst          576                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total          1324                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst          704                       # Number of instructions bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu1.inst          576                       # Number of instructions bytes read from this memory
 system.realview.nvmem.bytes_inst_read::total         1280                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst           16                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst           10                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.inst           11                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::total             26                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           16                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.inst           15                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu1.inst           12                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::total               28                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu0.inst           15                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu1.inst           12                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::total           27                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           16                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           15                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           12                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              28                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
@@ -588,8 +604,8 @@ system.cpu0.dcache.tags.total_refs          150576282                       # To
 system.cpu0.dcache.tags.sampled_refs          5387564                       # Sample count of references to valid blocks.
 system.cpu0.dcache.tags.avg_refs            27.948862                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       4951668000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.inst   501.034252                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.978583                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   501.034252                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.978583                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.978583                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
@@ -598,93 +614,93 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2           39
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu0.dcache.tags.tag_accesses        320066517                       # Number of tag accesses
 system.cpu0.dcache.tags.data_accesses       320066517                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.inst     77114778                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu0.data     77114778                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total       77114778                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.inst     69351990                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     69351990                       # number of WriteReq hits
 system.cpu0.dcache.WriteReq_hits::total      69351990                       # number of WriteReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst       251432                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       251432                       # number of WriteInvalidateReq hits
 system.cpu0.dcache.WriteInvalidateReq_hits::total       251432                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst      1745310                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1745310                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::total      1745310                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.inst      1668274                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1668274                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total      1668274                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.inst    146466768                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu0.data    146466768                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_hits::total       146466768                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.inst    146466768                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu0.data    146466768                       # number of overall hits
 system.cpu0.dcache.overall_hits::total      146466768                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.inst      3852692                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3852692                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total      3852692                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.inst      2255601                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      2255601                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::total      2255601                       # number of WriteReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst       766100                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       766100                       # number of WriteInvalidateReq misses
 system.cpu0.dcache.WriteInvalidateReq_misses::total       766100                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst       104059                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       104059                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total       104059                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.inst       180014                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       180014                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total       180014                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.inst      6108293                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu0.data      6108293                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::total       6108293                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.inst      6108293                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu0.data      6108293                       # number of overall misses
 system.cpu0.dcache.overall_misses::total      6108293                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst  54452724607                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  54452724607                       # number of ReadReq miss cycles
 system.cpu0.dcache.ReadReq_miss_latency::total  54452724607                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst  41906959422                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  41906959422                       # number of WriteReq miss cycles
 system.cpu0.dcache.WriteReq_miss_latency::total  41906959422                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst  27296991314                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  27296991314                       # number of WriteInvalidateReq miss cycles
 system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  27296991314                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst   1502404735                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   1502404735                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.LoadLockedReq_miss_latency::total   1502404735                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst   3769027814                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3769027814                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total   3769027814                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst      2840500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2840500                       # number of StoreCondFailReq miss cycles
 system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2840500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.inst  96359684029                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  96359684029                       # number of demand (read+write) miss cycles
 system.cpu0.dcache.demand_miss_latency::total  96359684029                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.inst  96359684029                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  96359684029                       # number of overall miss cycles
 system.cpu0.dcache.overall_miss_latency::total  96359684029                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.inst     80967470                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     80967470                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total     80967470                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.inst     71607591                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     71607591                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::total     71607591                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst      1017532                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1017532                       # number of WriteInvalidateReq accesses(hits+misses)
 system.cpu0.dcache.WriteInvalidateReq_accesses::total      1017532                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst      1849369                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1849369                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total      1849369                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst      1848288                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1848288                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total      1848288                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.inst    152575061                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data    152575061                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_accesses::total    152575061                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.inst    152575061                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    152575061                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total    152575061                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.047583                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.047583                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.047583                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.031499                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.031499                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::total     0.031499                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst     0.752900                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.752900                       # miss rate for WriteInvalidateReq accesses
 system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.752900                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.056267                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056267                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056267                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.097395                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.097395                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.097395                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.040035                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.040035                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     0.040035                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.040035                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.040035                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::total     0.040035                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14133.682269                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14133.682269                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::total 14133.682269                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 18579.065811                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18579.065811                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::total 18579.065811                       # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 35631.107315                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 35631.107315                       # average WriteInvalidateReq miss latency
 system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 35631.107315                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 14438.008582                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14438.008582                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14438.008582                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20937.414946                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20937.414946                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20937.414946                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 15775.222968                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15775.222968                       # average overall miss latency
 system.cpu0.dcache.demand_avg_miss_latency::total 15775.222968                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 15775.222968                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15775.222968                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::total 15775.222968                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -696,91 +712,91 @@ system.cpu0.dcache.fast_writes                      0                       # nu
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks      3733142                       # number of writebacks
 system.cpu0.dcache.writebacks::total          3733142                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst       361487                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       361487                       # number of ReadReq MSHR hits
 system.cpu0.dcache.ReadReq_mshr_hits::total       361487                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       935411                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       935411                       # number of WriteReq MSHR hits
 system.cpu0.dcache.WriteReq_mshr_hits::total       935411                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst          100                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data          100                       # number of WriteInvalidateReq MSHR hits
 system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total          100                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst           34                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data           34                       # number of LoadLockedReq MSHR hits
 system.cpu0.dcache.LoadLockedReq_mshr_hits::total           34                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst           67                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           67                       # number of StoreCondReq MSHR hits
 system.cpu0.dcache.StoreCondReq_mshr_hits::total           67                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.inst      1296898                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1296898                       # number of demand (read+write) MSHR hits
 system.cpu0.dcache.demand_mshr_hits::total      1296898                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.inst      1296898                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1296898                       # number of overall MSHR hits
 system.cpu0.dcache.overall_mshr_hits::total      1296898                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst      3491205                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3491205                       # number of ReadReq MSHR misses
 system.cpu0.dcache.ReadReq_mshr_misses::total      3491205                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst      1320190                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1320190                       # number of WriteReq MSHR misses
 system.cpu0.dcache.WriteReq_mshr_misses::total      1320190                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.inst       766000                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       766000                       # number of WriteInvalidateReq MSHR misses
 system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       766000                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst       104025                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       104025                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.LoadLockedReq_mshr_misses::total       104025                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst       179947                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       179947                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total       179947                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.inst      4811395                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4811395                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.demand_mshr_misses::total      4811395                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.inst      4811395                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4811395                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_misses::total      4811395                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst  42113152704                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  42113152704                       # number of ReadReq MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_miss_latency::total  42113152704                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst  22270249828                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  22270249828                       # number of WriteReq MSHR miss cycles
 system.cpu0.dcache.WriteReq_mshr_miss_latency::total  22270249828                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst  25755951436                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  25755951436                       # number of WriteInvalidateReq MSHR miss cycles
 system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  25755951436                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst   1293404753                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1293404753                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1293404753                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst   3399276642                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3399276642                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3399276642                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst      2291500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2291500                       # number of StoreCondFailReq MSHR miss cycles
 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2291500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst  64383402532                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  64383402532                       # number of demand (read+write) MSHR miss cycles
 system.cpu0.dcache.demand_mshr_miss_latency::total  64383402532                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst  64383402532                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  64383402532                       # number of overall MSHR miss cycles
 system.cpu0.dcache.overall_mshr_miss_latency::total  64383402532                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5824362996                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5824362996                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5824362996                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   5586865743                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5586865743                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5586865743                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst  11411228739                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11411228739                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11411228739                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.043119                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.043119                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.043119                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.018436                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018436                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018436                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst     0.752802                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.752802                       # mshr miss rate for WriteInvalidateReq accesses
 system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.752802                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.056249                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056249                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056249                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.097359                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.097359                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.097359                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.031535                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.031535                       # mshr miss rate for demand accesses
 system.cpu0.dcache.demand_mshr_miss_rate::total     0.031535                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.031535                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031535                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::total     0.031535                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12062.641038                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12062.641038                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12062.641038                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 16868.973275                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16868.973275                       # average WriteReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16868.973275                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 33623.957488                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33623.957488                       # average WriteInvalidateReq mshr miss latency
 system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 33623.957488                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 12433.595318                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12433.595318                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12433.595318                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18890.432416                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18890.432416                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18890.432416                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 13381.441875                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13381.441875                       # average overall mshr miss latency
 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13381.441875                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 13381.441875                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13381.441875                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13381.441875                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements          9463678                       # number of replacements
@@ -891,12 +907,14 @@ system.cpu0.l2cache.tags.warmup_cycle      5578143500                       # Cy
 system.cpu0.l2cache.tags.occ_blocks::writebacks  4129.920995                       # Average occupied blocks per requestor
 system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    42.114006                       # Average occupied blocks per requestor
 system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    24.266127                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  9438.642805                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  6921.151423                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  2517.491382                       # Average occupied blocks per requestor
 system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  2562.596205                       # Average occupied blocks per requestor
 system.cpu0.l2cache.tags.occ_percent::writebacks     0.252070                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002570                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001481                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.576089                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.422434                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.153655                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.156408                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_percent::total     0.988619                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_task_id_blocks::1022         2519                       # Occupied blocks per task id
@@ -922,137 +940,155 @@ system.cpu0.l2cache.tags.tag_accesses       319708402                       # Nu
 system.cpu0.l2cache.tags.data_accesses      319708402                       # Number of data accesses
 system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       463342                       # number of ReadReq hits
 system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       138212                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst     11610557                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.inst      8698965                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.data      2911592                       # number of ReadReq hits
 system.cpu0.l2cache.ReadReq_hits::total      12212111                       # number of ReadReq hits
 system.cpu0.l2cache.Writeback_hits::writebacks      3733141                       # number of Writeback hits
 system.cpu0.l2cache.Writeback_hits::total      3733141                       # number of Writeback hits
-system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.inst       193768                       # number of WriteInvalidateReq hits
+system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data       193768                       # number of WriteInvalidateReq hits
 system.cpu0.l2cache.WriteInvalidateReq_hits::total       193768                       # number of WriteInvalidateReq hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst        68627                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        68627                       # number of UpgradeReq hits
 system.cpu0.l2cache.UpgradeReq_hits::total        68627                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst        33597                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        33597                       # number of SCUpgradeReq hits
 system.cpu0.l2cache.SCUpgradeReq_hits::total        33597                       # number of SCUpgradeReq hits
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-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33325.580959                       # average overall miss latency
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 system.cpu0.l2cache.demand_avg_miss_latency::total 33321.968286                       # average overall miss latency
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-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33325.580959                       # average overall miss latency
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 system.cpu0.l2cache.overall_avg_miss_latency::total 33321.968286                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs           82                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -1065,129 +1101,148 @@ system.cpu0.l2cache.cache_copies                    0                       # nu
 system.cpu0.l2cache.writebacks::writebacks      1399370                       # number of writebacks
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 system.cpu0.l2cache.ReadReq_mshr_hits::total         3404                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.inst          156                       # number of WriteInvalidateReq MSHR hits
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 system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total          156                       # number of WriteInvalidateReq MSHR hits
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-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst        13061                       # number of demand (read+write) MSHR hits
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 system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher      1036981                       # number of HardPFReq MSHR misses
 system.cpu0.l2cache.HardPFReq_mshr_misses::total      1036981                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.inst       570601                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data       570601                       # number of WriteInvalidateReq MSHR misses
 system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total       570601                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst       126856                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       126856                       # number of UpgradeReq MSHR misses
 system.cpu0.l2cache.UpgradeReq_mshr_misses::total       126856                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst       146340                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       146340                       # number of SCUpgradeReq MSHR misses
 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       146340                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst           10                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           10                       # number of SCUpgradeFailReq MSHR misses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           10                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst       261018                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       261018                       # number of ReadExReq MSHR misses
 system.cpu0.l2cache.ReadExReq_mshr_misses::total       261018                       # number of ReadExReq MSHR misses
 system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        11843                       # number of demand (read+write) MSHR misses
 system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8237                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst      1706228                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       765226                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       941002                       # number of demand (read+write) MSHR misses
 system.cpu0.l2cache.demand_mshr_misses::total      1726308                       # number of demand (read+write) MSHR misses
 system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        11843                       # number of overall MSHR misses
 system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8237                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst      1706228                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       765226                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       941002                       # number of overall MSHR misses
 system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher      1036981                       # number of overall MSHR misses
 system.cpu0.l2cache.overall_mshr_misses::total      2763289                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    299835249                       # number of ReadReq MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    221721501                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst  34355781249                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst  17303340727                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data  17052440522                       # number of ReadReq MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  34877337999                       # number of ReadReq MSHR miss cycles
 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  47311809533                       # number of HardPFReq MSHR miss cycles
 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  47311809533                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst  20034543782                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  20034543782                       # number of WriteInvalidateReq MSHR miss cycles
 system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  20034543782                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst   2151275072                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2151275072                       # number of UpgradeReq MSHR miss cycles
 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2151275072                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst   1993779824                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   1993779824                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   1993779824                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst      1835000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1835000                       # number of SCUpgradeFailReq MSHR miss cycles
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1835000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst   9532664011                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   9532664011                       # number of ReadExReq MSHR miss cycles
 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   9532664011                       # number of ReadExReq MSHR miss cycles
 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    299835249                       # number of demand (read+write) MSHR miss cycles
 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    221721501                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  43888445260                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17303340727                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  26585104533                       # number of demand (read+write) MSHR miss cycles
 system.cpu0.l2cache.demand_mshr_miss_latency::total  44410002010                       # number of demand (read+write) MSHR miss cycles
 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    299835249                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    221721501                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  43888445260                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17303340727                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  26585104533                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  47311809533                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.overall_mshr_miss_latency::total  91721811543                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   9672004742                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4113621500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5558383242                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   9672004742                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst   5338553005                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5338553005                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5338553005                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst  15010557747                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4113621500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10896936247                       # number of overall MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  15010557747                       # number of overall MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.024923                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.056244                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.110666                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.080855                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.189149                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.107106                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst     0.746347                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.746347                       # mshr miss rate for WriteInvalidateReq accesses
 system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.746347                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst     0.648936                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.648936                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.648936                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.813285                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.813285                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.813285                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst     0.231718                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.231718                       # mshr miss rate for ReadExReq accesses
 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.231718                       # mshr miss rate for ReadExReq accesses
 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.024923                       # mshr miss rate for demand accesses
 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.056244                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.120279                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.080855                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.199305                       # mshr miss rate for demand accesses
 system.cpu0.l2cache.demand_mshr_miss_rate::total     0.116585                       # mshr miss rate for demand accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.024923                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.056244                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.120279                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.080855                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.199305                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::total     0.186617                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148                       # average ReadReq mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23772.172383                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22612.065882                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25077.708478                       # average ReadReq mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23802.344928                       # average ReadReq mshr miss latency
 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406                       # average HardPFReq mshr miss latency
 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45624.567406                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 35111.301561                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 35111.301561                       # average WriteInvalidateReq mshr miss latency
 system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 35111.301561                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16958.402220                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16958.402220                       # average UpgradeReq mshr miss latency
 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16958.402220                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13624.298374                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13624.298374                       # average SCUpgradeReq mshr miss latency
 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13624.298374                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst       183500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       183500                       # average SCUpgradeFailReq mshr miss latency
 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       183500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 36521.098204                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36521.098204                       # average ReadExReq mshr miss latency
 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36521.098204                       # average ReadExReq mshr miss latency
 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148                       # average overall mshr miss latency
 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25722.497380                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22612.065882                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28251.910764                       # average overall mshr miss latency
 system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25725.422121                       # average overall mshr miss latency
 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148                       # average overall mshr miss latency
 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25722.497380                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22612.065882                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28251.910764                       # average overall mshr miss latency
 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406                       # average overall mshr miss latency
 system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33192.985440                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
 system.cpu0.toL2Bus.trans_dist::ReadReq      16482247                       # Transaction distribution
@@ -1441,8 +1496,8 @@ system.cpu1.dcache.tags.total_refs          161270449                       # To
 system.cpu1.dcache.tags.sampled_refs          5624987                       # Sample count of references to valid blocks.
 system.cpu1.dcache.tags.avg_refs            28.670368                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle     8377201144000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.inst   426.107402                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.832241                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   426.107402                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.832241                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_percent::total     0.832241                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
@@ -1451,93 +1506,93 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::2          209
 system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
 system.cpu1.dcache.tags.tag_accesses        342291215                       # Number of tag accesses
 system.cpu1.dcache.tags.data_accesses       342291215                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.inst     83489779                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::cpu1.data     83489779                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total       83489779                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.inst     73474609                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     73474609                       # number of WriteReq hits
 system.cpu1.dcache.WriteReq_hits::total      73474609                       # number of WriteReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst        71990                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data        71990                       # number of WriteInvalidateReq hits
 system.cpu1.dcache.WriteInvalidateReq_hits::total        71990                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst      1908367                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1908367                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_hits::total      1908367                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.inst      1854336                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1854336                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total      1854336                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.inst    156964388                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::cpu1.data    156964388                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_hits::total       156964388                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.inst    156964388                       # number of overall hits
+system.cpu1.dcache.overall_hits::cpu1.data    156964388                       # number of overall hits
 system.cpu1.dcache.overall_hits::total      156964388                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.inst      4311289                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::cpu1.data      4311289                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_misses::total      4311289                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.inst      2366929                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      2366929                       # number of WriteReq misses
 system.cpu1.dcache.WriteReq_misses::total      2366929                       # number of WriteReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst       476593                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       476593                       # number of WriteInvalidateReq misses
 system.cpu1.dcache.WriteInvalidateReq_misses::total       476593                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst       141331                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       141331                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total       141331                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.inst       193852                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       193852                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_misses::total       193852                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.inst      6678218                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::cpu1.data      6678218                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_misses::total       6678218                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.inst      6678218                       # number of overall misses
+system.cpu1.dcache.overall_misses::cpu1.data      6678218                       # number of overall misses
 system.cpu1.dcache.overall_misses::total      6678218                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst  60722587231                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  60722587231                       # number of ReadReq miss cycles
 system.cpu1.dcache.ReadReq_miss_latency::total  60722587231                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst  38093191666                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  38093191666                       # number of WriteReq miss cycles
 system.cpu1.dcache.WriteReq_miss_latency::total  38093191666                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst  11613108236                       # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data  11613108236                       # number of WriteInvalidateReq miss cycles
 system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  11613108236                       # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst   1977833980                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   1977833980                       # number of LoadLockedReq miss cycles
 system.cpu1.dcache.LoadLockedReq_miss_latency::total   1977833980                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst   3982712056                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3982712056                       # number of StoreCondReq miss cycles
 system.cpu1.dcache.StoreCondReq_miss_latency::total   3982712056                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst      2357000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2357000                       # number of StoreCondFailReq miss cycles
 system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2357000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.inst  98815778897                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  98815778897                       # number of demand (read+write) miss cycles
 system.cpu1.dcache.demand_miss_latency::total  98815778897                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.inst  98815778897                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  98815778897                       # number of overall miss cycles
 system.cpu1.dcache.overall_miss_latency::total  98815778897                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.inst     87801068                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     87801068                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total     87801068                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.inst     75841538                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     75841538                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::total     75841538                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst       548583                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       548583                       # number of WriteInvalidateReq accesses(hits+misses)
 system.cpu1.dcache.WriteInvalidateReq_accesses::total       548583                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst      2049698                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2049698                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total      2049698                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst      2048188                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2048188                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total      2048188                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.inst    163642606                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data    163642606                       # number of demand (read+write) accesses
 system.cpu1.dcache.demand_accesses::total    163642606                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.inst    163642606                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    163642606                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total    163642606                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.049103                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049103                       # miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_miss_rate::total     0.049103                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.031209                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.031209                       # miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::total     0.031209                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst     0.868771                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.868771                       # miss rate for WriteInvalidateReq accesses
 system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.868771                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.068952                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.068952                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.068952                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.094646                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.094646                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::total     0.094646                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.040810                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.040810                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::total     0.040810                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.040810                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.040810                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::total     0.040810                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14084.555044                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14084.555044                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_miss_latency::total 14084.555044                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 16093.930856                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16093.930856                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::total 16093.930856                       # average WriteReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 24366.929930                       # average WriteInvalidateReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 24366.929930                       # average WriteInvalidateReq miss latency
 system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 24366.929930                       # average WriteInvalidateReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13994.339388                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13994.339388                       # average LoadLockedReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13994.339388                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20545.117182                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20545.117182                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20545.117182                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14796.728543                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14796.728543                       # average overall miss latency
 system.cpu1.dcache.demand_avg_miss_latency::total 14796.728543                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14796.728543                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14796.728543                       # average overall miss latency
 system.cpu1.dcache.overall_avg_miss_latency::total 14796.728543                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -1549,91 +1604,91 @@ system.cpu1.dcache.fast_writes                      0                       # nu
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks      3711348                       # number of writebacks
 system.cpu1.dcache.writebacks::total          3711348                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst       397792                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       397792                       # number of ReadReq MSHR hits
 system.cpu1.dcache.ReadReq_mshr_hits::total       397792                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst       970938                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       970938                       # number of WriteReq MSHR hits
 system.cpu1.dcache.WriteReq_mshr_hits::total       970938                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst           60                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data           60                       # number of WriteInvalidateReq MSHR hits
 system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total           60                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst           47                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data           47                       # number of LoadLockedReq MSHR hits
 system.cpu1.dcache.LoadLockedReq_mshr_hits::total           47                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst           68                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           68                       # number of StoreCondReq MSHR hits
 system.cpu1.dcache.StoreCondReq_mshr_hits::total           68                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.inst      1368730                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1368730                       # number of demand (read+write) MSHR hits
 system.cpu1.dcache.demand_mshr_hits::total      1368730                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.inst      1368730                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1368730                       # number of overall MSHR hits
 system.cpu1.dcache.overall_mshr_hits::total      1368730                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst      3913497                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3913497                       # number of ReadReq MSHR misses
 system.cpu1.dcache.ReadReq_mshr_misses::total      3913497                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst      1395991                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1395991                       # number of WriteReq MSHR misses
 system.cpu1.dcache.WriteReq_mshr_misses::total      1395991                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.inst       476533                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       476533                       # number of WriteInvalidateReq MSHR misses
 system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       476533                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst       141284                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       141284                       # number of LoadLockedReq MSHR misses
 system.cpu1.dcache.LoadLockedReq_mshr_misses::total       141284                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst       193784                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       193784                       # number of StoreCondReq MSHR misses
 system.cpu1.dcache.StoreCondReq_mshr_misses::total       193784                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.inst      5309488                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      5309488                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.demand_mshr_misses::total      5309488                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.inst      5309488                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5309488                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_misses::total      5309488                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst  46779736993                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  46779736993                       # number of ReadReq MSHR miss cycles
 system.cpu1.dcache.ReadReq_mshr_miss_latency::total  46779736993                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst  20386885918                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  20386885918                       # number of WriteReq MSHR miss cycles
 system.cpu1.dcache.WriteReq_mshr_miss_latency::total  20386885918                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst  10653380764                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  10653380764                       # number of WriteInvalidateReq MSHR miss cycles
 system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  10653380764                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst   1693632498                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1693632498                       # number of LoadLockedReq MSHR miss cycles
 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1693632498                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst   3584420895                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3584420895                       # number of StoreCondReq MSHR miss cycles
 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3584420895                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst      1830000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1830000                       # number of StoreCondFailReq MSHR miss cycles
 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1830000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst  67166622911                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  67166622911                       # number of demand (read+write) MSHR miss cycles
 system.cpu1.dcache.demand_mshr_miss_latency::total  67166622911                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst  67166622911                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  67166622911                       # number of overall MSHR miss cycles
 system.cpu1.dcache.overall_mshr_miss_latency::total  67166622911                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst    548139751                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    548139751                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    548139751                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst    613571252                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    613571252                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    613571252                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst   1161711003                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1161711003                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1161711003                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.044572                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.044572                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.044572                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.018407                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018407                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018407                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst     0.868662                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.868662                       # mshr miss rate for WriteInvalidateReq accesses
 system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.868662                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.068929                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.068929                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.068929                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.094612                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.094612                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.094612                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.032446                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032446                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_miss_rate::total     0.032446                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.032446                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032446                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::total     0.032446                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11953.436273                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11953.436273                       # average ReadReq mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11953.436273                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14603.880625                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14603.880625                       # average WriteReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14603.880625                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 22356.018920                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22356.018920                       # average WriteInvalidateReq mshr miss latency
 system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22356.018920                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11987.433099                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11987.433099                       # average LoadLockedReq mshr miss latency
 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11987.433099                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18496.990954                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18496.990954                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18496.990954                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12650.301293                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12650.301293                       # average overall mshr miss latency
 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12650.301293                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12650.301293                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12650.301293                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12650.301293                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements          9215030                       # number of replacements
@@ -1744,12 +1799,14 @@ system.cpu1.l2cache.tags.warmup_cycle    9611078525000                       # C
 system.cpu1.l2cache.tags.occ_blocks::writebacks  5526.220513                       # Average occupied blocks per requestor
 system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    77.627317                       # Average occupied blocks per requestor
 system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    76.256480                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  6438.113983                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3620.154380                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2817.959604                       # Average occupied blocks per requestor
 system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1415.441924                       # Average occupied blocks per requestor
 system.cpu1.l2cache.tags.occ_percent::writebacks     0.337294                       # Average percentage of cache occupancy
 system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004738                       # Average percentage of cache occupancy
 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004654                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.392951                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.220957                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.171995                       # Average percentage of cache occupancy
 system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.086392                       # Average percentage of cache occupancy
 system.cpu1.l2cache.tags.occ_percent::total     0.826029                       # Average percentage of cache occupancy
 system.cpu1.l2cache.tags.occ_task_id_blocks::1022         2491                       # Occupied blocks per task id
@@ -1776,141 +1833,159 @@ system.cpu1.l2cache.tags.tag_accesses       321109712                       # Nu
 system.cpu1.l2cache.tags.data_accesses      321109712                       # Number of data accesses
 system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       544517                       # number of ReadReq hits
 system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       158528                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst     11678610                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.inst      8400098                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.data      3278512                       # number of ReadReq hits
 system.cpu1.l2cache.ReadReq_hits::total      12381655                       # number of ReadReq hits
 system.cpu1.l2cache.Writeback_hits::writebacks      3711345                       # number of Writeback hits
 system.cpu1.l2cache.Writeback_hits::total      3711345                       # number of Writeback hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.inst       202419                       # number of WriteInvalidateReq hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       202419                       # number of WriteInvalidateReq hits
 system.cpu1.l2cache.WriteInvalidateReq_hits::total       202419                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst        77280                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        77280                       # number of UpgradeReq hits
 system.cpu1.l2cache.UpgradeReq_hits::total        77280                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst        41809                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        41809                       # number of SCUpgradeReq hits
 system.cpu1.l2cache.SCUpgradeReq_hits::total        41809                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.inst       939119                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       939119                       # number of ReadExReq hits
 system.cpu1.l2cache.ReadExReq_hits::total       939119                       # number of ReadExReq hits
 system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       544517                       # number of demand (read+write) hits
 system.cpu1.l2cache.demand_hits::cpu1.itb.walker       158528                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst     12617729                       # number of demand (read+write) hits
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 system.cpu1.l2cache.demand_hits::total       13320774                       # number of demand (read+write) hits
 system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       544517                       # number of overall hits
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-system.cpu1.l2cache.overall_hits::cpu1.inst     12617729                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      8400098                       # number of overall hits
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 system.cpu1.l2cache.overall_hits::total      13320774                       # number of overall hits
 system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12561                       # number of ReadReq misses
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-system.cpu1.l2cache.ReadReq_misses::cpu1.inst      1591427                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.inst       815444                       # number of ReadReq misses
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 system.cpu1.l2cache.ReadReq_misses::total      1612858                       # number of ReadReq misses
 system.cpu1.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
 system.cpu1.l2cache.Writeback_misses::total            1                       # number of Writeback misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.inst       272843                       # number of WriteInvalidateReq misses
+system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data       272843                       # number of WriteInvalidateReq misses
 system.cpu1.l2cache.WriteInvalidateReq_misses::total       272843                       # number of WriteInvalidateReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst       137034                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       137034                       # number of UpgradeReq misses
 system.cpu1.l2cache.UpgradeReq_misses::total       137034                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst       151974                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       151974                       # number of SCUpgradeReq misses
 system.cpu1.l2cache.SCUpgradeReq_misses::total       151974                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst            1                       # number of SCUpgradeFailReq misses
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 system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.inst       244121                       # number of ReadExReq misses
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 system.cpu1.l2cache.ReadExReq_misses::total       244121                       # number of ReadExReq misses
 system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12561                       # number of demand (read+write) misses
 system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8870                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst      1835548                       # number of demand (read+write) misses
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 system.cpu1.l2cache.demand_misses::total      1856979                       # number of demand (read+write) misses
 system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12561                       # number of overall misses
 system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8870                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst      1835548                       # number of overall misses
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 system.cpu1.l2cache.overall_misses::total      1856979                       # number of overall misses
 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    455863233                       # number of ReadReq miss cycles
 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    358991737                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst  47206598788                       # number of ReadReq miss cycles
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 system.cpu1.l2cache.ReadReq_miss_latency::total  48021453758                       # number of ReadReq miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst    213581444                       # number of WriteInvalidateReq miss cycles
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 system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total    213581444                       # number of WriteInvalidateReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst   2792930491                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2792930491                       # number of UpgradeReq miss cycles
 system.cpu1.l2cache.UpgradeReq_miss_latency::total   2792930491                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst   3071034580                       # number of SCUpgradeReq miss cycles
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 system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3071034580                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst      1783500                       # number of SCUpgradeFailReq miss cycles
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 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1783500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst   9626384839                       # number of ReadExReq miss cycles
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 system.cpu1.l2cache.ReadExReq_miss_latency::total   9626384839                       # number of ReadExReq miss cycles
 system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    455863233                       # number of demand (read+write) miss cycles
 system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    358991737                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  56832983627                       # number of demand (read+write) miss cycles
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 system.cpu1.l2cache.demand_miss_latency::total  57647838597                       # number of demand (read+write) miss cycles
 system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    455863233                       # number of overall miss cycles
 system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    358991737                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  56832983627                       # number of overall miss cycles
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 system.cpu1.l2cache.overall_miss_latency::total  57647838597                       # number of overall miss cycles
 system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       557078                       # number of ReadReq accesses(hits+misses)
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-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst     13270037                       # number of ReadReq accesses(hits+misses)
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 system.cpu1.l2cache.ReadReq_accesses::total     13994513                       # number of ReadReq accesses(hits+misses)
 system.cpu1.l2cache.Writeback_accesses::writebacks      3711346                       # number of Writeback accesses(hits+misses)
 system.cpu1.l2cache.Writeback_accesses::total      3711346                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst       475262                       # number of WriteInvalidateReq accesses(hits+misses)
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 system.cpu1.l2cache.WriteInvalidateReq_accesses::total       475262                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst       214314                       # number of UpgradeReq accesses(hits+misses)
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 system.cpu1.l2cache.UpgradeReq_accesses::total       214314                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst       193783                       # number of SCUpgradeReq accesses(hits+misses)
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 system.cpu1.l2cache.SCUpgradeReq_accesses::total       193783                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst            1                       # number of SCUpgradeFailReq accesses(hits+misses)
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 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst      1183240                       # number of ReadExReq accesses(hits+misses)
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 system.cpu1.l2cache.ReadExReq_accesses::total      1183240                       # number of ReadExReq accesses(hits+misses)
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-system.cpu1.l2cache.demand_accesses::cpu1.inst     14453277                       # number of demand (read+write) accesses
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 system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       167398                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst     14453277                       # number of overall (read+write) accesses
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 system.cpu1.l2cache.overall_accesses::total     15177753                       # number of overall (read+write) accesses
 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022548                       # miss rate for ReadReq accesses
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-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.119926                       # miss rate for ReadReq accesses
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.191388                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.ReadReq_miss_rate::total     0.115249                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
 system.cpu1.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst     0.574090                       # miss rate for WriteInvalidateReq accesses
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 system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.574090                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst     0.639408                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.639408                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.639408                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst     0.784248                       # miss rate for SCUpgradeReq accesses
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 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.784248                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst            1                       # miss rate for SCUpgradeFailReq accesses
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 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst     0.206316                       # miss rate for ReadExReq accesses
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 system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.052987                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.126999                       # miss rate for demand accesses
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 system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.052987                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.126999                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.088486                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.194761                       # miss rate for overall accesses
 system.cpu1.l2cache.overall_miss_rate::total     0.122349                       # miss rate for overall accesses
 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36291.953905                       # average ReadReq miss latency
 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40472.574634                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29663.062640                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 27683.292523                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 31743.509845                       # average ReadReq miss latency
 system.cpu1.l2cache.ReadReq_avg_miss_latency::total 29774.136197                       # average ReadReq miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.inst   782.799793                       # average WriteInvalidateReq miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data   782.799793                       # average WriteInvalidateReq miss latency
 system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total   782.799793                       # average WriteInvalidateReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 20381.295817                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20381.295817                       # average UpgradeReq miss latency
 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20381.295817                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20207.631437                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20207.631437                       # average SCUpgradeReq miss latency
 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20207.631437                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst      1783500                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1783500                       # average SCUpgradeFailReq miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1783500                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 39432.842070                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39432.842070                       # average ReadExReq miss latency
 system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39432.842070                       # average ReadExReq miss latency
 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36291.953905                       # average overall miss latency
 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40472.574634                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30962.406664                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27683.292523                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33583.643275                       # average overall miss latency
 system.cpu1.l2cache.demand_avg_miss_latency::total 31043.882886                       # average overall miss latency
 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36291.953905                       # average overall miss latency
 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40472.574634                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30962.406664                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27683.292523                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33583.643275                       # average overall miss latency
 system.cpu1.l2cache.overall_avg_miss_latency::total 31043.882886                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -1923,133 +1998,152 @@ system.cpu1.l2cache.cache_copies                    0                       # nu
 system.cpu1.l2cache.writebacks::writebacks      1092301                       # number of writebacks
 system.cpu1.l2cache.writebacks::total         1092301                       # number of writebacks
 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            1                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst         1805                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst            1                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data         1804                       # number of ReadReq MSHR hits
 system.cpu1.l2cache.ReadReq_mshr_hits::total         1806                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.inst           45                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data           45                       # number of WriteInvalidateReq MSHR hits
 system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total           45                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst         7072                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         7072                       # number of ReadExReq MSHR hits
 system.cpu1.l2cache.ReadExReq_mshr_hits::total         7072                       # number of ReadExReq MSHR hits
 system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst         8877                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
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 system.cpu1.l2cache.demand_mshr_hits::total         8878                       # number of demand (read+write) MSHR hits
 system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            1                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst         8877                       # number of overall MSHR hits
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 system.cpu1.l2cache.overall_mshr_hits::total         8878                       # number of overall MSHR hits
 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        12561                       # number of ReadReq MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8869                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst      1589622                       # number of ReadReq MSHR misses
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 system.cpu1.l2cache.ReadReq_mshr_misses::total      1611052                       # number of ReadReq MSHR misses
 system.cpu1.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
 system.cpu1.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
 system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher      1032302                       # number of HardPFReq MSHR misses
 system.cpu1.l2cache.HardPFReq_mshr_misses::total      1032302                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.inst       272798                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data       272798                       # number of WriteInvalidateReq MSHR misses
 system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total       272798                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst       137034                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       137034                       # number of UpgradeReq MSHR misses
 system.cpu1.l2cache.UpgradeReq_mshr_misses::total       137034                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst       151974                       # number of SCUpgradeReq MSHR misses
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 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       151974                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst            1                       # number of SCUpgradeFailReq MSHR misses
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 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst       237049                       # number of ReadExReq MSHR misses
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 system.cpu1.l2cache.ReadExReq_mshr_misses::total       237049                       # number of ReadExReq MSHR misses
 system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        12561                       # number of demand (read+write) MSHR misses
 system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8869                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst      1826671                       # number of demand (read+write) MSHR misses
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 system.cpu1.l2cache.demand_mshr_misses::total      1848101                       # number of demand (read+write) MSHR misses
 system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        12561                       # number of overall MSHR misses
 system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8869                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst      1826671                       # number of overall MSHR misses
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 system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher      1032302                       # number of overall MSHR misses
 system.cpu1.l2cache.overall_mshr_misses::total      2880403                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    367223255                       # number of ReadReq MSHR miss cycles
 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    296231251                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst  35897455818                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst  16845762712                       # number of ReadReq MSHR miss cycles
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 system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  36560910324                       # number of ReadReq MSHR miss cycles
 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  41289088164                       # number of HardPFReq MSHR miss cycles
 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  41289088164                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst   7103244766                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   7103244766                       # number of WriteInvalidateReq MSHR miss cycles
 system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total   7103244766                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst   2312644672                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2312644672                       # number of UpgradeReq MSHR miss cycles
 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2312644672                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst   2076231085                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2076231085                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2076231085                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst      1461500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1461500                       # number of SCUpgradeFailReq MSHR miss cycles
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1461500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst   7288633813                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7288633813                       # number of ReadExReq MSHR miss cycles
 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7288633813                       # number of ReadExReq MSHR miss cycles
 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    367223255                       # number of demand (read+write) MSHR miss cycles
 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    296231251                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  43186089631                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  16845762712                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  26340326919                       # number of demand (read+write) MSHR miss cycles
 system.cpu1.l2cache.demand_mshr_miss_latency::total  43849544137                       # number of demand (read+write) MSHR miss cycles
 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    367223255                       # number of overall MSHR miss cycles
 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    296231251                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  43186089631                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  16845762712                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  26340326919                       # number of overall MSHR miss cycles
 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  41289088164                       # number of overall MSHR miss cycles
 system.cpu1.l2cache.overall_mshr_miss_latency::total  85138632301                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst    514241998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7364250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    506877748                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    514241998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst    574249999                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    574249999                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    574249999                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst   1088491997                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7364250                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1081127747                       # number of overall MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1088491997                       # number of overall MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022548                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.052982                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.119790                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.088486                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.190943                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.115120                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
 system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst     0.573995                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.573995                       # mshr miss rate for WriteInvalidateReq accesses
 system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.573995                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst     0.639408                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.639408                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.639408                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.784248                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.784248                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.784248                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst     0.200339                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.200339                       # mshr miss rate for ReadExReq accesses
 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.200339                       # mshr miss rate for ReadExReq accesses
 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022548                       # mshr miss rate for demand accesses
 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.052982                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.126385                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.088486                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.193066                       # mshr miss rate for demand accesses
 system.cpu1.l2cache.demand_mshr_miss_rate::total     0.121764                       # mshr miss rate for demand accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022548                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.052982                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.126385                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.088486                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.193066                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::total     0.189778                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660                       # average ReadReq mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22582.384880                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20658.418445                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24608.899371                       # average ReadReq mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22693.811450                       # average ReadReq mshr miss latency
 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782                       # average HardPFReq mshr miss latency
 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39997.101782                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 26038.478163                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26038.478163                       # average WriteInvalidateReq mshr miss latency
 system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 26038.478163                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16876.429733                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16876.429733                       # average UpgradeReq mshr miss latency
 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16876.429733                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13661.751912                       # average SCUpgradeReq mshr miss latency
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 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13661.751912                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst      1461500                       # average SCUpgradeFailReq mshr miss latency
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 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30747.372117                       # average ReadExReq mshr miss latency
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-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23641.963786                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20658.418445                       # average overall mshr miss latency
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 system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23726.811542                       # average overall mshr miss latency
 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660                       # average overall mshr miss latency
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-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23641.963786                       # average overall mshr miss latency
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 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782                       # average overall mshr miss latency
 system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29557.889053                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
 system.cpu1.toL2Bus.trans_dist::ReadReq      16597851                       # Transaction distribution
@@ -2344,20 +2438,24 @@ system.l2c.tags.warmup_cycle               8003493500                       # Cy
 system.l2c.tags.occ_blocks::writebacks   16627.933383                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.dtb.walker    13.809416                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker    10.076521                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7682.914611                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4159.600580                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     3523.314031                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  5733.726218                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.dtb.walker   373.789781                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.itb.walker   460.262003                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst    14361.821399                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3670.846899                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    10690.974499                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 19215.753624                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.253722                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu0.inst       0.117232                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.063470                       # Average percentage of cache occupancy
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 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.005704                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.itb.walker     0.007023                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.219144                       # Average percentage of cache occupancy
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 system.l2c.tags.occ_percent::total           0.983888                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1022        14505                       # Occupied blocks per task id
@@ -2379,240 +2477,276 @@ system.l2c.tags.tag_accesses                 65568567                       # Nu
 system.l2c.tags.data_accesses                65568567                       # Number of data accesses
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 system.l2c.ReadReq_hits::total                3314514                       # number of ReadReq hits
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-system.l2c.WriteInvalidateReq_hits::cpu0.inst       125819                       # number of WriteInvalidateReq hits
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 system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  37505012849                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.dtb.walker    202393999                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.itb.walker    185177500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst  16969846032                       # number of overall miss cycles
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 system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  31520804985                       # number of overall miss cycles
 system.l2c.overall_miss_latency::total   106467817356                       # number of overall miss cycles
 system.l2c.ReadReq_accesses::cpu0.dtb.walker         8395                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.itb.walker         6043                       # number of ReadReq accesses(hits+misses)
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 system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       796553                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.dtb.walker         9295                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.itb.walker         6808                       # number of ReadReq accesses(hits+misses)
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 system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher       786977                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            4184800                       # number of ReadReq accesses(hits+misses)
 system.l2c.Writeback_accesses::writebacks      2491671                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total          2491671                       # number of Writeback accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu0.inst       561349                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu1.inst       264022                       # number of WriteInvalidateReq accesses(hits+misses)
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 system.l2c.WriteInvalidateReq_accesses::total       825371                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.inst        74724                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.inst        77877                       # number of UpgradeReq accesses(hits+misses)
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 system.l2c.UpgradeReq_accesses::total          152601                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.inst        14136                       # number of SCUpgradeReq accesses(hits+misses)
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 system.l2c.SCUpgradeReq_accesses::total         29560                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.inst       133036                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.inst       108495                       # number of ReadExReq accesses(hits+misses)
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 system.l2c.ReadExReq_accesses::total           241531                       # number of ReadExReq accesses(hits+misses)
 system.l2c.demand_accesses::cpu0.dtb.walker         8395                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.itb.walker         6043                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         1353971                       # number of demand (read+write) accesses
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 system.l2c.demand_accesses::cpu0.l2cache.prefetcher       796553                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.dtb.walker         9295                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.itb.walker         6808                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst         1458289                       # number of demand (read+write) accesses
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 system.l2c.demand_accesses::cpu1.l2cache.prefetcher       786977                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             4426331                       # number of demand (read+write) accesses
 system.l2c.overall_accesses::cpu0.dtb.walker         8395                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.itb.walker         6043                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        1353971                       # number of overall (read+write) accesses
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 system.l2c.overall_accesses::cpu0.l2cache.prefetcher       796553                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.dtb.walker         9295                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.itb.walker         6808                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        1458289                       # number of overall (read+write) accesses
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 system.l2c.overall_accesses::cpu1.l2cache.prefetcher       786977                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            4426331                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.198213                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.215290                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.138495                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu0.data      0.207496                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.344865                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.266595                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.339160                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.120184                       # miss rate for ReadReq accesses
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 system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.325950                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::total          0.207964                       # miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu0.inst     0.775863                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.inst     0.467828                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.775863                       # miss rate for WriteInvalidateReq accesses
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 system.l2c.WriteInvalidateReq_miss_rate::total     0.677328                       # miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.601667                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.583921                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.601667                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.583921                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::total       0.592611                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.inst     0.584394                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.585970                       # miss rate for SCUpgradeReq accesses
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 system.l2c.SCUpgradeReq_miss_rate::total     0.585217                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.inst     0.576077                       # miss rate for ReadExReq accesses
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 system.l2c.ReadExReq_miss_rate::total        0.545673                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu0.dtb.walker     0.198213                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu0.inst       0.181490                       # miss rate for demand accesses
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-system.l2c.overall_miss_rate::cpu0.inst      0.181490                       # miss rate for overall accesses
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 system.l2c.overall_miss_rate::total          0.226391                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83510.664663                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85361.451191                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80169.090855                       # average ReadReq miss latency
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 system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567                       # average ReadReq miss latency
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 system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 80198.137722                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78670.068054                       # average ReadReq miss latency
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 system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total 110287.345605                       # average ReadReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.inst    84.065307                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.inst   289.502514                       # average WriteInvalidateReq miss latency
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 system.l2c.WriteInvalidateReq_avg_miss_latency::total   129.455028                       # average WriteInvalidateReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  4749.705954                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  4765.015503                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  4749.705954                       # average UpgradeReq miss latency
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 system.l2c.UpgradeReq_avg_miss_latency::total  4757.404321                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst  4442.559860                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst  4570.178026                       # average SCUpgradeReq miss latency
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 system.l2c.SCUpgradeReq_avg_miss_latency::total  4509.234985                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 81923.471301                       # average ReadExReq miss latency
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 system.l2c.ReadExReq_avg_miss_latency::total 79563.908883                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83510.664663                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85361.451191                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 80716.247770                       # average overall miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81676.351493                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 80198.137722                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 78064.992028                       # average overall miss latency
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 system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total 106246.505884                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83510.664663                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85361.451191                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 80716.247770                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 77090.527175                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 82294.798121                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81676.351493                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 80198.137722                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 78064.992028                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 76553.012049                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 78591.993908                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total 106246.505884                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs              5735                       # number of cycles access was blocked
@@ -2625,188 +2759,226 @@ system.l2c.fast_writes                              0                       # nu
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks             1116216                       # number of writebacks
 system.l2c.writebacks::total                  1116216                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst           210                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst           177                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.inst           188                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data            22                       # number of ReadReq MSHR hits
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+system.l2c.ReadReq_mshr_hits::cpu1.data            15                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total               387                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            210                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            177                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst            188                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             22                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst            162                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             15                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                387                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           210                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           177                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst           188                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            22                       # number of overall MSHR hits
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 system.l2c.overall_mshr_hits::total               387                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1664                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1301                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst       168883                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst        74347                       # number of ReadReq MSHR misses
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 system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       274703                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2478                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2309                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst       162046                       # number of ReadReq MSHR misses
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 system.l2c.WriteInvalidateReq_mshr_misses::total       559047                       # number of WriteInvalidateReq MSHR misses
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 system.l2c.UpgradeReq_mshr_misses::total        90433                       # number of UpgradeReq MSHR misses
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 system.l2c.SCUpgradeReq_mshr_misses::total        17299                       # number of SCUpgradeReq MSHR misses
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 system.l2c.ReadExReq_mshr_misses::total        131797                       # number of ReadExReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu0.itb.walker         1301                       # number of demand (read+write) MSHR misses
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 system.l2c.demand_mshr_misses::total          1001696                       # number of demand (read+write) MSHR misses
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 system.l2c.ReadReq_mshr_miss_latency::total  85169385965                       # number of ReadReq MSHR miss cycles
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 system.l2c.WriteInvalidateReq_mshr_miss_latency::total  12301694482                       # number of WriteInvalidateReq MSHR miss cycles
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 system.l2c.UpgradeReq_mshr_miss_latency::total    916395657                       # number of UpgradeReq MSHR miss cycles
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 system.l2c.SCUpgradeReq_mshr_miss_latency::total    177262631                       # number of SCUpgradeReq MSHR miss cycles
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 system.l2c.overall_mshr_miss_latency::total  93996922312                       # number of overall MSHR miss cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    418305498                       # number of ReadReq MSHR uncacheable cycles
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 system.l2c.ReadReq_mshr_uncacheable_latency::total   8136500246                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst    484709502                       # number of WriteReq MSHR uncacheable cycles
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 system.l2c.WriteReq_mshr_uncacheable_latency::total   5258700499                       # number of WriteReq MSHR uncacheable cycles
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 system.l2c.overall_mshr_uncacheable_latency::total  13395200745                       # number of overall MSHR uncacheable cycles
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-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.138323                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.120052                       # mshr miss rate for ReadReq accesses
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 system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.325950                       # mshr miss rate for ReadReq accesses
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-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst     0.775863                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst     0.467828                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.775863                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.467828                       # mshr miss rate for WriteInvalidateReq accesses
 system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.677328                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.601667                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.583921                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.601667                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.583921                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total     0.592611                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.584394                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.585970                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.584394                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.585970                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.585217                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.576077                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.508392                       # mshr miss rate for ReadExReq accesses
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-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.181335                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.148944                       # mshr miss rate for demand accesses
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 system.l2c.demand_mshr_miss_rate::total      0.226304                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.198213                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.215290                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.181335                       # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::cpu0.data     0.290745                       # mshr miss rate for overall accesses
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 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.266595                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.148944                       # mshr miss rate for overall accesses
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 system.l2c.overall_mshr_miss_rate::total     0.226304                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67591.919720                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64472.755767                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70044.958587                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66114.279032                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63938.984667                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67263.713741                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::total 97907.212176                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22469.301798                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 20366.746845                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22469.301798                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20366.746845                       # average WriteInvalidateReq mshr miss latency
 system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22004.758959                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10131.989012                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10134.836676                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10131.989012                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10134.836676                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10133.420953                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10275.715047                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10220.729033                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10275.715047                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10220.729033                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10246.987167                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69355.674069                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63675.021611                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69355.674069                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63675.021611                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::total 66978.279832                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68142.470667                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64472.755767                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69736.349993                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65494.840344                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63938.984667                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66035.621841                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::total 93837.773448                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68142.470667                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64472.755767                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69736.349993                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65494.840344                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63938.984667                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66035.621841                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::total 93837.773448                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq              969598                       # Transaction distribution