diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-04 13:02:12 -0600 |
---|---|---|
committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-04 13:02:12 -0600 |
commit | e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb (patch) | |
tree | 553bace58f742b4c98ac52d600a1103901011b8b /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual | |
parent | 0d8d6e44419e2c5464012b66abc62aaad433026b (diff) | |
download | gem5-e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb.tar.xz |
stats: changes due to recent changesets.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 1254 |
1 files changed, 713 insertions, 541 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 3b8bb2577..f7aa432dd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -4,22 +4,24 @@ sim_seconds 47.355615 # Nu sim_ticks 47355615197500 # Number of ticks simulated final_tick 47355615197500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178863 # Simulator instruction rate (inst/s) -host_op_rate 210359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9462962325 # Simulator tick rate (ticks/s) -host_mem_usage 759628 # Number of bytes of host memory used -host_seconds 5004.31 # Real time elapsed on the host +host_inst_rate 119180 # Simulator instruction rate (inst/s) +host_op_rate 140167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6305360463 # Simulator tick rate (ticks/s) +host_mem_usage 747912 # Number of bytes of host memory used +host_seconds 7510.37 # Real time elapsed on the host sim_insts 895084962 # Number of instructions simulated sim_ops 1052703090 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 106496 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 83264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 18925144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 8104128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10821016 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.l2cache.prefetcher 17557952 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 158592 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 147776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 13767904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3589696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 10178208 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 16399360 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 427968 # Number of bytes read from this memory system.physmem.bytes_read::total 67574456 # Number of bytes read from this memory @@ -27,30 +29,34 @@ system.physmem.bytes_inst_read::cpu0.inst 8104128 # N system.physmem.bytes_inst_read::cpu1.inst 3589696 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 11693824 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 78266240 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.inst 20812 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.inst 4 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory system.physmem.bytes_written::total 78287056 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 1664 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1301 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 295727 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 126627 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 169100 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.l2cache.prefetcher 274343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2478 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 2309 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 215138 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 159049 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 256240 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6687 # Number of read requests responded to by this memory system.physmem.num_reads::total 1055887 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1222910 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.inst 2602 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.inst 1 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::total 1225513 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 2249 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 399639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 171133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 228505 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.l2cache.prefetcher 370768 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 3349 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 3121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 290734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 75803 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 214931 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 346302 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 9037 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1426958 # Total read bandwidth from this memory (bytes/s) @@ -58,17 +64,19 @@ system.physmem.bw_inst_read::cpu0.inst 171133 # In system.physmem.bw_inst_read::cpu1.inst 75803 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 246936 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1652734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 439 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1653174 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1652734 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 2249 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 400078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 171133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 228945 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.l2cache.prefetcher 370768 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 3349 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 3121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 290734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 75803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 214931 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 346302 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 9037 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3080131 # Total bandwidth to/from this memory (bytes/s) @@ -354,23 +362,31 @@ system.physmem_1.memoryStateTime::REF 1581308040000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 234336016748 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 16 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 16 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). @@ -588,8 +604,8 @@ system.cpu0.dcache.tags.total_refs 150576282 # To system.cpu0.dcache.tags.sampled_refs 5387564 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 27.948862 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 4951668000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 501.034252 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.978583 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.034252 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978583 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.978583 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id @@ -598,93 +614,93 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 39 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 320066517 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 320066517 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 77114778 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 77114778 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 77114778 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 69351990 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69351990 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 69351990 # number of WriteReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 251432 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 251432 # number of WriteInvalidateReq hits system.cpu0.dcache.WriteInvalidateReq_hits::total 251432 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1745310 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1745310 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 1745310 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1668274 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1668274 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 1668274 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 146466768 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 146466768 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 146466768 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 146466768 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 146466768 # number of overall hits system.cpu0.dcache.overall_hits::total 146466768 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 3852692 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 3852692 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 3852692 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 2255601 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2255601 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 2255601 # number of WriteReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst 766100 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 766100 # number of WriteInvalidateReq misses system.cpu0.dcache.WriteInvalidateReq_misses::total 766100 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 104059 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 104059 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 104059 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 180014 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 180014 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 180014 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 6108293 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 6108293 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 6108293 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 6108293 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 6108293 # number of overall misses system.cpu0.dcache.overall_misses::total 6108293 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 54452724607 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54452724607 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 54452724607 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 41906959422 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 41906959422 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 41906959422 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst 27296991314 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 27296991314 # number of WriteInvalidateReq miss cycles system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 27296991314 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1502404735 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 1502404735 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 1502404735 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3769027814 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3769027814 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 3769027814 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 2840500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2840500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2840500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 96359684029 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 96359684029 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 96359684029 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 96359684029 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 96359684029 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 96359684029 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 80967470 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 80967470 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 80967470 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 71607591 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 71607591 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 71607591 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 1017532 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1017532 # number of WriteInvalidateReq accesses(hits+misses) system.cpu0.dcache.WriteInvalidateReq_accesses::total 1017532 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1849369 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1849369 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 1849369 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1848288 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1848288 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 1848288 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 152575061 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 152575061 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 152575061 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 152575061 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 152575061 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 152575061 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.047583 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.047583 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.047583 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.031499 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031499 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.031499 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst 0.752900 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.752900 # miss rate for WriteInvalidateReq accesses system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.752900 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.056267 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056267 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056267 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.097395 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097395 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097395 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.040035 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040035 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.040035 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.040035 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040035 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.040035 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14133.682269 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14133.682269 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 14133.682269 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 18579.065811 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18579.065811 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 18579.065811 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 35631.107315 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 35631.107315 # average WriteInvalidateReq miss latency system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 35631.107315 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 14438.008582 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14438.008582 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14438.008582 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20937.414946 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20937.414946 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20937.414946 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 15775.222968 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15775.222968 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 15775.222968 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 15775.222968 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15775.222968 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 15775.222968 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -696,91 +712,91 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 3733142 # number of writebacks system.cpu0.dcache.writebacks::total 3733142 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 361487 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 361487 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 361487 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 935411 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 935411 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 935411 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst 100 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 100 # number of WriteInvalidateReq MSHR hits system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 100 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 34 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 34 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 67 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 1296898 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1296898 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 1296898 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 1296898 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1296898 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 1296898 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3491205 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3491205 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 3491205 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1320190 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1320190 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 1320190 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.inst 766000 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 766000 # number of WriteInvalidateReq MSHR misses system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 766000 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 104025 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104025 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104025 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 179947 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 179947 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 179947 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 4811395 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4811395 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 4811395 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 4811395 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4811395 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 4811395 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 42113152704 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42113152704 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42113152704 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 22270249828 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22270249828 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22270249828 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 25755951436 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 25755951436 # number of WriteInvalidateReq MSHR miss cycles system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 25755951436 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1293404753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1293404753 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1293404753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3399276642 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3399276642 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3399276642 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2291500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2291500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2291500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 64383402532 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 64383402532 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 64383402532 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 64383402532 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 64383402532 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 64383402532 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5824362996 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5824362996 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5824362996 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 5586865743 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5586865743 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5586865743 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 11411228739 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11411228739 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11411228739 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.043119 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043119 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043119 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.018436 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018436 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.752802 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.752802 # mshr miss rate for WriteInvalidateReq accesses system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.752802 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.056249 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056249 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056249 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.097359 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097359 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097359 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031535 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.031535 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031535 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.031535 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12062.641038 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12062.641038 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12062.641038 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 16868.973275 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16868.973275 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16868.973275 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 33623.957488 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33623.957488 # average WriteInvalidateReq mshr miss latency system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 33623.957488 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 12433.595318 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12433.595318 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12433.595318 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18890.432416 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18890.432416 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18890.432416 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 13381.441875 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 13381.441875 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 9463678 # number of replacements @@ -891,12 +907,14 @@ system.cpu0.l2cache.tags.warmup_cycle 5578143500 # Cy system.cpu0.l2cache.tags.occ_blocks::writebacks 4129.920995 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 42.114006 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 24.266127 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 9438.642805 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 6921.151423 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2517.491382 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 2562.596205 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.252070 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002570 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001481 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.576089 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.422434 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.153655 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.156408 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.988619 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1022 2519 # Occupied blocks per task id @@ -922,137 +940,155 @@ system.cpu0.l2cache.tags.tag_accesses 319708402 # Nu system.cpu0.l2cache.tags.data_accesses 319708402 # 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mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.648936 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.648936 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.648936 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813285 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.813285 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813285 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.231718 # 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average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23802.344928 # average ReadReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average HardPFReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45624.567406 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 35111.301561 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 35111.301561 # average WriteInvalidateReq mshr miss latency system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 35111.301561 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16958.402220 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16958.402220 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16958.402220 # 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average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28251.910764 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33192.985440 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # 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Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.832241 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.107402 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832241 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.832241 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id @@ -1451,93 +1506,93 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::2 209 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 342291215 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 342291215 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 83489779 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 83489779 # 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average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20545.117182 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14796.728543 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 14796.728543 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14796.728543 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 14796.728543 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -1549,91 +1604,91 @@ system.cpu1.dcache.fast_writes 0 # nu system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 3711348 # number of writebacks system.cpu1.dcache.writebacks::total 3711348 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 397792 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 397792 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 397792 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 970938 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 970938 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 970938 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst 60 # 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mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044572 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044572 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.018407 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018407 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018407 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.868662 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.868662 # mshr miss rate for WriteInvalidateReq accesses system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.868662 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.068929 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068929 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068929 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.094612 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094612 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094612 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.032446 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032446 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.032446 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.032446 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032446 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.032446 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11953.436273 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11953.436273 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11953.436273 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14603.880625 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14603.880625 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14603.880625 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 22356.018920 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22356.018920 # average WriteInvalidateReq mshr miss latency system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22356.018920 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11987.433099 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11987.433099 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11987.433099 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18496.990954 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18496.990954 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18496.990954 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12650.301293 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12650.301293 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 9215030 # number of replacements @@ -1744,12 +1799,14 @@ system.cpu1.l2cache.tags.warmup_cycle 9611078525000 # C system.cpu1.l2cache.tags.occ_blocks::writebacks 5526.220513 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 77.627317 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 76.256480 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 6438.113983 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3620.154380 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2817.959604 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1415.441924 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.337294 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004738 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004654 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.392951 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.220957 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.171995 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086392 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.826029 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2491 # Occupied blocks per task id @@ -1776,141 +1833,159 @@ system.cpu1.l2cache.tags.tag_accesses 321109712 # Nu system.cpu1.l2cache.tags.data_accesses 321109712 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 544517 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158528 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 11678610 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 8400098 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 3278512 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 12381655 # number of ReadReq hits system.cpu1.l2cache.Writeback_hits::writebacks 3711345 # number of Writeback hits system.cpu1.l2cache.Writeback_hits::total 3711345 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.inst 202419 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 202419 # number of WriteInvalidateReq hits system.cpu1.l2cache.WriteInvalidateReq_hits::total 202419 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 77280 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 77280 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 77280 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 41809 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 41809 # number of SCUpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::total 41809 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 939119 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 939119 # number of ReadExReq hits system.cpu1.l2cache.ReadExReq_hits::total 939119 # number of ReadExReq hits system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 544517 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.itb.walker 158528 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 12617729 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 8400098 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 4217631 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::total 13320774 # number of demand (read+write) hits system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 544517 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.itb.walker 158528 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 12617729 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 8400098 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 4217631 # number of overall hits system.cpu1.l2cache.overall_hits::total 13320774 # number of overall hits system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12561 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8870 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 1591427 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 815444 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 775983 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::total 1612858 # number of ReadReq misses system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.inst 272843 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 272843 # number of WriteInvalidateReq misses system.cpu1.l2cache.WriteInvalidateReq_misses::total 272843 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 137034 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 137034 # number of UpgradeReq misses system.cpu1.l2cache.UpgradeReq_misses::total 137034 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 151974 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 151974 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::total 151974 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 244121 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 244121 # number of ReadExReq misses system.cpu1.l2cache.ReadExReq_misses::total 244121 # number of ReadExReq misses system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12561 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8870 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 1835548 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 815444 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1020104 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::total 1856979 # number of demand (read+write) misses system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12561 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8870 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 1835548 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 815444 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1020104 # number of overall misses system.cpu1.l2cache.overall_misses::total 1856979 # number of overall misses system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 455863233 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 358991737 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 47206598788 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 22574174788 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 24632424000 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::total 48021453758 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst 213581444 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 213581444 # number of WriteInvalidateReq miss cycles system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 213581444 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2792930491 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2792930491 # number of UpgradeReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::total 2792930491 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 3071034580 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3071034580 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3071034580 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 1783500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1783500 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1783500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9626384839 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9626384839 # number of ReadExReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::total 9626384839 # number of ReadExReq miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 455863233 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 358991737 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 56832983627 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22574174788 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 34258808839 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::total 57647838597 # number of demand (read+write) miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 455863233 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 358991737 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 56832983627 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22574174788 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 34258808839 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::total 57647838597 # number of overall miss cycles system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 557078 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 167398 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 13270037 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 9215542 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4054495 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 13994513 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::writebacks 3711346 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::total 3711346 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst 475262 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 475262 # number of WriteInvalidateReq accesses(hits+misses) system.cpu1.l2cache.WriteInvalidateReq_accesses::total 475262 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 214314 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 214314 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 214314 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 193783 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193783 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 193783 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 1183240 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1183240 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 1183240 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 557078 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 167398 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 14453277 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 9215542 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5237735 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::total 15177753 # number of demand (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 557078 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 167398 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 14453277 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 9215542 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5237735 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 15177753 # number of overall (read+write) accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052987 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.119926 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.088486 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.191388 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::total 0.115249 # miss rate for ReadReq accesses system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst 0.574090 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.574090 # miss rate for WriteInvalidateReq accesses system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.574090 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.639408 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.639408 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.639408 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.784248 # 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average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16876.429733 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16876.429733 # average UpgradeReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16876.429733 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13661.751912 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13661.751912 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13661.751912 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 1461500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1461500 # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1461500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30747.372117 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30747.372117 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30747.372117 # average ReadExReq mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23641.963786 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26047.861530 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23726.811542 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23641.963786 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26047.861530 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29557.889053 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # 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Cy system.l2c.tags.occ_blocks::writebacks 16627.933383 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.809416 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 10.076521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7682.914611 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4159.600580 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3523.314031 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5733.726218 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 373.789781 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 460.262003 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 14361.821399 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3670.846899 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 10690.974499 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 19215.753624 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.253722 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000211 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.117232 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.063470 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.053762 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.087490 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005704 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.007023 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.219144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.056013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.163131 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.293209 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.983888 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1022 14505 # Occupied blocks per task id @@ -2379,240 +2477,276 @@ system.l2c.tags.tag_accesses 65568567 # Nu system.l2c.tags.data_accesses 65568567 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 6731 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 4742 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 1051842 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 690690 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 361152 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 521850 # 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average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 97907.212176 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22469.301798 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 20366.746845 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22469.301798 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20366.746845 # average WriteInvalidateReq mshr miss latency system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22004.758959 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10131.989012 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10134.836676 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10131.989012 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10134.836676 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10133.420953 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10275.715047 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10220.729033 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10275.715047 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10220.729033 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10246.987167 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69355.674069 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63675.021611 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69355.674069 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63675.021611 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 66978.279832 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69736.349993 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66035.621841 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69736.349993 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66035.621841 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 969598 # Transaction distribution |