diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 5254 |
1 files changed, 2659 insertions, 2595 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 99e4aebe7..d3ad4a453 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.477179 # Number of seconds simulated -sim_ticks 47477179149500 # Number of ticks simulated -final_tick 47477179149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.482330 # Number of seconds simulated +sim_ticks 47482329862000 # Number of ticks simulated +final_tick 47482329862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181000 # Simulator instruction rate (inst/s) -host_op_rate 212908 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9614368962 # Simulator tick rate (ticks/s) -host_mem_usage 772236 # Number of bytes of host memory used -host_seconds 4938.15 # Real time elapsed on the host -sim_insts 893806699 # Number of instructions simulated -sim_ops 1051369194 # Number of ops (including micro ops) simulated +host_inst_rate 176341 # Simulator instruction rate (inst/s) +host_op_rate 207374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9393535208 # Simulator tick rate (ticks/s) +host_mem_usage 769764 # Number of bytes of host memory used +host_seconds 5054.79 # Real time elapsed on the host +sim_insts 891365561 # Number of instructions simulated +sim_ops 1048233259 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 125376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 108736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7965248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 14333320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 15086080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 149568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 136256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3627008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 11510096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 14847104 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 436288 # Number of bytes read from this memory -system.physmem.bytes_read::total 68325080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7965248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3627008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11592256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 80335616 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 124416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 101184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 8041216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 40378184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15310528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 143616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 132928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3236032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 17140560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 13345792 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 446144 # Number of bytes read from this memory +system.physmem.bytes_read::total 98400600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 8041216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3236032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11277248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78262528 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 80356200 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 124457 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 223971 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 235720 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2129 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56672 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 179858 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 231986 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6817 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1067605 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1255244 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78283112 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1944 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1581 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 125644 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 630922 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 239227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2244 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 50563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 267834 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 208528 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6971 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1537535 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1222852 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1257818 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 167770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 301899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 317754 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 76395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 242434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 312721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1439114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 167770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 76395 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 244165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1692089 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1225426 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 169352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 850383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 322447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3025 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 68152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 360988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 281069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2072363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 169352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 68152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 237504 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1648245 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1692523 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1692089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 167770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 302333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 317754 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 76395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 242434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 312721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3131637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1067605 # Number of read requests accepted -system.physmem.writeReqs 1929186 # Number of write requests accepted -system.physmem.readBursts 1067605 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1929186 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 68309056 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue -system.physmem.bytesWritten 120257344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 68325080 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 123323752 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 50133 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 117648 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 62386 # Per bank write bursts -system.physmem.perBankRdBursts::1 65796 # Per bank write bursts -system.physmem.perBankRdBursts::2 60427 # Per bank write bursts -system.physmem.perBankRdBursts::3 63507 # Per bank write bursts -system.physmem.perBankRdBursts::4 66319 # Per bank write bursts -system.physmem.perBankRdBursts::5 73621 # Per bank write bursts -system.physmem.perBankRdBursts::6 69221 # Per bank write bursts -system.physmem.perBankRdBursts::7 63591 # Per bank write bursts -system.physmem.perBankRdBursts::8 61143 # Per bank write bursts -system.physmem.perBankRdBursts::9 115825 # Per bank write bursts -system.physmem.perBankRdBursts::10 59973 # Per bank write bursts -system.physmem.perBankRdBursts::11 66407 # Per bank write bursts -system.physmem.perBankRdBursts::12 58867 # Per bank write bursts -system.physmem.perBankRdBursts::13 61123 # Per bank write bursts -system.physmem.perBankRdBursts::14 58743 # Per bank write bursts -system.physmem.perBankRdBursts::15 60380 # Per bank write bursts -system.physmem.perBankWrBursts::0 115877 # Per bank write bursts -system.physmem.perBankWrBursts::1 122877 # Per bank write bursts -system.physmem.perBankWrBursts::2 115996 # Per bank write bursts -system.physmem.perBankWrBursts::3 119851 # Per bank write bursts -system.physmem.perBankWrBursts::4 119313 # Per bank write bursts -system.physmem.perBankWrBursts::5 126432 # Per bank write bursts -system.physmem.perBankWrBursts::6 119028 # Per bank write bursts -system.physmem.perBankWrBursts::7 120185 # Per bank write bursts -system.physmem.perBankWrBursts::8 118113 # Per bank write bursts -system.physmem.perBankWrBursts::9 119452 # Per bank write bursts -system.physmem.perBankWrBursts::10 113141 # Per bank write bursts -system.physmem.perBankWrBursts::11 117109 # Per bank write bursts -system.physmem.perBankWrBursts::12 112676 # Per bank write bursts -system.physmem.perBankWrBursts::13 113553 # Per bank write bursts -system.physmem.perBankWrBursts::14 112771 # Per bank write bursts -system.physmem.perBankWrBursts::15 112647 # Per bank write bursts +system.physmem.bw_write::total 1648679 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1648245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 169352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 850817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 322447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 68152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 360988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 281069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3721041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1537535 # Number of read requests accepted +system.physmem.writeReqs 1225426 # Number of write requests accepted +system.physmem.readBursts 1537535 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1225426 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 98362112 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 40128 # Total number of bytes read from write queue +system.physmem.bytesWritten 78282112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 98400600 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78283112 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 627 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 220170 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 94941 # Per bank write bursts +system.physmem.perBankRdBursts::1 98803 # Per bank write bursts +system.physmem.perBankRdBursts::2 90365 # Per bank write bursts +system.physmem.perBankRdBursts::3 103122 # Per bank write bursts +system.physmem.perBankRdBursts::4 90513 # Per bank write bursts +system.physmem.perBankRdBursts::5 102407 # Per bank write bursts +system.physmem.perBankRdBursts::6 86370 # Per bank write bursts +system.physmem.perBankRdBursts::7 97727 # Per bank write bursts +system.physmem.perBankRdBursts::8 90531 # Per bank write bursts +system.physmem.perBankRdBursts::9 141203 # Per bank write bursts +system.physmem.perBankRdBursts::10 86748 # Per bank write bursts +system.physmem.perBankRdBursts::11 95428 # Per bank write bursts +system.physmem.perBankRdBursts::12 92596 # Per bank write bursts +system.physmem.perBankRdBursts::13 93840 # Per bank write bursts +system.physmem.perBankRdBursts::14 85305 # Per bank write bursts +system.physmem.perBankRdBursts::15 87009 # Per bank write bursts +system.physmem.perBankWrBursts::0 77173 # Per bank write bursts +system.physmem.perBankWrBursts::1 80360 # Per bank write bursts +system.physmem.perBankWrBursts::2 74652 # Per bank write bursts +system.physmem.perBankWrBursts::3 83758 # Per bank write bursts +system.physmem.perBankWrBursts::4 75004 # Per bank write bursts +system.physmem.perBankWrBursts::5 81344 # Per bank write bursts +system.physmem.perBankWrBursts::6 71841 # Per bank write bursts +system.physmem.perBankWrBursts::7 79366 # Per bank write bursts +system.physmem.perBankWrBursts::8 74851 # Per bank write bursts +system.physmem.perBankWrBursts::9 75375 # Per bank write bursts +system.physmem.perBankWrBursts::10 73319 # Per bank write bursts +system.physmem.perBankWrBursts::11 78054 # Per bank write bursts +system.physmem.perBankWrBursts::12 76445 # Per bank write bursts +system.physmem.perBankWrBursts::13 77751 # Per bank write bursts +system.physmem.perBankWrBursts::14 70793 # Per bank write bursts +system.physmem.perBankWrBursts::15 73072 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 226 # Number of times write queue was full causing retry -system.physmem.totGap 47477177227000 # Total gap between requests +system.physmem.numWrRetry 43 # Number of times write queue was full causing retry +system.physmem.totGap 47482327991500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1067575 # Read request sizes (log2) +system.physmem.readPktSize::6 1537505 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1926612 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 704225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 50762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38076 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 32557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 29624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 27261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 21025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 5650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1222852 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 944383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 373776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 49487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 29546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 27146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 25089 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 22356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 19759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 863 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 440 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,153 +188,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 45205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 65288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 93465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 105702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 113971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 112162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 108444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 104050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 100974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 97727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 97663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 116214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 104741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 100206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 114790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 102548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 96204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 91928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 6040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 704 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1080190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 174.567156 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 106.861850 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 244.135229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 694007 64.25% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 206792 19.14% 83.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51978 4.81% 88.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24974 2.31% 90.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18580 1.72% 92.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11712 1.08% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8387 0.78% 94.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7821 0.72% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 55939 5.18% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1080190 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 83578 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.770071 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 136.461901 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 83575 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 83578 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 83578 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.482244 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.955849 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.755182 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 75860 90.77% 90.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 5202 6.22% 96.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 1276 1.53% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 755 0.90% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 241 0.29% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 100 0.12% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 48 0.06% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-255 8 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 9 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 10 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 17 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-383 25 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-415 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-447 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-479 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-511 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-543 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-575 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-671 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-703 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1056-1087 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 83578 # Writes before turning the bus around for reads -system.physmem.totQLat 40962619238 # Total ticks spent queuing -system.physmem.totMemAccLat 60975037988 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5336645000 # Total ticks spent in databus transfers -system.physmem.avgQLat 38378.62 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 17449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 20135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 57274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 64486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 68059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 69963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 74225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 75616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 79113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 78742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 81088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 80039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 81169 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 122 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 940608 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 187.797442 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 115.260175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 246.189901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 561167 59.66% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 186793 19.86% 79.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 62478 6.64% 86.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 31194 3.32% 89.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21090 2.24% 91.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13303 1.41% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10059 1.07% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 10062 1.07% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 44462 4.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 940608 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 69828 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.009810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 322.555489 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 69825 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 69828 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 69828 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.516727 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.040521 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.611414 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 66194 94.80% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1213 1.74% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 484 0.69% 97.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 227 0.33% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 283 0.41% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 499 0.71% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 107 0.15% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 41 0.06% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 40 0.06% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 28 0.04% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 48 0.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 19 0.03% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 437 0.63% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 36 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 59 0.08% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 38 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 18 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 30 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 69828 # Writes before turning the bus around for reads +system.physmem.totQLat 47438420321 # Total ticks spent queuing +system.physmem.totMemAccLat 76255445321 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7684540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30866.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 57128.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.53 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 49616.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.07 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.20 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.74 # Average write queue length when enqueuing -system.physmem.readRowHits 799066 # Number of row buffer hits during reads -system.physmem.writeRowHits 1067089 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 56.79 # Row buffer hit rate for writes -system.physmem.avgGap 15842672.12 # Average gap between requests -system.physmem.pageHitRate 63.34 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4225820760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2305755375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4093954800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6217942320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3100978164960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1196990920755 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27436312080750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31751124639720 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.766110 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45642284556030 # Time in different power states -system.physmem_0.memoryStateTime::REF 1585367160000 # Time in different power states +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.49 # Average write queue length when enqueuing +system.physmem.readRowHits 1237162 # Number of row buffer hits during reads +system.physmem.writeRowHits 582295 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.61 # Row buffer hit rate for writes +system.physmem.avgGap 17185305.18 # Average gap between requests +system.physmem.pageHitRate 65.92 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3664415160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1999432875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5961079800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4040267040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3101314831680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1200459376170 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27436362274500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31753801677225 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.749891 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45642197013620 # Time in different power states +system.physmem_0.memoryStateTime::REF 1585539280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 249523460470 # Time in different power states +system.physmem_0.memoryStateTime::ACT 254592941380 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3940415640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2150028375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4231125600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5958113760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3100978164960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1192295919105 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27440430503250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31749984270690 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.742090 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45649112064952 # Time in different power states -system.physmem_1.memoryStateTime::REF 1585367160000 # Time in different power states +system.physmem_1.actEnergy 3446581320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1880575125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6026748000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3885796800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3101314831680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1189099091205 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27446327436750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31751981060880 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.711548 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45658799171891 # Time in different power states +system.physmem_1.memoryStateTime::REF 1585539280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 242698243548 # Time in different power states +system.physmem_1.memoryStateTime::ACT 237989586859 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -368,15 +379,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 146228375 # Number of BP lookups -system.cpu0.branchPred.condPredicted 102974776 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6711039 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 109409110 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 78811291 # Number of BTB hits +system.cpu0.branchPred.lookups 132987745 # Number of BP lookups +system.cpu0.branchPred.condPredicted 94268605 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6098049 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 100013530 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 72636793 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.033573 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17518133 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1190785 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.626967 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15695407 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1093856 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -407,62 +418,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 302414 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 302414 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9161 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80364 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 302414 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 302414 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 302414 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 89525 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 18873.046300 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17079.714221 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14739.219535 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 88579 98.94% 98.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 783 0.87% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 49 0.05% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 43 0.05% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 89525 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 80364 89.77% 89.77% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9161 10.23% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 89525 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302414 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 275636 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 275636 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8285 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76005 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 275636 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 275636 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 275636 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 84290 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 20584.826195 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18820.617576 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14196.942212 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 79742 94.60% 94.60% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3631 4.31% 98.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 417 0.49% 99.41% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 355 0.42% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 30 0.04% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 13 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 32 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 8 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 18 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 24 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 84290 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 669754704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 669754704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 669754704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 76005 90.17% 90.17% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8285 9.83% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 84290 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 275636 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302414 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89525 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 275636 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 84290 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89525 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 391939 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 84290 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 359926 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 94852147 # DTB read hits -system.cpu0.dtb.read_misses 252189 # DTB read misses -system.cpu0.dtb.write_hits 83443537 # DTB write hits -system.cpu0.dtb.write_misses 50225 # DTB write misses +system.cpu0.dtb.read_hits 84907220 # DTB read hits +system.cpu0.dtb.read_misses 227423 # DTB read misses +system.cpu0.dtb.write_hits 75575788 # DTB write hits +system.cpu0.dtb.write_misses 48213 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36113 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2068 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9574 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 35105 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1851 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8962 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10663 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 95104336 # DTB read accesses -system.cpu0.dtb.write_accesses 83493762 # DTB write accesses +system.cpu0.dtb.perms_faults 10953 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 85134643 # DTB read accesses +system.cpu0.dtb.write_accesses 75624001 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 178295684 # DTB hits -system.cpu0.dtb.misses 302414 # DTB misses -system.cpu0.dtb.accesses 178598098 # DTB accesses +system.cpu0.dtb.hits 160483008 # DTB hits +system.cpu0.dtb.misses 275636 # DTB misses +system.cpu0.dtb.accesses 160758644 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -492,187 +507,193 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 66598 # Table walker walks requested -system.cpu0.itb.walker.walksLong 66598 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 516 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54284 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 66598 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 66598 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 66598 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 54800 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 21262.637080 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 19017.155066 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 16721.874177 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 53728 98.04% 98.04% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 946 1.73% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 48 0.09% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 54 0.10% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 9 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 54800 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54284 99.06% 99.06% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 516 0.94% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 54800 # Table walker page sizes translated +system.cpu0.itb.walker.walks 64906 # Table walker walks requested +system.cpu0.itb.walker.walksLong 64906 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 453 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52493 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 64906 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 64906 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 64906 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 52946 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 23323.187776 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21129.664435 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 16367.746814 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 48035 90.72% 90.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3919 7.40% 98.13% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 305 0.58% 98.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 573 1.08% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 22 0.04% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 23 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 32 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 10 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 11 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 52946 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 669040204 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 669040204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 669040204 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 52493 99.14% 99.14% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 453 0.86% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 52946 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66598 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66598 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64906 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64906 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54800 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54800 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 121398 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 261387859 # ITB inst hits -system.cpu0.itb.inst_misses 66598 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52946 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52946 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 117852 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 238223958 # ITB inst hits +system.cpu0.itb.inst_misses 64906 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25865 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24846 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 223375 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 205008 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 261454457 # ITB inst accesses -system.cpu0.itb.hits 261387859 # DTB hits -system.cpu0.itb.misses 66598 # DTB misses -system.cpu0.itb.accesses 261454457 # DTB accesses -system.cpu0.numCycles 1029830596 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 238288864 # ITB inst accesses +system.cpu0.itb.hits 238223958 # DTB hits +system.cpu0.itb.misses 64906 # DTB misses +system.cpu0.itb.accesses 238288864 # DTB accesses +system.cpu0.numCycles 971262699 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 487755400 # Number of instructions committed -system.cpu0.committedOps 573075495 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 47715438 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4391 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93925247519 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.111367 # CPI: cycles per instruction -system.cpu0.ipc 0.473627 # IPC: instructions per cycle +system.cpu0.committedInsts 437915417 # Number of instructions committed +system.cpu0.committedOps 515248827 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 45685554 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4508 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93994129820 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.217923 # CPI: cycles per instruction +system.cpu0.ipc 0.450872 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13314 # number of quiesce instructions executed -system.cpu0.tickCycles 777849504 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 251981092 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5902107 # number of replacements -system.cpu0.dcache.tags.tagsinuse 475.000126 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 169363182 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5902609 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.692936 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 5093256500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.000126 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.927735 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.927735 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 502 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 153 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.980469 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 359562725 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 359562725 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 86974547 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 86974547 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 77401946 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 77401946 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 298185 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 298185 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 275916 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 275916 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1961524 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1961524 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1923644 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1923644 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 164376493 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 164376493 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 164674678 # number of overall hits -system.cpu0.dcache.overall_hits::total 164674678 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3650210 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3650210 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2435892 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2435892 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670224 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 670224 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 817849 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 817849 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 165967 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 165967 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202383 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 202383 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6086102 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6086102 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6756326 # number of overall misses -system.cpu0.dcache.overall_misses::total 6756326 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 55969500387 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 55969500387 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 47032436273 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 47032436273 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 33507618312 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 33507618312 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2441854002 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2441854002 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4283229947 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4283229947 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1855000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1855000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 103001936660 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 103001936660 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 103001936660 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 103001936660 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 90624757 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 90624757 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 79837838 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 79837838 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 968409 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 968409 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093765 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1093765 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2127491 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2127491 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2126027 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2126027 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 170462595 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 170462595 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 171431004 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 171431004 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040278 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.040278 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030510 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030510 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.692088 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.692088 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.747737 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.747737 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.078011 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078011 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095193 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095193 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.035703 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.035703 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039411 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.039411 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15333.227509 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15333.227509 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19308.095873 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19308.095873 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40970.421572 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 40970.421572 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14712.888719 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14712.888719 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21163.980903 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21163.980903 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 13434 # number of quiesce instructions executed +system.cpu0.tickCycles 710739035 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 260523664 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5570429 # number of replacements +system.cpu0.dcache.tags.tagsinuse 501.849943 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 152007137 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5570934 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.285754 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4974167000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.849943 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980176 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.980176 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 323765599 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 323765599 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 77611950 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77611950 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69963904 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69963904 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 263445 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 263445 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 169638 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 169638 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1758419 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1758419 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1721710 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1721710 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 147575854 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 147575854 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 147839299 # number of overall hits +system.cpu0.dcache.overall_hits::total 147839299 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3380647 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3380647 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2384184 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2384184 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670394 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 670394 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 781336 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 781336 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 154783 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 154783 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189820 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 189820 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5764831 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5764831 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6435225 # number of overall misses +system.cpu0.dcache.overall_misses::total 6435225 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 51653726500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 51653726500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 46144722000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 46144722000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 52344211500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 52344211500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2307846500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2307846500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3989603000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3989603000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3214000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3214000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 97798448500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 97798448500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 97798448500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 97798448500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 80992597 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 80992597 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 72348088 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 72348088 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 933839 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 933839 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 950974 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 950974 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1913202 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1913202 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1911530 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1911530 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 153340685 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 153340685 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 154274524 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 154274524 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041740 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.041740 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032954 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.032954 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.717890 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.717890 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.821617 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.821617 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080903 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.080903 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099303 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099303 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037595 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.037595 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041713 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.041713 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15279.242849 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15279.242849 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19354.513746 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19354.513746 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 66993.216107 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 66993.216107 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14910.206547 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14910.206547 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21017.822147 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21017.822147 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16924.122642 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16924.122642 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15245.258541 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15245.258541 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16964.668782 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16964.668782 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15197.362718 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15197.362718 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -681,161 +702,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3966592 # number of writebacks -system.cpu0.dcache.writebacks::total 3966592 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 443574 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 443574 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1010368 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1010368 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 102 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 102 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43626 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43626 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 27 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 27 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1453942 # 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number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122341 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 122341 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202356 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 202356 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4632160 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4632160 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5296975 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5296975 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31604 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31604 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30977 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 30977 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62581 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62581 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42580313466 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42580313466 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25667045166 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25667045166 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14837829930 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14837829930 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 32271814438 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 32271814438 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1568491891 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1568491891 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3969414040 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3969414040 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1696000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1696000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 68247358632 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 68247358632 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 83085188562 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 83085188562 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5612600750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5612600750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5285393252 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5285393252 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10897994002 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10897994002 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035384 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035384 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017855 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017855 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.686502 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.686502 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.747644 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.747644 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057505 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057505 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095180 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095180 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027174 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027174 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030899 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030899 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13278.811024 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13278.811024 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18005.340609 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18005.340609 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22318.735182 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22318.735182 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39464.301842 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39464.301842 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12820.656125 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12820.656125 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19615.993793 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19615.993793 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3773399 # number of writebacks +system.cpu0.dcache.writebacks::total 3773399 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 430069 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 430069 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 999795 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 999795 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 103 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 103 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40774 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 40774 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 43 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1429864 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1429864 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1429864 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1429864 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2950578 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2950578 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1384389 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1384389 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664773 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 664773 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 781233 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 781233 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 114009 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 114009 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189777 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 189777 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4334967 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4334967 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4999740 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4999740 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32882 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32882 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32815 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32815 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65697 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65697 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40501320500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40501320500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25594559000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25594559000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15267286500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15267286500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 51557242500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 51557242500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1530630500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1530630500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3798446000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3798446000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2841500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2841500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 66095879500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 66095879500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81363166000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 81363166000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5911844500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5911844500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5682739500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5682739500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11594584000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11594584000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036430 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036430 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019135 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019135 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.711871 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.711871 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.821508 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.821508 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059591 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059591 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099280 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099280 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028270 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028270 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032408 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032408 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13726.571709 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13726.571709 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18487.982063 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18487.982063 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22966.165142 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22966.165142 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 65994.706445 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 65994.706445 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13425.523424 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13425.523424 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20015.312709 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20015.312709 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14733.376790 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14733.376790 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15685.403190 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15685.403190 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177591.467852 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177591.467852 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170623.147884 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170623.147884 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174142.215720 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174142.215720 # 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Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 431 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 532607059 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 532607059 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 250868144 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 250868144 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 250868144 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 250868144 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 250868144 # number of overall hits -system.cpu0.icache.overall_hits::total 250868144 # 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number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 261158401 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 261158401 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 261158401 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 261158401 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 261158401 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 261158401 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039402 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.039402 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039402 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.039402 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039402 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9460.124992 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8031555 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8035489 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 3395 # 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Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5460.175756 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3311.396146 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 928.755541 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.390955 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004062 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003623 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.333263 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.202112 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056687 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.990701 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1465 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 86 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14441 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 685 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 484 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 25 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 40 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 671 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4595 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6778 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2297 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.084167 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.885559 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 347615506 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 347615506 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522089 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 157285 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 9486915 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2945564 # 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number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 157285 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 9486915 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3872988 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 14039277 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 522089 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 157285 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 9486915 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3872988 # number of overall hits -system.cpu0.l2cache.overall_hits::total 14039277 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12017 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8240 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 803341 # 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miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049781 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.078068 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.262412 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.124908 # miss rate for ReadReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.730401 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.730401 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.568064 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.568064 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.821496 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.821496 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 15 # 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mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.217482 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.217482 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022499 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049763 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078067 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.251858 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.131688 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022499 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049763 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078067 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.251858 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.233619 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.233619 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081749 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273400 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.273400 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755630 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755630 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263984 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.138710 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263984 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.178514 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27473.220807 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25880.813515 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48160.836260 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48160.836260 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43640.937143 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43640.937143 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20345.789725 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20345.789725 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14744.179820 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14744.179820 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 712749.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 712749.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41400.167567 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41400.167567 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30245.364016 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27775.872116 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30245.364016 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48160.836260 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33122.966054 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169590.676813 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 116204.246166 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163122.558640 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163122.558640 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 166389.019814 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128854.728074 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187286 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30086.717448 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48894.087088 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20301.303730 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20301.303730 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15251.634537 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15251.634537 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 794166 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 794166 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39966.645809 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39966.645809 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24404.302768 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27220.014094 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27220.014094 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 77198.341917 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77198.341917 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29889.876681 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27849.318172 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29889.876681 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33307.659423 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171784.395718 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117501.338437 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165674.249581 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165674.249581 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168732.438315 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130899.147378 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 17664917 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 15307376 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 30977 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3966591 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1103078 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166462 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 816287 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 481802 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368927 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 516230 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1338230 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1206066 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20685127 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17177406 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 364539 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1170846 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 39397918 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 661924032 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 645723507 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1324200 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4272848 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1313244587 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4794163 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 26128529 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.203121 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.402322 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 870203 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14200168 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32815 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 7469298 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 14383795 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1113522 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 480939 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348630 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 494804 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 46 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1552927 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1165328 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9511346 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6196752 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 886361 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 779633 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28635865 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18059535 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 358708 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1078688 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 48132796 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 612072768 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 561022439 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1317384 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3945224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1178357815 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 11561310 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 42854991 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.281176 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.449573 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 20821287 79.69% 79.69% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 5307242 20.31% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 30805196 71.88% 71.88% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 12049795 28.12% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 26128529 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 15626998682 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 42854991 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 19582200977 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 207003480 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 188679986 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 15540735463 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14347273859 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8534595583 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7985002182 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 199309237 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 194043982 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 637104704 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 585561447 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 125576312 # Number of BP lookups -system.cpu1.branchPred.condPredicted 90437850 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5588126 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 96414800 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 70448335 # Number of BTB hits +system.cpu1.branchPred.lookups 137760504 # Number of BP lookups +system.cpu1.branchPred.condPredicted 98367064 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6188278 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 103396299 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 75843064 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.067968 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 14240452 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 921306 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.351817 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15930905 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1003913 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1329,67 +1378,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 267188 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 267188 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10577 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85745 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 267188 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 267188 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 267188 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 96322 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 19417.832759 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17582.202051 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14852.958051 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 91721 95.22% 95.22% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3398 3.53% 98.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 602 0.62% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 416 0.43% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 24 0.02% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 24 0.02% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 36 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 19 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 31 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 34 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 96322 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1244507444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1244507444 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1244507444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 85745 89.02% 89.02% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10577 10.98% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 96322 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 267188 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 290439 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 290439 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10797 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87034 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 290439 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 290439 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 290439 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 97831 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20885.603745 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 19076.396548 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15781.781984 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 96557 98.70% 98.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.10% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 36 0.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 66 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 60 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 20 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 97831 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1532721648 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1532721648 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1532721648 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 87034 88.96% 88.96% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10797 11.04% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 97831 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 290439 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 267188 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 96322 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 290439 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97831 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 96322 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 363510 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97831 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 388270 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 79480191 # DTB read hits -system.cpu1.dtb.read_misses 220503 # DTB read misses -system.cpu1.dtb.write_hits 69950509 # DTB write hits -system.cpu1.dtb.write_misses 46685 # DTB write misses +system.cpu1.dtb.read_hits 89204123 # DTB read hits +system.cpu1.dtb.read_misses 242859 # DTB read misses +system.cpu1.dtb.write_hits 77378465 # DTB write hits +system.cpu1.dtb.write_misses 47580 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 40279 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1007 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7671 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 40087 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1034 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8257 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 12807 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 79700694 # DTB read accesses -system.cpu1.dtb.write_accesses 69997194 # DTB write accesses +system.cpu1.dtb.perms_faults 11467 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 89446982 # DTB read accesses +system.cpu1.dtb.write_accesses 77426045 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 149430700 # DTB hits -system.cpu1.dtb.misses 267188 # DTB misses -system.cpu1.dtb.accesses 149697888 # DTB accesses +system.cpu1.dtb.hits 166582588 # DTB hits +system.cpu1.dtb.misses 290439 # DTB misses +system.cpu1.dtb.accesses 166873027 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1419,187 +1463,192 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 64917 # Table walker walks requested -system.cpu1.itb.walker.walksLong 64917 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 645 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55496 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 64917 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 64917 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 64917 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 56141 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 22418.994977 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 19682.840516 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19289.014659 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 54677 97.39% 97.39% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1297 2.31% 99.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 81 0.14% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 18 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 56141 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1243919944 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1243919944 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1243919944 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 55496 98.85% 98.85% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 645 1.15% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 56141 # Table walker page sizes translated +system.cpu1.itb.walker.walks 66791 # Table walker walks requested +system.cpu1.itb.walker.walksLong 66791 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 712 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57147 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 66791 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 66791 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 66791 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 57859 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 23479.562384 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 21074.499694 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18067.183609 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 53326 92.17% 92.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 3146 5.44% 97.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 488 0.84% 98.45% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 735 1.27% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.05% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 27 0.05% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 52 0.09% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 8 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 9 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 57859 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1533304148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1533304148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1533304148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 57147 98.77% 98.77% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 712 1.23% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 57859 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64917 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64917 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 66791 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 66791 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56141 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56141 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 121058 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 225481249 # ITB inst hits -system.cpu1.itb.inst_misses 64917 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57859 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 57859 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 124650 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 246625416 # ITB inst hits +system.cpu1.itb.inst_misses 66791 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 28543 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 29073 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 202570 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 217204 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 225546166 # ITB inst accesses -system.cpu1.itb.hits 225481249 # DTB hits -system.cpu1.itb.misses 64917 # DTB misses -system.cpu1.itb.accesses 225546166 # DTB accesses -system.cpu1.numCycles 849119079 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 246692207 # ITB inst accesses +system.cpu1.itb.hits 246625416 # DTB hits +system.cpu1.itb.misses 66791 # DTB misses +system.cpu1.itb.accesses 246692207 # DTB accesses +system.cpu1.numCycles 916577474 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 406051299 # Number of instructions committed -system.cpu1.committedOps 478293699 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 46606937 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5644 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 94106060514 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.091162 # CPI: cycles per instruction -system.cpu1.ipc 0.478203 # IPC: instructions per cycle +system.cpu1.committedInsts 453450144 # Number of instructions committed +system.cpu1.committedOps 532984432 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 47678042 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5221 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 94048897478 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.021341 # CPI: cycles per instruction +system.cpu1.ipc 0.494721 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5757 # number of quiesce instructions executed -system.cpu1.tickCycles 666946808 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 182172271 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5052284 # number of replacements -system.cpu1.dcache.tags.tagsinuse 457.990994 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 141727438 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5052796 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.049309 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8380007678500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.990994 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.894514 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.894514 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 5293 # number of quiesce instructions executed +system.cpu1.tickCycles 728135326 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 188442148 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5347951 # number of replacements +system.cpu1.dcache.tags.tagsinuse 430.817141 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 158458993 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5348463 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.627015 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8387659413500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.817141 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.841440 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.841440 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 301466109 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 301466109 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 72704936 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 72704936 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 65165576 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 65165576 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 206723 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 206723 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 46881 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 46881 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1586345 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1586345 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1544117 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1544117 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 137870512 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 137870512 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 138077235 # number of overall hits -system.cpu1.dcache.overall_hits::total 138077235 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3207186 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3207186 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2249159 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2249159 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 660232 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 660232 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 426407 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 426407 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 160976 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 160976 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201965 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 201965 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5456345 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5456345 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6116577 # number of overall misses -system.cpu1.dcache.overall_misses::total 6116577 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 49733165026 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 49733165026 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 39916128019 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 39916128019 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12105984043 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12105984043 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2535632453 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2535632453 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4276755567 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4276755567 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1256500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1256500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 89649293045 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 89649293045 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 89649293045 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 89649293045 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 75912122 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 75912122 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 67414735 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 67414735 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 866955 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 866955 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 473288 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 473288 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1747321 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1747321 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1746082 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1746082 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 143326857 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 143326857 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 144193812 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 144193812 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.042249 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.042249 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033363 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.033363 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.761553 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.761553 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.900946 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.900946 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092127 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092127 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.115668 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.115668 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038069 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038069 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042419 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.042419 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15506.791632 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15506.791632 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17747.134826 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17747.134826 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28390.678490 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 28390.678490 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15751.617962 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15751.617962 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21175.726324 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21175.726324 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 335833986 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 335833986 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 81837847 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 81837847 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 72225758 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 72225758 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 239509 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 239509 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 145455 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 145455 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1785819 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1785819 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1759762 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1759762 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 154063605 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 154063605 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 154303114 # number of overall hits +system.cpu1.dcache.overall_hits::total 154303114 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3469404 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3469404 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2254005 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2254005 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 641263 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 641263 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 468533 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 468533 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 172541 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 172541 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 196757 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 196757 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5723409 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5723409 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6364672 # number of overall misses +system.cpu1.dcache.overall_misses::total 6364672 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 51425230000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 51425230000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 38096829500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 38096829500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16555952500 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 16555952500 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2623224000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2623224000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4131954500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4131954500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2147500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2147500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 89522059500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 89522059500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 89522059500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 89522059500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 85307251 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 85307251 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 74479763 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 74479763 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 880772 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 880772 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 613988 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 613988 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1958360 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1958360 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1956519 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1956519 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 159787014 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 159787014 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 160667786 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 160667786 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040670 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.040670 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030263 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030263 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.728069 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.728069 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.763098 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.763098 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088105 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088105 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100565 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100565 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035819 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035819 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039614 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.039614 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14822.496890 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14822.496890 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16901.838949 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16901.838949 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35335.723418 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35335.723418 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15203.482071 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15203.482071 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21000.292239 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21000.292239 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16430.283101 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16430.283101 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14656.775030 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14656.775030 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15641.387764 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15641.387764 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14065.463153 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14065.463153 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1608,161 +1657,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3294639 # number of writebacks -system.cpu1.dcache.writebacks::total 3294639 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 376716 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 376716 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 934861 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 934861 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 50 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 50 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39920 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39920 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 26 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 26 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1311577 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1311577 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1311577 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1311577 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2830470 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2830470 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1314298 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1314298 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 659943 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 659943 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 426357 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 426357 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 121056 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 121056 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 201939 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 201939 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4144768 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4144768 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4804711 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4804711 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7026 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7026 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7515 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7515 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14541 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14541 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38398702439 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38398702439 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21764603493 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21764603493 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13372610673 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13372610673 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11459992206 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11459992206 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1620200910 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1620200910 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3963729421 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3963729421 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1148000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1148000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60163305932 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 60163305932 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 73535916605 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 73535916605 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 828088750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 828088750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 987688750 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 987688750 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1815777500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1815777500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037286 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037286 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019496 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019496 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.761219 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.761219 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.900841 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.900841 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069281 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069281 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.115653 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.115653 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028918 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028918 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033321 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033321 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13566.193049 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13566.193049 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16559.869598 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16559.869598 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20263.281333 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20263.281333 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26878.864909 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26878.864909 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13383.895966 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13383.895966 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19628.350249 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19628.350249 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3440440 # number of writebacks +system.cpu1.dcache.writebacks::total 3440440 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 392659 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 392659 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 925831 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 925831 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 46 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 46 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41204 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41204 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 43 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1318490 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1318490 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1318490 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1318490 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3076745 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3076745 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1328174 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1328174 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 640972 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 640972 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 468487 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 468487 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 131337 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 131337 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 196714 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 196714 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4404919 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4404919 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5045891 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5045891 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5366 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5366 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5280 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5280 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10646 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10646 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41480566500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41480566500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21714665000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21714665000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12811841000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12811841000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16084660000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16084660000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1751023000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1751023000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3933903500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3933903500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1830000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63195231500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 63195231500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 76007072500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 76007072500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 593786000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 593786000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 651165500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 651165500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1244951500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1244951500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036067 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036067 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017833 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017833 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.727739 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.727739 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.763023 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.763023 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067065 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067065 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100543 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100543 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027567 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027567 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031406 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031406 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13481.964381 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13481.964381 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16349.262220 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16349.262220 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19988.144568 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19988.144568 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 34333.204550 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 34333.204550 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13332.290215 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13332.290215 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19998.086054 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19998.086054 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14515.482153 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14515.482153 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15304.961444 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15304.961444 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117860.624822 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 117860.624822 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 131428.975383 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 131428.975383 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124872.945465 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124872.945465 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14346.513863 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14346.513863 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15063.161788 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15063.161788 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110657.100261 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110657.100261 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123326.799242 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 123326.799242 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116940.775878 # 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Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 9156821 # number of replacements +system.cpu1.icache.tags.tagsinuse 506.982135 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 237244674 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9157333 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.907617 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8375787773000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.982135 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990199 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990199 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 459058494 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 459058494 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 216759728 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 216759728 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 216759728 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 216759728 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 216759728 # number of overall hits -system.cpu1.icache.overall_hits::total 216759728 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8513013 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8513013 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8513013 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8513013 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8513013 # number of overall misses -system.cpu1.icache.overall_misses::total 8513013 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 85304905568 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 85304905568 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 85304905568 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 85304905568 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 85304905568 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 85304905568 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 225272741 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 225272741 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 225272741 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 225272741 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 225272741 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 225272741 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037790 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.037790 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037790 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.037790 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037790 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.037790 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10020.530401 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10020.530401 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10020.530401 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10020.530401 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10020.530401 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10020.530401 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 501961349 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 501961349 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 237244674 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 237244674 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 237244674 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 237244674 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 237244674 # number of overall hits +system.cpu1.icache.overall_hits::total 237244674 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 9157334 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 9157334 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 9157334 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 9157334 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 9157334 # number of overall misses +system.cpu1.icache.overall_misses::total 9157334 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 90409615500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 90409615500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 90409615500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 90409615500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 90409615500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 90409615500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 246402008 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 246402008 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 246402008 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 246402008 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 246402008 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 246402008 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037164 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.037164 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037164 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.037164 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037164 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.037164 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9872.918854 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9872.918854 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9872.918854 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9872.918854 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9872.918854 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9872.918854 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1771,241 +1820,257 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8513013 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8513013 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8513013 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8513013 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8513013 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 8513013 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 90 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 90 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 76768195856 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 76768195856 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 76768195856 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 76768195856 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 76768195856 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 76768195856 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8107000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8107000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8107000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8107000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037790 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037790 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037790 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.037790 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037790 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.037790 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9017.746814 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9017.746814 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9017.746814 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9017.746814 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9017.746814 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9017.746814 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90077.777778 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90077.777778 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90077.777778 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90077.777778 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9157334 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 9157334 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 9157334 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 9157334 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 9157334 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 9157334 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85830949000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 85830949000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85830949000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 85830949000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85830949000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 85830949000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8848000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8848000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8848000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8848000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037164 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.037164 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.037164 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9372.918908 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9372.918908 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9372.918908 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95139.784946 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95139.784946 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7158191 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7159863 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 1351 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7355033 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7356454 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 1193 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 847001 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2383886 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13587.340153 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 13938188 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2400056 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.807443 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10048790087250 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4939.758457 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 75.017087 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 74.049784 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4551.314512 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3187.549823 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 759.650489 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.301499 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004579 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004520 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.277790 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.194553 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.046365 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.829305 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1323 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14780 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 433 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 562 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1093 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4947 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2638 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5915 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080750 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.902100 # 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number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 7753793 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3475511 # number of overall hits -system.cpu1.l2cache.overall_hits::total 11874455 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11727 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8782 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 759220 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 998421 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1778150 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 251764 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 251764 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 136318 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 136318 # 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number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22071218543 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 43512796951 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 66406868973 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 449146209 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 373707270 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22071218543 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 43512796951 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 66406868973 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 501686 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 163974 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 8513013 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3611258 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 12789931 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3294638 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3294638 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 424954 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 424954 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 207214 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 207214 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 201938 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 201938 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1108855 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1108855 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 501686 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 163974 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 8513013 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4720113 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 13898786 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 501686 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163974 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 8513013 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4720113 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 13898786 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023375 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053557 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.089183 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.276475 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.139027 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.592450 # 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Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9890893366500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5242.566110 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 80.941753 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.247702 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3561.549924 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3753.026790 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 801.168735 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.319981 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004940 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005264 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1163 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5423 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4799 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3398 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.908081 # 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mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.086224 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.257602 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257602 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.583331 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.583331 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022220 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245384 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136831 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022220 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245384 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.197716 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26142.997438 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24691.283229 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48574.921562 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32389.394609 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32389.394609 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19532.523541 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19532.523541 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14695.402755 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14695.402755 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 937500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 937500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33990.973225 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33990.973225 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27653.845407 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25788.930330 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27653.845407 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31864.283112 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 109853.793054 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109497.154300 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123927.811045 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 123927.811045 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 117127.449969 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 116909.250906 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.185012 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33000.974564 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42844.691183 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20281.638720 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20281.638720 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.862293 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15343.862293 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 376499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 376499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33349.967224 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33349.967224 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22153.141840 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25787.655901 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25787.655901 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45475.391737 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45475.391737 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27206.226770 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25299.806196 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27206.226770 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29868.845908 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102654.211703 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102389.906576 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 115826.041667 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 115826.041667 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109186.924667 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 108995.995903 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 15573132 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13012901 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7515 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3294638 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1065592 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1119456 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 424954 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 452600 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 368137 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 473527 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1269149 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1115295 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17026205 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14595450 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 357835 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1096931 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 33076421 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 544838528 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 546511254 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1311792 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4013488 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1096675062 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5302361 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 23181233 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.250406 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.433247 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 927149 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13939785 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5280 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 7136333 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 14143122 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1073027 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 445884 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 351130 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 465721 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1873672 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1132302 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9157334 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6348630 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 574099 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 467371 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27470555 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17217135 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368278 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1176846 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 46232814 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 586075264 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 544882505 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1351280 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4317584 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1136626633 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 12009621 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 42070384 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.298426 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.457567 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 17376502 74.96% 74.96% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 5804731 25.04% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 29515487 70.16% 70.16% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 12554897 29.84% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 23181233 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 12806281931 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 42070384 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 18619089977 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 180531485 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 181245984 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 12781520856 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13738184900 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7568960857 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7905383000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 194234943 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 199375485 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 595690418 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 637173449 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40349 # Transaction distribution -system.iobus.trans_dist::ReadResp 40349 # Transaction distribution -system.iobus.trans_dist::WriteReq 136610 # Transaction distribution -system.iobus.trans_dist::WriteResp 29882 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47640 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40322 # Transaction distribution +system.iobus.trans_dist::ReadResp 40322 # Transaction distribution +system.iobus.trans_dist::WriteReq 136608 # Transaction distribution +system.iobus.trans_dist::WriteResp 136608 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47696 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2231,18 +2318,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122574 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122578 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231202 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231202 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47660 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353860 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47716 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2252,18 +2339,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155681 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155708 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338824 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496839 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36172000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496618 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36211000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2283,7 +2370,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2291,778 +2378,754 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 607512131 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 569805082 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92695000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92701000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148588668 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147898000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115637 # number of replacements -system.iocache.tags.tagsinuse 11.310069 # Cycle average of tags in use +system.iocache.tags.replacements 115582 # number of replacements +system.iocache.tags.tagsinuse 11.293791 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115653 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115598 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9129457632000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.399895 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.910174 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.462493 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.244386 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706879 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9174209621000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.830929 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.462862 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239433 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466429 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705862 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041045 # Number of tag accesses -system.iocache.tags.data_accesses 1041045 # Number of data accesses +system.iocache.tags.tag_accesses 1040766 # Number of tag accesses +system.iocache.tags.data_accesses 1040766 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8941 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8873 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8910 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8904 # number of demand (read+write) misses -system.iocache.demand_misses::total 8944 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8873 # number of demand (read+write) misses +system.iocache.demand_misses::total 8913 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8904 # number of overall misses -system.iocache.overall_misses::total 8944 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1622865167 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1628060667 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8873 # number of overall misses +system.iocache.overall_misses::total 8913 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1631093968 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1636288968 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19842621296 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19842621296 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1622865167 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1628429667 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1622865167 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1628429667 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12624582114 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12624582114 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1631093968 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1636657968 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1631093968 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1636657968 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8941 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8873 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8910 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8904 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8944 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8873 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8913 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8873 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8913 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182262.485063 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182089.326362 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183826.661558 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183646.348822 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185917.671989 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 185917.671989 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 182262.485063 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 182069.506597 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 182262.485063 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 182069.506597 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 110288 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118287.442040 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118287.442040 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183826.661558 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183625.936048 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 183826.661558 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183625.936048 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31363 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16227 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3550 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.796574 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.834648 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106703 # number of writebacks -system.iocache.writebacks::total 106703 # number of writebacks +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8904 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8941 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8873 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8910 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8904 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8944 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8873 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8913 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8904 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8944 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1158690425 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1161960925 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14292687374 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14292687374 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1158690425 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1162173925 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1158690425 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1162173925 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8873 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8913 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1187443968 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1190788968 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7288182114 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7288182114 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1187443968 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1191007968 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1187443968 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1191007968 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130131.449349 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 129958.721060 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133916.941890 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133916.941890 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 130131.449349 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 129938.945103 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 130131.449349 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 129938.945103 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133826.661558 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133646.348822 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68287.442040 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68287.442040 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 133826.661558 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 133625.936048 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 133826.661558 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 133625.936048 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1500558 # number of replacements -system.l2c.tags.tagsinuse 64423.791175 # Cycle average of tags in use -system.l2c.tags.total_refs 5010724 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1561220 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.209493 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8774171000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 18406.054563 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 163.983954 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 204.641755 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4710.197783 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8659.570147 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11639.948556 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 186.392680 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 219.831325 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3870.715230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6776.772016 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9585.683167 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.280854 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002502 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003123 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.071872 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.132135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.177612 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002844 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003354 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.059062 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.103405 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.146266 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983029 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9890 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50532 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 96 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 403 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9383 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 240 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1652 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 43541 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.150909 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.771057 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 65146304 # Number of tag accesses -system.l2c.tags.data_accesses 65146304 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6273 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4042 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 730934 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 606426 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 316069 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6330 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4616 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 702346 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 568034 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 305702 # number of ReadReq hits -system.l2c.ReadReq_hits::total 3250772 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2490573 # number of Writeback hits -system.l2c.Writeback_hits::total 2490573 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 135019 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 128371 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 263390 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 28214 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 29967 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 58181 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6140 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6184 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12324 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 50287 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53122 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 103409 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6273 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4042 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 730934 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 656713 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 316069 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6330 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4616 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 702346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 621156 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 305702 # number of demand (read+write) hits -system.l2c.demand_hits::total 3354181 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6273 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4042 # number of overall hits -system.l2c.overall_hits::cpu0.inst 730934 # number of overall hits -system.l2c.overall_hits::cpu0.data 656713 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 316069 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6330 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4616 # number of overall hits -system.l2c.overall_hits::cpu1.inst 702346 # number of overall hits -system.l2c.overall_hits::cpu1.data 621156 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 305702 # number of overall hits -system.l2c.overall_hits::total 3354181 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1959 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1699 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 72396 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 144803 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 235787 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2337 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2129 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 56871 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 125845 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 232153 # number of ReadReq misses -system.l2c.ReadReq_misses::total 875979 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 452629 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 114950 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 567579 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 49085 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 42979 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 92064 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 9286 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 8933 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 18219 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 81593 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 56532 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 138125 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1959 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1699 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 72396 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 226396 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 235787 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2337 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2129 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 56871 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 182377 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 232153 # number of demand (read+write) misses -system.l2c.demand_misses::total 1014104 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1959 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1699 # number of overall misses -system.l2c.overall_misses::cpu0.inst 72396 # number of overall misses -system.l2c.overall_misses::cpu0.data 226396 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 235787 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2337 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2129 # number of overall misses -system.l2c.overall_misses::cpu1.inst 56871 # number of overall misses -system.l2c.overall_misses::cpu1.data 182377 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 232153 # number of overall misses -system.l2c.overall_misses::total 1014104 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 183693028 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 155473534 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 6124405792 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 13529784764 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 31415388170 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 209221515 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 197082496 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4800216916 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 11513015623 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 30700473496 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 98828755334 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 50831909 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 41081201 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 91913110 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 314052545 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 253554995 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 567607540 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 59571609 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 53385310 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 112956919 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7326457212 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4778922810 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 12105380022 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 183693028 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 155473534 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 6124405792 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20856241976 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 31415388170 # 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Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1520944 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.105071 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 17020.262251 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 105.114677 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 114.825043 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4617.432955 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6910.402402 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7514.168760 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 272.316465 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 336.862323 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3976.770964 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9922.626808 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13024.323921 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.259709 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001604 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.001752 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.070456 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.105444 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.114657 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004155 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.005140 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2000 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4985 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 43502 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.147003 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003555 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.774567 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 74931302 # Number of tag accesses +system.l2c.tags.data_accesses 74931302 # Number of data accesses +system.l2c.Writeback_hits::writebacks 2473005 # number of Writeback hits +system.l2c.Writeback_hits::total 2473005 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 29717 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 30251 # 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number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 746511 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 321187 # number of demand (read+write) hits +system.l2c.demand_hits::total 3601028 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6955 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5054 # number of overall hits +system.l2c.overall_hits::cpu0.inst 704009 # number of overall hits +system.l2c.overall_hits::cpu0.data 771079 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 296922 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6236 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4142 # number of overall hits +system.l2c.overall_hits::cpu1.inst 738933 # number of overall hits +system.l2c.overall_hits::cpu1.data 746511 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 321187 # number of overall hits +system.l2c.overall_hits::total 3601028 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.238282 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.094352 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.451557 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.446368 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.264623 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.333977 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.063950 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.266924 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.393737 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.292149 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20782.672878 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.123136 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20770.697773 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20806.403659 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20800.429860 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20803.287207 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83747.368221 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76297.204102 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 82003.086666 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73437.114077 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81151.273568 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72948.231473 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78166.887712 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97540.588835 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73437.114077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83193.673125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72948.231473 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 77116.636438 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 90723.447575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73437.114077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83193.673125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72948.231473 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 77116.636438 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 90723.447575 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153783.741865 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84684.936614 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96859.005197 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148672.360201 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 98824.053030 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141763.341646 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151230.657412 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91698.703495 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 110147.934372 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 975380 # Transaction distribution -system.membus.trans_dist::ReadResp 975380 # Transaction distribution -system.membus.trans_dist::WriteReq 38492 # Transaction distribution -system.membus.trans_dist::WriteResp 38492 # Transaction distribution -system.membus.trans_dist::Writeback 1255244 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 671368 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 671368 # Transaction distribution -system.membus.trans_dist::UpgradeReq 435292 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 320448 # Transaction distribution -system.membus.trans_dist::UpgradeResp 117663 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution -system.membus.trans_dist::ReadExReq 151367 # Transaction distribution -system.membus.trans_dist::ReadExResp 133687 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122574 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 90631 # Transaction distribution +system.membus.trans_dist::ReadResp 933772 # Transaction distribution +system.membus.trans_dist::WriteReq 38095 # Transaction distribution +system.membus.trans_dist::WriteResp 38095 # Transaction distribution +system.membus.trans_dist::Writeback 1222852 # Transaction distribution +system.membus.trans_dist::CleanEvict 259291 # Transaction distribution +system.membus.trans_dist::UpgradeReq 429274 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 300804 # Transaction distribution +system.membus.trans_dist::UpgradeResp 113465 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 664837 # Transaction distribution +system.membus.trans_dist::ReadExResp 644660 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 843141 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122578 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5296349 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5445421 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335920 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335920 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5781341 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155681 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5299387 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5446901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5789694 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155708 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177552960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 177762857 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14095872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14095872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191858729 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 658635 # Total snoops (count) -system.membus.snoop_fanout::samples 3847839 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49768 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 169409152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 169615952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7274560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7274560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 176890512 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 639479 # Total snoops (count) +system.membus.snoop_fanout::samples 3957833 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3847839 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3957833 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3847839 # Request fanout histogram -system.membus.reqLayer0.occupancy 109654500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3957833 # Request fanout histogram +system.membus.reqLayer0.occupancy 109447997 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21898998 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20601500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 11397821385 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8645644788 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6506682845 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8381282870 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 152058832 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229327995 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3106,45 +3169,46 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 5105910 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5098639 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38492 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2490573 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 937823 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 830969 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 486096 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 332772 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 818868 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302211 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302211 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8322623 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6766752 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15089375 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 277489443 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 218349254 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 495838697 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1695482 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9694113 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.011945 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.108639 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 90633 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5042509 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38095 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3695900 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1651242 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 481742 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 313276 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 795018 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 104 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1145784 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1145784 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4959107 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8783138 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7404481 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 16187619 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 270950615 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 216626041 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 487576656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3318184 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 13892424 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.121763 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.327012 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9578315 98.81% 98.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115798 1.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 12200843 87.82% 87.82% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1691581 12.18% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9694113 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8435746901 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 13892424 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8859040198 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2506500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2520000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4797228870 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5187778836 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4287100444 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4493465928 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |