diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-12-05 00:11:25 +0000 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-12-05 00:11:25 +0000 |
| commit | bbcbe028fe904ec3f48b39e02c4a8fbc6f438699 (patch) | |
| tree | 2e3c780f3c56f844d4fb36b438c3691af198a02b /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual | |
| parent | 78275c9d2f918d245902c3c00a9486b4af8e8099 (diff) | |
| download | gem5-bbcbe028fe904ec3f48b39e02c4a8fbc6f438699.tar.xz | |
stats: Update to reflect changes to PCI handling
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual')
4 files changed, 2628 insertions, 2638 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini index ee909a18b..f4750f909 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -1615,10 +1615,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.realview.pciconfig.pio -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] @@ -1645,7 +1644,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[27] +cpu_side=system.iobus.master[25] mem_side=system.membus.slave[3] [system.iocache.tags] @@ -1809,12 +1808,9 @@ port=system.membus.master[5] [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=805306368 -pci_cfg_gen_offsets=true -pci_io_base=788529152 system=system [system.realview.aaci_fake] @@ -1907,16 +1903,15 @@ config_latency=20000 ctrl_offset=2 disks= eventq_index=0 +host=system.realview.pci_host io_shift=2 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[8] +pio=system.iobus.master[9] [system.realview.clcd] type=Pl111 @@ -1932,7 +1927,7 @@ pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] -pio=system.iobus.master[4] +pio=system.iobus.master[5] [system.realview.dcc] type=SubSystem @@ -2095,13 +2090,13 @@ eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 +host=system.realview.pci_host pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 -platform=system.realview rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -2111,9 +2106,8 @@ tx_fifo_size=393216 tx_read_delay=0 wb_comp_delay=10000 wb_delay=10000 -config=system.iobus.master[26] dma=system.iobus.slave[4] -pio=system.iobus.master[25] +pio=system.iobus.master[24] [system.realview.generic_timer] type=GenericTimer @@ -2155,7 +2149,7 @@ vnc=system.vncserver workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.ide] type=IdeController @@ -2236,14 +2230,13 @@ config_latency=20000 ctrl_offset=0 disks=system.cf0 eventq_index=0 +host=system.realview.pci_host io_shift=0 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[24] dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -2260,7 +2253,7 @@ pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.kmi1] type=Pl050 @@ -2275,7 +2268,7 @@ pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake @@ -2398,17 +2391,19 @@ null=false range=0:67108863 port=system.membus.master[1] -[system.realview.pciconfig] -type=PciConfigAll -bus=0 +[system.realview.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=805306368 +conf_device_bits=12 +conf_size=268435456 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=788529152 platform=system.realview -size=268435456 system=system -pio=system.iobus.default +pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl @@ -2460,7 +2455,7 @@ int_num1=34 pio_addr=470876160 pio_latency=100000 system=system -pio=system.iobus.master[2] +pio=system.iobus.master[3] [system.realview.timer1] type=Sp804 @@ -2475,7 +2470,7 @@ int_num1=35 pio_addr=470941696 pio_latency=100000 system=system -pio=system.iobus.master[3] +pio=system.iobus.master[4] [system.realview.uart] type=Pl011 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout index 7b7bd2fbd..207c42573 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 3 2015 15:48:05 -gem5 started Dec 3 2015 18:19:04 -gem5 executing on e104799-lin, pid 6711 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual +gem5 compiled Dec 4 2015 11:13:17 +gem5 started Dec 4 2015 12:36:35 +gem5 executing on e104799-lin, pid 5221 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47381662864000 because m5_exit instruction encountered +Exiting @ tick 47381683294000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 331b8e7fb..b300e6060 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.381663 # Number of seconds simulated -sim_ticks 47381662864000 # Number of ticks simulated -final_tick 47381662864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.381683 # Number of seconds simulated +sim_ticks 47381683294000 # Number of ticks simulated +final_tick 47381683294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132815 # Simulator instruction rate (inst/s) -host_op_rate 156205 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7502885455 # Simulator tick rate (ticks/s) -host_mem_usage 760860 # Number of bytes of host memory used -host_seconds 6315.13 # Real time elapsed on the host -sim_insts 838745469 # Number of instructions simulated -sim_ops 986455629 # Number of ops (including micro ops) simulated +host_inst_rate 169119 # Simulator instruction rate (inst/s) +host_op_rate 198983 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9178439782 # Simulator tick rate (ticks/s) +host_mem_usage 757568 # Number of bytes of host memory used +host_seconds 5162.28 # Real time elapsed on the host +sim_insts 873041938 # Number of instructions simulated +sim_ops 1027205539 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 42368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 41792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 6976384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 35367624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 9096640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 59520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 61888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3056960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 12429456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 7583744 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 432640 # Number of bytes read from this memory -system.physmem.bytes_read::total 75149016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 6976384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3056960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10033344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 59523200 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 85568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 75648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7273408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 37833736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 11654720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 106816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 96448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3691584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 15254352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 10772160 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 424448 # Number of bytes read from this memory +system.physmem.bytes_read::total 87268888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7273408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3691584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10964992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 68656704 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 59543784 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 662 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 653 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 109006 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 552632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 142135 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 930 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 47765 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 194223 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 118496 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6760 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1174229 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 930050 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 68677288 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1182 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 113647 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 591165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 182105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1669 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1507 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 57681 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 238362 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 168315 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6632 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1363602 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1072761 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 932624 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 147238 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 746441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 191987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 262326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 160057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1586036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 147238 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64518 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 211756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1256250 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1075335 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1806 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 153507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 798489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 245975 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77912 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 321946 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 227349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1841828 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 153507 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77912 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 231418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1449014 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1256684 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1256250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 147238 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 746876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 191987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 262326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 160057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2842720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1174229 # Number of read requests accepted -system.physmem.writeReqs 932624 # Number of write requests accepted -system.physmem.readBursts 1174229 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 932624 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 75113152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 37504 # Total number of bytes read from write queue -system.physmem.bytesWritten 59543040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 75149016 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 59543784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 586 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1449448 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1449014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 153507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 798923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 245975 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77912 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 321946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 227349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3291276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1363603 # Number of read requests accepted +system.physmem.writeReqs 1075335 # Number of write requests accepted +system.physmem.readBursts 1363603 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1075335 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 87237120 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 33472 # Total number of bytes read from write queue +system.physmem.bytesWritten 68675712 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 87268952 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 68677288 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 523 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 448232 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 71067 # Per bank write bursts -system.physmem.perBankRdBursts::1 73380 # Per bank write bursts -system.physmem.perBankRdBursts::2 69314 # Per bank write bursts -system.physmem.perBankRdBursts::3 74537 # Per bank write bursts -system.physmem.perBankRdBursts::4 66547 # Per bank write bursts -system.physmem.perBankRdBursts::5 79030 # Per bank write bursts -system.physmem.perBankRdBursts::6 66275 # Per bank write bursts -system.physmem.perBankRdBursts::7 68082 # Per bank write bursts -system.physmem.perBankRdBursts::8 68948 # Per bank write bursts -system.physmem.perBankRdBursts::9 127738 # Per bank write bursts -system.physmem.perBankRdBursts::10 63222 # Per bank write bursts -system.physmem.perBankRdBursts::11 73993 # Per bank write bursts -system.physmem.perBankRdBursts::12 67075 # Per bank write bursts -system.physmem.perBankRdBursts::13 69321 # Per bank write bursts -system.physmem.perBankRdBursts::14 63089 # Per bank write bursts -system.physmem.perBankRdBursts::15 72025 # Per bank write bursts -system.physmem.perBankWrBursts::0 57427 # Per bank write bursts -system.physmem.perBankWrBursts::1 61393 # Per bank write bursts -system.physmem.perBankWrBursts::2 59144 # Per bank write bursts -system.physmem.perBankWrBursts::3 61303 # Per bank write bursts -system.physmem.perBankWrBursts::4 56823 # Per bank write bursts -system.physmem.perBankWrBursts::5 63517 # Per bank write bursts -system.physmem.perBankWrBursts::6 54876 # Per bank write bursts -system.physmem.perBankWrBursts::7 56576 # Per bank write bursts -system.physmem.perBankWrBursts::8 56101 # Per bank write bursts -system.physmem.perBankWrBursts::9 62480 # Per bank write bursts -system.physmem.perBankWrBursts::10 54750 # Per bank write bursts -system.physmem.perBankWrBursts::11 61148 # Per bank write bursts -system.physmem.perBankWrBursts::12 54574 # Per bank write bursts -system.physmem.perBankWrBursts::13 57375 # Per bank write bursts -system.physmem.perBankWrBursts::14 53605 # Per bank write bursts -system.physmem.perBankWrBursts::15 59268 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 497625 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 80650 # Per bank write bursts +system.physmem.perBankRdBursts::1 88729 # Per bank write bursts +system.physmem.perBankRdBursts::2 73569 # Per bank write bursts +system.physmem.perBankRdBursts::3 80330 # Per bank write bursts +system.physmem.perBankRdBursts::4 79168 # Per bank write bursts +system.physmem.perBankRdBursts::5 89219 # Per bank write bursts +system.physmem.perBankRdBursts::6 76757 # Per bank write bursts +system.physmem.perBankRdBursts::7 80146 # Per bank write bursts +system.physmem.perBankRdBursts::8 80110 # Per bank write bursts +system.physmem.perBankRdBursts::9 145487 # Per bank write bursts +system.physmem.perBankRdBursts::10 85462 # Per bank write bursts +system.physmem.perBankRdBursts::11 91495 # Per bank write bursts +system.physmem.perBankRdBursts::12 74671 # Per bank write bursts +system.physmem.perBankRdBursts::13 80575 # Per bank write bursts +system.physmem.perBankRdBursts::14 75276 # Per bank write bursts +system.physmem.perBankRdBursts::15 81436 # Per bank write bursts +system.physmem.perBankWrBursts::0 65415 # Per bank write bursts +system.physmem.perBankWrBursts::1 72062 # Per bank write bursts +system.physmem.perBankWrBursts::2 62920 # Per bank write bursts +system.physmem.perBankWrBursts::3 67234 # Per bank write bursts +system.physmem.perBankWrBursts::4 65543 # Per bank write bursts +system.physmem.perBankWrBursts::5 71204 # Per bank write bursts +system.physmem.perBankWrBursts::6 63108 # Per bank write bursts +system.physmem.perBankWrBursts::7 65618 # Per bank write bursts +system.physmem.perBankWrBursts::8 64627 # Per bank write bursts +system.physmem.perBankWrBursts::9 73983 # Per bank write bursts +system.physmem.perBankWrBursts::10 67070 # Per bank write bursts +system.physmem.perBankWrBursts::11 71654 # Per bank write bursts +system.physmem.perBankWrBursts::12 63584 # Per bank write bursts +system.physmem.perBankWrBursts::13 67795 # Per bank write bursts +system.physmem.perBankWrBursts::14 63419 # Per bank write bursts +system.physmem.perBankWrBursts::15 67822 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 47381660751500 # Total gap between requests +system.physmem.numWrRetry 20 # Number of times write queue was full causing retry +system.physmem.totGap 47381681282500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1174199 # Read request sizes (log2) +system.physmem.readPktSize::6 1363573 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 930050 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 756841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 295232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 26539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 15837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 14079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 12670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 10425 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1072761 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 866656 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 332331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 26767 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 20794 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 18575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 16649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 13953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -188,164 +188,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 18671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 45390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 50223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 52287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 55018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 55938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 58169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 58483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 59754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 64501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 59690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 64110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 58190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 54561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 52990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 18197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 20578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 39692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 50721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 56749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 63294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 64512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 67169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 67826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 69607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 74517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 70375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 69942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 75013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 68273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 64139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 363 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 104 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 709891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 189.684557 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 114.673344 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 252.164844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 431942 60.85% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 132623 18.68% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44376 6.25% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24102 3.40% 89.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15088 2.13% 91.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9957 1.40% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7669 1.08% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7642 1.08% 94.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 36492 5.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 709891 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 51534 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.773974 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 380.344580 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 51531 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::59 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 845070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 184.496716 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 112.937858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 245.074486 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 518646 61.37% 61.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 158346 18.74% 80.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53030 6.28% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28124 3.33% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18210 2.15% 91.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11789 1.40% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8638 1.02% 94.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8488 1.00% 95.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 39799 4.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 845070 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60101 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.679190 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 352.199560 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 60098 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 51534 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 51534 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.053324 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.386136 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.764507 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 48029 93.20% 93.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1359 2.64% 95.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 210 0.41% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 316 0.61% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 77 0.15% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 304 0.59% 97.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 196 0.38% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 89 0.17% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 103 0.20% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 90 0.17% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 42 0.08% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 57 0.11% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 406 0.79% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 44 0.09% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 34 0.07% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 103 0.20% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 21 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 20 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 51534 # Writes before turning the bus around for reads -system.physmem.totQLat 26583019130 # Total ticks spent queuing -system.physmem.totMemAccLat 48588825380 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5868215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22650.00 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60101 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60101 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.854245 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.273539 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.223401 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 56328 93.72% 93.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1584 2.64% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 235 0.39% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 339 0.56% 97.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 81 0.13% 97.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 304 0.51% 97.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 166 0.28% 98.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 108 0.18% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 84 0.14% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 101 0.17% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 39 0.06% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 59 0.10% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 433 0.72% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 41 0.07% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 33 0.05% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 91 0.15% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 21 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 26 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60101 # Writes before turning the bus around for reads +system.physmem.totQLat 33864601554 # Total ticks spent queuing +system.physmem.totMemAccLat 59422351554 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6815400000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24844.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41400.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.59 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.59 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.26 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43594.18 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.83 # Average write queue length when enqueuing -system.physmem.readRowHits 952385 # Number of row buffer hits during reads -system.physmem.writeRowHits 441721 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.48 # Row buffer hit rate for writes -system.physmem.avgGap 22489305.50 # Average gap between requests -system.physmem.pageHitRate 66.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2710380960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1478878500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4432209600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3052442880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3094739659440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1177500235590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27396100823250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31680014630220 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.613444 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45575607610794 # Time in different power states -system.physmem_0.memoryStateTime::REF 1582177740000 # Time in different power states +system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing +system.physmem.readRowHits 1093420 # Number of row buffer hits during reads +system.physmem.writeRowHits 497646 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 46.38 # Row buffer hit rate for writes +system.physmem.avgGap 19427177.44 # Average gap between requests +system.physmem.pageHitRate 65.31 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3178488600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1734294375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5058697800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3454513920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3094741185120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1187868500820 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27387019861500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31683055542135 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.677294 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45560417443643 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582178520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 223874273456 # Time in different power states +system.physmem_0.memoryStateTime::ACT 239087007607 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2656364760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1449405375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4722003000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2976166800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3094739659440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1182079758375 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27392083725750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31680707083500 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.628058 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45568857815114 # Time in different power states -system.physmem_1.memoryStateTime::REF 1582177740000 # Time in different power states +system.physmem_1.actEnergy 3210233040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1751615250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5573178000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3498901920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3094741185120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1203743481615 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27373094439750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31685613034695 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.731270 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45537111526279 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582178520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 230624127636 # Time in different power states +system.physmem_1.memoryStateTime::ACT 262392956221 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -379,15 +379,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 125258409 # Number of BP lookups -system.cpu0.branchPred.condPredicted 88001025 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5802079 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 93100413 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 67841086 # Number of BTB hits +system.cpu0.branchPred.lookups 132357688 # Number of BP lookups +system.cpu0.branchPred.condPredicted 93633614 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5912907 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 98988393 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 72530253 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.868727 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15085862 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1028654 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.271472 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15763072 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1049472 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -418,61 +418,64 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 252652 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 252652 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 7537 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 66702 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 252652 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 252652 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 252652 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 74239 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22181.016716 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 20809.120487 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 13879.929548 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 73678 99.24% 99.24% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 179 0.24% 99.49% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 332 0.45% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 14 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 15 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 74239 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 265700 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 265700 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9033 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 73083 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 265700 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 265700 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 265700 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 82116 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22524.489746 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 20895.928471 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16961.244602 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 81335 99.05% 99.05% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 195 0.24% 99.29% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 500 0.61% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 20 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 22 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 15 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 82116 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 66702 89.85% 89.85% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 7537 10.15% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 74239 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 252652 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 73083 89.00% 89.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9033 11.00% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 82116 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 265700 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 252652 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 74239 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 265700 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 82116 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 74239 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 326891 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 82116 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 347816 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 81678885 # DTB read hits -system.cpu0.dtb.read_misses 209727 # DTB read misses -system.cpu0.dtb.write_hits 70936828 # DTB write hits -system.cpu0.dtb.write_misses 42925 # DTB write misses +system.cpu0.dtb.read_hits 86394812 # DTB read hits +system.cpu0.dtb.read_misses 220998 # DTB read misses +system.cpu0.dtb.write_hits 74903999 # DTB write hits +system.cpu0.dtb.write_misses 44702 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 33720 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8048 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 37665 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1452 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8673 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9709 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 81888612 # DTB read accesses -system.cpu0.dtb.write_accesses 70979753 # DTB write accesses +system.cpu0.dtb.perms_faults 10301 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 86615810 # DTB read accesses +system.cpu0.dtb.write_accesses 74948701 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 152615713 # DTB hits -system.cpu0.dtb.misses 252652 # DTB misses -system.cpu0.dtb.accesses 152868365 # DTB accesses +system.cpu0.dtb.hits 161298811 # DTB hits +system.cpu0.dtb.misses 265700 # DTB misses +system.cpu0.dtb.accesses 161564511 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -502,191 +505,191 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 57977 # Table walker walks requested -system.cpu0.itb.walker.walksLong 57977 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 503 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 46742 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 57977 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 57977 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 57977 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 47245 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 24873.087099 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23068.832563 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17067.215870 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 43882 92.88% 92.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 2853 6.04% 98.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 11 0.02% 98.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 288 0.61% 99.55% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 169 0.36% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 7 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 4 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 13 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 59769 # Table walker walks requested +system.cpu0.itb.walker.walksLong 59769 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 498 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49758 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 59769 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 59769 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 59769 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 50256 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25230.221267 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23083.004989 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19430.494891 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 46691 92.91% 92.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2859 5.69% 98.60% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 7 0.01% 98.61% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 383 0.76% 99.37% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 254 0.51% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 9 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 4 0.01% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 25 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 8 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 47245 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 50256 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 46742 98.94% 98.94% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 503 1.06% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 47245 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 49758 99.01% 99.01% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 498 0.99% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 50256 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57977 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57977 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59769 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59769 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 47245 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 47245 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 105222 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 224840362 # ITB inst hits -system.cpu0.itb.inst_misses 57977 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50256 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50256 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 110025 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 238646690 # ITB inst hits +system.cpu0.itb.inst_misses 59769 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24328 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 27225 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 193753 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 203945 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 224898339 # ITB inst accesses -system.cpu0.itb.hits 224840362 # DTB hits -system.cpu0.itb.misses 57977 # DTB misses -system.cpu0.itb.accesses 224898339 # DTB accesses -system.cpu0.numCycles 954325944 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 238706459 # ITB inst accesses +system.cpu0.itb.hits 238646690 # DTB hits +system.cpu0.itb.misses 59769 # DTB misses +system.cpu0.itb.accesses 238706459 # DTB accesses +system.cpu0.numCycles 1007854766 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 417810947 # Number of instructions committed -system.cpu0.committedOps 490605107 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 41344261 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4694 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93809718025 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.284109 # CPI: cycles per instruction -system.cpu0.ipc 0.437807 # IPC: instructions per cycle +system.cpu0.committedInsts 441362500 # Number of instructions committed +system.cpu0.committedOps 518398273 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 43962057 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 5117 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93756283149 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.283508 # CPI: cycles per instruction +system.cpu0.ipc 0.437923 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4756 # number of quiesce instructions executed -system.cpu0.tickCycles 674001287 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 280324657 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5190067 # number of replacements -system.cpu0.dcache.tags.tagsinuse 482.757722 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 144829115 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5190578 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.902310 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 5202 # number of quiesce instructions executed +system.cpu0.tickCycles 710760418 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 297094348 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5529190 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.574807 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 153025870 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5529699 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.673454 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.757722 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.942886 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.942886 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 307937411 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 307937411 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 74836049 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 74836049 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 65744025 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 65744025 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 248898 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 248898 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 135683 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 135683 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1688860 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1688860 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1659238 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1659238 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 140580074 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 140580074 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 140828972 # number of overall hits -system.cpu0.dcache.overall_hits::total 140828972 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3204136 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3204136 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2171939 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2171939 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 583430 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 583430 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 728874 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 728874 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 150550 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 150550 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 178568 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 178568 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5376075 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5376075 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5959505 # number of overall misses -system.cpu0.dcache.overall_misses::total 5959505 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 51043675000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 51043675000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55065851500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 55065851500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 67163849000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 67163849000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2254990500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2254990500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5008928500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5008928500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5076500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5076500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 106109526500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 106109526500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 106109526500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 106109526500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 78040185 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 78040185 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 67915964 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 67915964 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 832328 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 832328 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 864557 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 864557 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1839410 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1839410 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1837806 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1837806 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 145956149 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 145956149 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 146788477 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 146788477 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041058 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.041058 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031980 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.031980 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.700962 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.700962 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843061 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.843061 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.081847 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.081847 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097164 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097164 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036833 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.036833 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040599 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.040599 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15930.558191 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15930.558191 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25353.314020 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25353.314020 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 92147.406822 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 92147.406822 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14978.349386 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14978.349386 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28050.538170 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28050.538170 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.574807 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938623 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.938623 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 325514940 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 325514940 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 79084139 # 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number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2562226000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2562226000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5482087500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5482087500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5099500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5099500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 115804493500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 115804493500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 115804493500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 115804493500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 82522561 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 82522561 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 71731631 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 71731631 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 884756 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 884756 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 893053 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 893053 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1958770 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1958770 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1957065 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1957065 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 154254192 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 154254192 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 155138948 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 155138948 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041666 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.041666 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031873 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.031873 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.715416 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.715416 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.839436 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.839436 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085711 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085711 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099542 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099542 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037112 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.037112 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040981 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.040981 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16664.923910 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16664.923910 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25588.804094 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25588.804094 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 92146.429519 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 92146.429519 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15261.519584 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15261.519584 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28140.688363 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28140.688363 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19737.359784 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19737.359784 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17805.090607 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17805.090607 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20228.873220 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20228.873220 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18214.892393 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18214.892393 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -695,161 +698,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 5190079 # number of writebacks -system.cpu0.dcache.writebacks::total 5190079 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 389569 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 389569 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 893829 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 893829 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 64 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 64 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40085 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 40085 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 63 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 63 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1283398 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1283398 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1283398 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1283398 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2814567 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2814567 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1278110 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1278110 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 581694 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 581694 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 728810 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 728810 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 110465 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 110465 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 178505 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 178505 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4092677 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4092677 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4674371 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4674371 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16748 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16748 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18251 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18251 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34999 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34999 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40095557000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40095557000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32063318500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 32063318500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14032843000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14032843000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 66427837000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 66427837000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1488538500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1488538500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4826102000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4826102000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4518500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4518500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 72158875500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 72158875500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 86191718500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 86191718500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3021431000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3021431000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3257996500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3257996500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6279427500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6279427500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036066 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036066 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018819 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018819 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.698876 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.698876 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.842987 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.842987 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060055 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060055 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097129 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097129 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028040 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028040 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031844 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031844 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14245.728384 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14245.728384 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25086.509377 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25086.509377 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24124.097893 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.097893 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 91145.616827 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 91145.616827 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13475.204816 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13475.204816 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27036.228677 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27036.228677 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5529208 # number of writebacks +system.cpu0.dcache.writebacks::total 5529208 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 425438 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 425438 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 937459 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 937459 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 53 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 53 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41154 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41154 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 15 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 15 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1362897 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1362897 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1362897 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1362897 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3012984 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3012984 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1348832 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1348832 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 631309 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 631309 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 749608 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 749608 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126734 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126734 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194795 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 194795 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4361816 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4361816 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4993125 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4993125 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15485 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15485 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16430 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16430 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31915 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31915 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44936822000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44936822000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34248227000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34248227000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15688131000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15688131000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 68324152500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 68324152500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1728085500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1728085500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5286161500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5286161500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5009500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5009500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 79185049000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 79185049000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94873180000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 94873180000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2777500000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2777500000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2891122000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2891122000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5668622000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5668622000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036511 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036511 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018804 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018804 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.713540 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.713540 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.839377 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.839377 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064701 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064701 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099534 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099534 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028277 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028277 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032185 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032185 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14914.391182 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14914.391182 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25391.024976 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25391.024976 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24850.162123 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24850.162123 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 91146.509242 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 91146.509242 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13635.531901 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13635.531901 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27137.049206 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27137.049206 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17631.216805 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17631.216805 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18439.212142 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18439.212142 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180405.481251 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180405.481251 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178510.574763 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 178510.574763 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179417.340495 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179417.340495 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18154.147034 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18154.147034 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19000.762048 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19000.762048 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179367.129480 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179367.129480 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175966.037736 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175966.037736 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177616.230613 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177616.230613 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 8911456 # number of replacements +system.cpu0.icache.tags.replacements 8961850 # number of replacements system.cpu0.icache.tags.tagsinuse 511.890744 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 215729294 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 8911968 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.206695 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 229474819 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 8962362 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 25.604279 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 40343615000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890744 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999787 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 458194521 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 458194521 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 215729294 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 215729294 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 215729294 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 215729294 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 215729294 # number of overall hits -system.cpu0.icache.overall_hits::total 215729294 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 8911978 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 8911978 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 8911978 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 8911978 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 8911978 # number of overall misses -system.cpu0.icache.overall_misses::total 8911978 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92482342000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 92482342000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 92482342000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 92482342000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 92482342000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 92482342000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 224641272 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 224641272 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 224641272 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 224641272 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 224641272 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 224641272 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039672 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.039672 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039672 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.039672 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039672 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.039672 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10377.308158 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10377.308158 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10377.308158 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10377.308158 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10377.308158 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10377.308158 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 485836753 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 485836753 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 229474819 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 229474819 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 229474819 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 229474819 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 229474819 # number of overall hits +system.cpu0.icache.overall_hits::total 229474819 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 8962372 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 8962372 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 8962372 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 8962372 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 8962372 # number of overall misses +system.cpu0.icache.overall_misses::total 8962372 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94471116000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 94471116000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 94471116000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 94471116000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 94471116000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 94471116000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 238437191 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 238437191 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 238437191 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 238437191 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 238437191 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 238437191 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037588 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.037588 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037588 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.037588 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037588 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.037588 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10540.860835 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10540.860835 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10540.860835 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10540.860835 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10540.860835 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10540.860835 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -858,499 +861,491 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 8911456 # number of writebacks -system.cpu0.icache.writebacks::total 8911456 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8911978 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 8911978 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 8911978 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 8911978 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 8911978 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 8911978 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 8961850 # number of writebacks +system.cpu0.icache.writebacks::total 8961850 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8962372 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 8962372 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 8962372 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 8962372 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8962372 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 8962372 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 88026353500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 88026353500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88026353500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 88026353500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 88026353500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 88026353500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89989930500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 89989930500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89989930500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 89989930500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89989930500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 89989930500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039672 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039672 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039672 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.039672 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039672 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.039672 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9877.308214 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9877.308214 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9877.308214 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037588 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037588 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037588 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.037588 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037588 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.037588 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10040.860890 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10040.860890 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10040.860890 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10040.860890 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10040.860890 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10040.860890 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7009428 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7009488 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 54 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7773827 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7774021 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 173 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 921168 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2475518 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16200.233462 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 22065601 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2491662 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 8.855776 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1015459 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2700718 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16213.055668 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 22438549 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2716794 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 8.259201 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 9049945000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15248.600129 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 44.173698 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 44.219033 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 863.240603 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.930701 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002696 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002699 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.052688 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.988784 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1264 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14832 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 796 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 176 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 279 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 32 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1045 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5479 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6042 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2161 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.077148 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002930 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.905273 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 474836128 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 474836128 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 472021 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 147981 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 620002 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3408595 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3408595 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 10690717 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 10690717 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 115 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 115 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 789207 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 789207 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8250320 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 8250320 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2605662 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2605662 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 165539 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 165539 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 472021 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 147981 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 8250320 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3394869 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 12265191 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 472021 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 147981 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 8250320 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3394869 # number of overall hits -system.cpu0.l2cache.overall_hits::total 12265191 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10450 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7208 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 17658 # number of ReadReq misses -system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses -system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 242851 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 242851 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 178501 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 178501 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 254335 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 254335 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 661657 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 661657 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 900762 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 900762 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 561341 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 561341 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10450 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7208 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 661657 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1155097 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1834412 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10450 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7208 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 661657 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1155097 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1834412 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 323189500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 243712500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 566902000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3278340000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 3278340000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1776981500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1776981500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4439499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4439499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15942119997 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 15942119997 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 24805875000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 24805875000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33147375490 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 33147375490 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 64101878000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 64101878000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 323189500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 243712500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 24805875000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 49089495487 # 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number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3820823499 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4591998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4591998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14771566500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14771566500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 22450783500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 22450783500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 32316263992 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 32316263992 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 62472768000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 62472768000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 364821500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 277497500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 22450783500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 47087830492 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 70180932992 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 364821500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 277497500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 22450783500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 47087830492 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 35765340066 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 105946273058 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2887260500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9883415500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3121073500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3121073500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2653464500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9649619500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2767850000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2767850000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6008334000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 13004489000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027689 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses -system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5421314500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12417469500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028229 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999527 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999527 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998643 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998643 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.239772 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.239772 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.074243 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.256623 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.256623 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772261 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772261 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252758 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.129745 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252758 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.242429 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.242429 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079332 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.260815 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.260815 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.775614 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.775614 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256661 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.136550 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256661 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.178601 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26106.536022 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41102.047113 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30802.220271 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30802.220271 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19512.736623 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19512.736623 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1031874.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1031874.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55487.890257 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.890257 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31490.545606 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30754.680317 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30754.680317 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108194.184996 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108194.184996 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36135.828071 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34358.895348 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36135.828071 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36203.474366 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.189248 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34093.365180 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46802.000652 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46802.000652 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31159.903678 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31159.903678 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19615.493408 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19615.493408 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 510222 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 510222 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55365.484012 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55365.484012 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31576.214868 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32859.363553 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32859.363553 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 107694.400725 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 107694.400725 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37662.039004 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35442.839203 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37662.039004 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46802.000652 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38605.937054 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172394.345594 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143119.676499 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171008.355707 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171008.355707 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171357.087504 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142337.367614 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168463.177115 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 168463.177115 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171671.590617 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 148949.569341 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169867.288109 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 147433.860895 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 29004574 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14815953 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2223 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1990994 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1990568 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 426 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 781840 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 13286786 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 18251 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 18251 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 4847792 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 10690718 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2645908 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 891756 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 444613 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 320296 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 480335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 85 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1119465 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1052013 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 8911978 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4503059 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 735449 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 726880 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 26838850 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16809682 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 328338 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1022103 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 44998973 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1143972032 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 629474552 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1241512 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3859768 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1778547864 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6630650 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 21811897 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.104823 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.306390 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 29837081 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 15255646 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2671 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2145858 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2145409 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 449 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 816702 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 13639128 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 16430 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 16430 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5128977 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 10898588 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2922524 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 983530 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 456186 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 346923 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 512261 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1174017 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1108975 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 8962372 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4744543 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 755832 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 747915 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 26989618 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17891664 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 337201 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1079102 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 46297585 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1150395968 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671911459 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1269832 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4069344 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1827646603 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7092856 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 22718303 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.108382 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.310926 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 19525925 89.52% 89.52% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2285546 10.48% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 426 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 20256496 89.16% 89.16% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2461358 10.83% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 449 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 21811897 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 28866629481 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 22718303 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 29677749987 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 172367004 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 177431926 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 13449935466 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 13525621280 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7428549534 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7933800899 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 173196405 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 178529385 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 539756748 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 570584194 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 127068265 # Number of BP lookups -system.cpu1.branchPred.condPredicted 89752795 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6099791 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 94409743 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 68319168 # Number of BTB hits +system.cpu1.branchPred.lookups 131141392 # Number of BP lookups +system.cpu1.branchPred.condPredicted 92458444 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6313157 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 97645974 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 70218111 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.364531 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 15069899 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 999135 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 71.910913 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15567912 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1046402 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1380,62 +1375,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 271482 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 271482 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7964 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78105 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 271482 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 271482 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 271482 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 86069 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22755.010515 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21243.396519 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15660.005020 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 85331 99.14% 99.14% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 168 0.20% 99.34% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 495 0.58% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 14 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 20 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 22 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 286101 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 286101 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9457 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80855 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 286101 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 286101 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 286101 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 90312 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23344.699486 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21447.607691 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 19228.959334 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 89271 98.85% 98.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 163 0.18% 99.03% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 728 0.81% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 35 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 43 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 28 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 30 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 86069 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 90312 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 527505760 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 527505760 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 527505760 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 78105 90.75% 90.75% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 7964 9.25% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 86069 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 271482 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 80855 89.53% 89.53% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9457 10.47% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 90312 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 286101 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 271482 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86069 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 286101 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90312 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86069 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 357551 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 376413 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 82675138 # DTB read hits -system.cpu1.dtb.read_misses 225741 # DTB read misses -system.cpu1.dtb.write_hits 73180273 # DTB write hits -system.cpu1.dtb.write_misses 45741 # DTB write misses +system.cpu1.dtb.read_hits 84597106 # DTB read hits +system.cpu1.dtb.read_misses 236435 # DTB read misses +system.cpu1.dtb.write_hits 75395592 # DTB write hits +system.cpu1.dtb.write_misses 49666 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37272 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1666 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8268 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 35920 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1878 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8819 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11369 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 82900879 # DTB read accesses -system.cpu1.dtb.write_accesses 73226014 # DTB write accesses +system.cpu1.dtb.perms_faults 11434 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 84833541 # DTB read accesses +system.cpu1.dtb.write_accesses 75445258 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 155855411 # DTB hits -system.cpu1.dtb.misses 271482 # DTB misses -system.cpu1.dtb.accesses 156126893 # DTB accesses +system.cpu1.dtb.hits 159992698 # DTB hits +system.cpu1.dtb.misses 286101 # DTB misses +system.cpu1.dtb.accesses 160278799 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1465,186 +1461,186 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 69604 # Table walker walks requested -system.cpu1.itb.walker.walksLong 69604 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 666 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61994 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 69604 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 69604 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 69604 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 62660 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25321.249601 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23483.555874 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 17582.582178 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 61881 98.76% 98.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 12 0.02% 98.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 712 1.14% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 23 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 70499 # Table walker walks requested +system.cpu1.itb.walker.walksLong 70499 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 664 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 63113 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 70499 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 70499 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 70499 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 63777 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26275.796917 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23950.266979 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 21020.894290 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 62694 98.30% 98.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 8 0.01% 98.31% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 977 1.53% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 22 0.03% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 42 0.07% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 28 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 62660 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 63777 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 526611260 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 526611260 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 526611260 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61994 98.94% 98.94% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 666 1.06% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 62660 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 63113 98.96% 98.96% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 664 1.04% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63777 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69604 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69604 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 70499 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 70499 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62660 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62660 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 132264 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 226404999 # ITB inst hits -system.cpu1.itb.inst_misses 69604 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63777 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63777 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 134276 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 232338774 # ITB inst hits +system.cpu1.itb.inst_misses 70499 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26762 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25488 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 203402 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 208774 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 226474603 # ITB inst accesses -system.cpu1.itb.hits 226404999 # DTB hits -system.cpu1.itb.misses 69604 # DTB misses -system.cpu1.itb.accesses 226474603 # DTB accesses -system.cpu1.numCycles 896249910 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 232409273 # ITB inst accesses +system.cpu1.itb.hits 232338774 # DTB hits +system.cpu1.itb.misses 70499 # DTB misses +system.cpu1.itb.accesses 232409273 # DTB accesses +system.cpu1.numCycles 934140798 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 420934522 # Number of instructions committed -system.cpu1.committedOps 495850522 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 42911431 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4588 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93867828238 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.129191 # CPI: cycles per instruction -system.cpu1.ipc 0.469662 # IPC: instructions per cycle +system.cpu1.committedInsts 431679438 # Number of instructions committed +system.cpu1.committedOps 508807266 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 44929639 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4564 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93829974504 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.163969 # CPI: cycles per instruction +system.cpu1.ipc 0.462114 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13511 # number of quiesce instructions executed -system.cpu1.tickCycles 680922299 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 215327611 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 4921419 # number of replacements -system.cpu1.dcache.tags.tagsinuse 458.899025 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 148299852 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4921931 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.130421 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 13472 # number of quiesce instructions executed +system.cpu1.tickCycles 702823433 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 231317365 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5070717 # number of replacements +system.cpu1.dcache.tags.tagsinuse 459.449189 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 152180192 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5071229 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.008543 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8388824602000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.899025 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.896287 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.896287 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 459.449189 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.897362 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.897362 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 313981831 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 313981831 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 76035057 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 76035057 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 68321160 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 68321160 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 232478 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 232478 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 184182 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 184182 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1549703 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1549703 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1524262 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1524262 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 144356217 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 144356217 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 144588695 # number of overall hits -system.cpu1.dcache.overall_hits::total 144588695 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3124160 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3124160 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2104338 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2104338 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 561771 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 561771 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 510720 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 510720 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 156544 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 156544 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 180437 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 180437 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5228498 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5228498 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5790269 # number of overall misses -system.cpu1.dcache.overall_misses::total 5790269 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 48221817000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 48221817000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 44559226500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 44559226500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 19302885000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 19302885000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2427765500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2427765500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5104015500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5104015500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 7589000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 7589000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 92781043500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 92781043500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 92781043500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 92781043500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 79159217 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 79159217 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 70425498 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 70425498 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 794249 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 794249 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 694902 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 694902 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1706247 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1706247 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1704699 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1704699 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 149584715 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 149584715 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 150378964 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 150378964 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039467 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.039467 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029880 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029880 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.707298 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.707298 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.734953 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.734953 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091748 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091748 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105847 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105847 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034953 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.034953 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.038505 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.038505 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15435.130403 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15435.130403 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21174.937914 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21174.937914 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37795.435855 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37795.435855 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15508.518372 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15508.518372 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28286.967196 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28286.967196 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 322309894 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 322309894 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 77705355 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 77705355 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 70371137 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 70371137 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 247594 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 247594 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 180643 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 180643 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1624088 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1624088 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1588942 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1588942 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 148076492 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 148076492 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 148324086 # number of overall hits +system.cpu1.dcache.overall_hits::total 148324086 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3222913 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3222913 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2183254 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2183254 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 592382 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 592382 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 513289 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 513289 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 153645 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 153645 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187516 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 187516 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5406167 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5406167 # 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average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5070732 # number of writebacks +system.cpu1.dcache.writebacks::total 5070732 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 348629 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 348629 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 899898 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 899898 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 110 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 110 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43396 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 43396 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 20 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 20 # 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number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21647 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21647 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 44342 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 44342 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41633767000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41633767000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 28169318500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 28169318500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14402198000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14402198000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20089556500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20089556500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1594381500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1594381500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5035777500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5035777500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4638000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4638000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69803085500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 69803085500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84205283500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 84205283500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4145895000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4145895000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4016889500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4016889500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8162784500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8162784500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035516 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035516 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017688 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017688 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.704731 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.704731 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.739523 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.739523 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062017 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062017 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105545 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105545 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027089 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027089 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030777 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030777 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14484.917635 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14484.917635 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21949.730628 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21949.730628 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24329.804361 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24329.804361 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 39147.269276 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 39147.269276 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14461.641375 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14461.641375 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26858.052972 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26858.052972 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16211.547240 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16211.547240 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16984.300519 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16984.300519 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185064.395752 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185064.395752 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187379.919221 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187379.919221 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186176.381360 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186176.381360 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16789.112453 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16789.112453 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17728.932265 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17728.932265 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182678.783873 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182678.783873 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 185563.334411 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 185563.334411 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 184086.971720 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 184086.971720 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 9409188 # number of replacements -system.cpu1.icache.tags.tagsinuse 506.684863 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 216784534 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9409700 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 23.038411 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 9965841 # number of replacements +system.cpu1.icache.tags.tagsinuse 506.684865 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 222156193 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9966353 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 22.290621 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8388652871500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.684863 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.684865 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989619 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.989619 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 461798168 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 461798168 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 216784534 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 216784534 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 216784534 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 216784534 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 216784534 # number of overall hits -system.cpu1.icache.overall_hits::total 216784534 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 9409700 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 9409700 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 9409700 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 9409700 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 9409700 # number of overall misses -system.cpu1.icache.overall_misses::total 9409700 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 95979801000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 95979801000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 95979801000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 95979801000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 95979801000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 95979801000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 226194234 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 226194234 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 226194234 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 226194234 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 226194234 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 226194234 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.041600 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.041600 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.041600 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.041600 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.041600 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.041600 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10200.091501 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10200.091501 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10200.091501 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10200.091501 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10200.091501 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10200.091501 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 474211445 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 474211445 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 222156193 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 222156193 # 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average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1816,254 +1812,256 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 9409188 # number of writebacks -system.cpu1.icache.writebacks::total 9409188 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9409700 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9409700 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9409700 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 9409700 # 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number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91274951000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 91274951000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91274951000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 91274951000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91274951000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 91274951000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 96192306000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 96192306000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 96192306000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 96192306000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 96192306000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 96192306000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12950500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12950500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12950500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 12950500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.041600 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.041600 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.041600 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9700.091501 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9700.091501 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9700.091501 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.042936 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.042936 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.042936 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.042936 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.042936 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.042936 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9651.705694 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9651.705694 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9651.705694 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9651.705694 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9651.705694 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9651.705694 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6599308 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6600409 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 970 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6510084 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6511152 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 939 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 793623 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2151198 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13377.061252 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 23203065 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2166951 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 10.707702 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9986150274500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12523.259690 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.377906 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 74.184237 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 713.239419 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.764359 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004051 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004528 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.043533 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.816471 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 985 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 109 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14659 # Occupied blocks per task id +system.cpu1.l2cache.prefetcher.pfSpanPage 783896 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2135895 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13423.461637 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 24573645 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2151628 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.420954 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9991507442000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 12589.805999 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.598025 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 73.072993 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 692.984620 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.768421 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004126 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004460 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.042296 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.819303 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 945 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 96 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14692 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 173 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 750 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 185 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 707 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 46 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1249 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4750 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8044 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 438 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.060120 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006653 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.894714 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 482635734 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 482635734 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 517404 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 182303 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 699707 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3095740 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3095740 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 11232116 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 11232116 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 197 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 197 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 799662 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 799662 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8718417 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 8718417 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2602566 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2602566 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 242267 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 242267 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 517404 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 182303 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 8718417 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3402228 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 12820352 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 517404 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 182303 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 8718417 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3402228 # number of overall hits -system.cpu1.l2cache.overall_hits::total 12820352 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10447 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7725 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 18172 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 203082 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 203082 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 180388 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 180388 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 239405 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 239405 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 691283 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 691283 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 862205 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 862205 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 266022 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 266022 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10447 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7725 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 691283 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1101610 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1811065 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10447 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7725 # 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number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 7003999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11577465998 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 11577465998 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24488845500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24488845500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 30668978480 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 30668978480 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 16284255500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 16284255500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 361003500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 296858500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24488845500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 42246444478 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 67393151978 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 361003500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 296858500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24488845500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 42246444478 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 67393151978 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 527851 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 190028 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 717879 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3095740 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3095740 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 11232116 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 11232116 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 203279 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 203279 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 180388 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 180388 # 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number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12214500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7174681000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7186895500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025312 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7818696500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7830911000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.024958 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999031 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999031 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998191 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998191 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226292 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226292 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073464 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248519 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248519 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.523368 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.523368 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243392 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.123409 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243392 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.218879 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.218879 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.066850 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245183 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245183 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.512572 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.512572 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.239077 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.116933 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.239077 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.169835 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30203.043311 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36118.703029 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32496.215800 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32496.215800 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19755.934430 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19755.934430 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1303599.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1303599.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 40767.089256 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 40767.089256 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29425.314202 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29525.390105 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29525.390105 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55213.942832 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55213.942832 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31936.723887 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30957.803939 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31936.723887 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32368.597869 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.162850 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38868.158020 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46447.148846 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46447.148846 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32424.723840 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32424.723840 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19335.311185 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19335.311185 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1405833 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1405833 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45218.858431 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45218.858431 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31542.063292 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33176.746514 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33176.746514 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 60939.383069 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 60939.383069 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35735.769518 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34215.212681 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35735.769518 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46447.148846 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37664.129796 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177059.252703 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176865.151948 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179877.200704 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179877.200704 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174673.298083 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174504.103217 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178060.978427 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 178060.978427 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178412.518029 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178308.328785 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 176327.105228 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 176236.913175 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 29428527 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15006964 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2768 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1972954 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1972589 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 365 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 814249 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13775310 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 19312 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 19312 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4142105 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 11232116 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2703238 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 874176 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 401941 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 322763 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 444037 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1114947 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1047219 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9409700 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4456605 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 514166 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 508289 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28226960 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15947748 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 397923 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1113211 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 45685842 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1204298752 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 609360975 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1520224 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4222808 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1819402759 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6269077 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 21677519 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.104647 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.306153 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 30858357 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15723821 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2528 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1980391 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1980008 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 383 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 850137 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 14487242 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 21647 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 21647 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4268815 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 11821046 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2688015 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 913599 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 423664 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 342986 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 458900 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1168045 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1089891 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9966353 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4640105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 517058 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 511224 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 29897221 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16450144 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 405579 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1179409 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 47932353 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1275569664 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 629289128 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1559696 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4501408 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1910919896 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6428198 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 22587485 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.100846 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.301181 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 19409393 89.54% 89.54% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2267761 10.46% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 365 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 20310003 89.92% 89.92% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2277099 10.08% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 383 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 21677519 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 29325134974 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 22587485 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 30765191484 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 172530424 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 188815582 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 14118247362 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 14953353610 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7236066136 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7474900412 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 207955878 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 210684864 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 585496227 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 616864733 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40404 # Transaction distribution -system.iobus.trans_dist::ReadResp 40404 # Transaction distribution -system.iobus.trans_dist::WriteReq 136972 # Transaction distribution -system.iobus.trans_dist::WriteResp 136972 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47770 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40414 # Transaction distribution +system.iobus.trans_dist::ReadResp 40414 # Transaction distribution +system.iobus.trans_dist::WriteReq 136987 # Transaction distribution +system.iobus.trans_dist::WriteResp 136987 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47846 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) @@ -2311,18 +2312,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122912 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231760 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231760 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122988 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231734 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231734 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354752 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47790 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354802 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47866 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2332,24 +2331,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155927 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156003 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355288 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513405 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47202500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513377 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47239500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 315000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) @@ -2362,767 +2360,764 @@ system.iobus.reqLayer16.occupancy 15500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25874502 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26112500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 168500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36405000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 36406501 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 566670204 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 123500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 566812397 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 31500 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92927000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92988000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148200000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148174000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115872 # number of replacements -system.iocache.tags.tagsinuse 11.264501 # Cycle average of tags in use -system.iocache.tags.total_refs 6 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115888 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000052 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9145998133000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.414921 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.849581 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463433 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.240599 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.704031 # Average percentage of cache occupancy +system.iocache.tags.replacements 115848 # number of replacements +system.iocache.tags.tagsinuse 11.264479 # Cycle average of tags in use +system.iocache.tags.total_refs 11 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115864 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000095 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 9145999585000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.415083 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.849396 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463443 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.240587 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.704030 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043272 # Number of tag accesses -system.iocache.tags.data_accesses 1043272 # Number of data accesses -system.iocache.WriteLineReq_hits::realview.ide 2 # number of WriteLineReq hits -system.iocache.WriteLineReq_hits::total 2 # number of WriteLineReq hits +system.iocache.tags.tag_accesses 1043144 # Number of tag accesses +system.iocache.tags.data_accesses 1043144 # Number of data accesses +system.iocache.WriteLineReq_hits::realview.ide 6 # number of WriteLineReq hits +system.iocache.WriteLineReq_hits::total 6 # number of WriteLineReq hits system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8896 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8933 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106982 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106982 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106978 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106978 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8896 # number of demand (read+write) misses -system.iocache.demand_misses::total 8936 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8883 # number of demand (read+write) misses +system.iocache.demand_misses::total 8923 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8896 # number of overall misses -system.iocache.overall_misses::total 8936 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5261000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1700094991 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1705355991 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8883 # number of overall misses +system.iocache.overall_misses::total 8923 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5243500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1665415552 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1670659052 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 14013428406 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 14013428406 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5630000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1700094991 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1705724991 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5630000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1700094991 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1705724991 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 14002624152 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 14002624152 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5612500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1665415552 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1671028052 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5612500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1665415552 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1671028052 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8896 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8933 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8896 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8936 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8883 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8923 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8896 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8936 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8883 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8923 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 0.999981 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 0.999981 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 0.999944 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 0.999944 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142189.189189 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 191107.800247 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190905.182022 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141716.216216 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 187483.457391 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 187293.615695 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130988.656092 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130988.656092 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 140750 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 191107.800247 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 190882.384848 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 140750 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 191107.800247 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 190882.384848 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 36149 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130892.558769 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130892.558769 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 140312.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 187483.457391 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 187271.999552 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 140312.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 187483.457391 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 187271.999552 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 35141 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3721 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3655 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.714862 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.614501 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106948 # number of writebacks -system.iocache.writebacks::total 106948 # number of writebacks +system.iocache.writebacks::writebacks 106943 # number of writebacks +system.iocache.writebacks::total 106943 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8896 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8933 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106982 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106982 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106978 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106978 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8896 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8936 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8883 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8923 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8896 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8936 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3411000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1255294991 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1258705991 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8883 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8923 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3393500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1221265552 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1224659052 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8664328406 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8664328406 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3630000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1255294991 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1258924991 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3630000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1255294991 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1258924991 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8653724152 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8653724152 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3612500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1221265552 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1224878052 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3612500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1221265552 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1224878052 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999981 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.999981 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999944 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.999944 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92189.189189 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141107.800247 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 140905.182022 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91716.216216 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137483.457391 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 137293.615695 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80988.656092 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80988.656092 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90750 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 141107.800247 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 140882.384848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90750 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 141107.800247 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 140882.384848 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80892.558769 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80892.558769 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90312.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 137483.457391 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 137271.999552 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90312.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 137483.457391 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 137271.999552 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1047057 # number of replacements -system.l2c.tags.tagsinuse 63052.180525 # Cycle average of tags in use -system.l2c.tags.total_refs 6067910 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1106756 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.482609 # Average number of references to valid blocks. +system.l2c.tags.replacements 1253630 # number of replacements +system.l2c.tags.tagsinuse 63075.564404 # Cycle average of tags in use +system.l2c.tags.total_refs 6221998 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1313632 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.736485 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 25661.598067 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 59.549817 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 63.820457 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6721.957431 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5596.771487 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5304.396230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 138.527549 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 206.635310 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5419.027786 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6651.679849 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 7228.216543 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.391565 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000909 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000974 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.102569 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.085400 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.080939 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002114 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003153 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.082688 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.101497 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.110294 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.962100 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9310 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 176 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50213 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 61 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 427 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 684 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1579 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 6559 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 23067.685004 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 146.868876 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 206.473413 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5441.439609 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6307.681817 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8428.958067 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 140.047033 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 198.225362 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4720.872050 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6856.377655 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 7560.935517 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.351985 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002241 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003151 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.083030 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.096248 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.128616 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002137 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003025 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.072035 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.104620 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.115371 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.962457 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 9537 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50225 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 45 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 233 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 325 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1551 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 7383 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 158 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2614 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 11152 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 36045 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.142059 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.002686 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.766190 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 72230268 # Number of tag accesses -system.l2c.tags.data_accesses 72230268 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2478146 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123319.428715 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125035.044479 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 132299.122166 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.288614 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.324686 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.304693 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.227474 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.229212 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228302 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.743754 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.439009 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.643834 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.183654 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.236874 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.086306 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.163993 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.358056 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.206713 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.238525 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.086452 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.167515 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.349357 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.186681 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.183654 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.236874 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.086306 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.439253 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.358056 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.206713 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.238525 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.086452 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.257899 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.349357 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.279962 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.183654 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.236874 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.086306 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.439253 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.358056 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.206713 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.238525 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.086452 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.257899 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.349357 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.279962 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73377.861964 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73523.799428 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73447.182525 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76403.760331 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76486.574158 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76443.378740 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129454.408093 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 125228.249202 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 128509.558709 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 123891.442866 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127658.044796 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123667.132539 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128778.627801 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140016.532293 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123891.442866 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129102.163083 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123667.132539 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 126766.617208 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 134616.848813 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123891.442866 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129102.163083 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123667.132539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 126766.617208 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 134616.848813 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154383.299498 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153344.559251 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159070.933014 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131241.202012 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153993.698975 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162871.815452 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158558.142321 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156682.699511 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130693.494077 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 151451.217285 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161054.718899 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156910.864827 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154180.133718 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152369.857434 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160896.324480 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 139282.030687 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 158817.140280 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 138452.781060 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 90049 # Transaction distribution -system.membus.trans_dist::ReadResp 640443 # Transaction distribution -system.membus.trans_dist::WriteReq 37563 # Transaction distribution -system.membus.trans_dist::WriteResp 37563 # Transaction distribution -system.membus.trans_dist::WritebackDirty 930050 # Transaction distribution -system.membus.trans_dist::CleanEvict 190296 # Transaction distribution -system.membus.trans_dist::UpgradeReq 413026 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 280293 # Transaction distribution -system.membus.trans_dist::UpgradeResp 150977 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 593740 # Transaction distribution -system.membus.trans_dist::ReadExResp 574320 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 550394 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106981 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106981 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122912 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 90579 # Transaction distribution +system.membus.trans_dist::ReadResp 797028 # Transaction distribution +system.membus.trans_dist::WriteReq 38077 # Transaction distribution +system.membus.trans_dist::WriteResp 38077 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1072761 # Transaction distribution +system.membus.trans_dist::CleanEvict 234796 # Transaction distribution +system.membus.trans_dist::UpgradeReq 432847 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 303767 # Transaction distribution +system.membus.trans_dist::UpgradeResp 155875 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 628014 # Transaction distribution +system.membus.trans_dist::ReadExResp 607752 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 706453 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106976 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106976 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122988 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 22290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4211327 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4356581 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343179 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 343179 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4699760 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155927 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24302 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4826718 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4974060 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342886 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342886 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5316946 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156003 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 44580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 127415488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 127617319 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7277312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7277312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 134894631 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 564682 # Total snoops (count) -system.membus.snoop_fanout::samples 3194785 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48604 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 148677184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 148883115 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7268800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 156151915 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 604039 # Total snoops (count) +system.membus.snoop_fanout::samples 3616779 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3194785 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3616779 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3194785 # Request fanout histogram -system.membus.reqLayer0.occupancy 109901497 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3616779 # Request fanout histogram +system.membus.reqLayer0.occupancy 110163500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 18632000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20375999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6680198838 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7677665405 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6549107858 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7558802547 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 229362666 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229140974 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3176,52 +3171,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 11369480 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6166084 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1983565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 99756 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 89163 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 10593 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 90051 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4379282 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 37563 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 37563 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3408225 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1479469 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 686639 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 358765 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1045403 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1072017 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1072017 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4296486 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106981 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8273345 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7109938 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15383283 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 249443752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200422911 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 449866663 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2689125 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7811601 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.375584 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.487066 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 11857284 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6410159 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2032721 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 132920 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 118959 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 13961 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 90581 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4604579 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38077 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38077 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3658344 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1620073 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 706187 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 382180 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1088365 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1100091 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1100091 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4521240 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106976 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8903542 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7167245 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 16070787 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267379155 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202223448 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 469602603 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2985982 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8314965 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.369241 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.486066 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4888281 62.58% 62.58% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2912727 37.29% 99.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 10593 0.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5258700 63.24% 63.24% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3042304 36.59% 99.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 13961 0.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7811601 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8585712934 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8314965 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8970776631 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2584443 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2598924 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4648327252 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5002984602 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4065319209 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4113788553 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal index e3cbb408a..d57761389 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal @@ -107,60 +107,60 @@ [ 2.145678] pci_bus 0000:00: bus scan returning with max=00
[ 2.145690] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 2.145712] pci 0000:00:00.0: fixup irq: got 33
-[ 2.145721] pci 0000:00:00.0: assigning IRQ 33
+[ 2.145720] pci 0000:00:00.0: assigning IRQ 33
[ 2.145731] pci 0000:00:01.0: fixup irq: got 34
[ 2.145740] pci 0000:00:01.0: assigning IRQ 34
[ 2.145752] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 2.145765] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.145779] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 2.145792] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.145778] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.145791] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 2.145803] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.145815] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.145814] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 2.145826] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 2.145838] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 2.146510] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.146790] ata_piix 0000:00:01.0: version 2.13
-[ 2.146802] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.146834] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.147106] scsi0 : ata_piix
-[ 2.147190] scsi1 : ata_piix
-[ 2.147234] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.147247] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.147374] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.146509] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.146789] ata_piix 0000:00:01.0: version 2.13
+[ 2.146800] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.146833] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.147105] scsi0 : ata_piix
+[ 2.147189] scsi1 : ata_piix
+[ 2.147233] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.147246] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.147373] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 2.147386] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.147401] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.147413] e1000 0000:00:00.0: enabling bus mastering
-[ 2.290900] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.290911] ata1.00: 2096640 sectors, multi 0: LBA
-[ 2.290940] ata1.00: configured for UDMA/33
+[ 2.147412] e1000 0000:00:00.0: enabling bus mastering
+[ 2.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.290910] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.290939] ata1.00: configured for UDMA/33
[ 2.291006] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.291133] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.291132] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.291158] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 2.291199] sd 0:0:0:0: [sda] Write Protect is off
[ 2.291208] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.291229] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 2.291366] sda: sda1
[ 2.291489] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 2.411160] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 2.411174] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.411161] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.411175] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 2.411196] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 2.411206] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.411207] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 2.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 2.411241] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 2.411314] usbcore: registered new interface driver usb-storage
-[ 2.411381] mousedev: PS/2 mouse device common for all mice
+[ 2.411382] mousedev: PS/2 mouse device common for all mice
[ 2.411554] usbcore: registered new interface driver usbhid
[ 2.411564] usbhid: USB HID core driver
-[ 2.411598] TCP: cubic registered
+[ 2.411599] TCP: cubic registered
[ 2.411606] NET: Registered protocol family 17
-[ 2.412103] devtmpfs: mounted
+[ 2.412104] devtmpfs: mounted
[ 2.412177] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.450715] udevd[609]: starting version 182
+[ 2.450669] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.523621] random: dd urandom read with 17 bits of entropy available
+[ 2.523747] random: dd urandom read with 17 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.651084] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.651088] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
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