diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 4572 |
1 files changed, 2382 insertions, 2190 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index ecc4cd446..3b8bb2577 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.349389 # Number of seconds simulated -sim_ticks 47349388766500 # Number of ticks simulated -final_tick 47349388766500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.355615 # Number of seconds simulated +sim_ticks 47355615197500 # Number of ticks simulated +final_tick 47355615197500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148460 # Simulator instruction rate (inst/s) -host_op_rate 174619 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7799944718 # Simulator tick rate (ticks/s) -host_mem_usage 883812 # Number of bytes of host memory used -host_seconds 6070.48 # Real time elapsed on the host -sim_insts 901223526 # Number of instructions simulated -sim_ops 1060022042 # Number of ops (including micro ops) simulated +host_inst_rate 178863 # Simulator instruction rate (inst/s) +host_op_rate 210359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9462962325 # Simulator tick rate (ticks/s) +host_mem_usage 759628 # Number of bytes of host memory used +host_seconds 5004.31 # Real time elapsed on the host +sim_insts 895084962 # Number of instructions simulated +sim_ops 1052703090 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 126592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 108352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 12219800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 55224576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 171840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 160768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 11630176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 36221056 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 451968 # Number of bytes read from this memory -system.physmem.bytes_read::total 116315128 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4075008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 659840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4734848 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 84862912 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 106496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 83264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 18925144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 17557952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 158592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 147776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 13767904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 16399360 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 427968 # Number of bytes read from this memory +system.physmem.bytes_read::total 67574456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 8104128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3589696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11693824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78266240 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 84883728 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1978 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1693 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 190956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 862884 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2685 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2512 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 181736 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 565954 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 7062 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1817460 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1325983 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78287056 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1664 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 295727 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 274343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2309 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 215138 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 256240 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6687 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1055887 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1222910 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1328586 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 258077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 1166321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 245625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 764974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2456529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 86063 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 13936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 99998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1792270 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 440 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1225513 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 399639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 370768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 290734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 346302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1426958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 171133 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 75803 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 246936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1652734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.inst 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1792710 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1792270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 258517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 1166321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 245625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 764974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4249239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1817460 # Number of read requests accepted -system.physmem.writeReqs 1459105 # Number of write requests accepted -system.physmem.readBursts 1817460 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1459105 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 116259968 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 57472 # Total number of bytes read from write queue -system.physmem.bytesWritten 92884608 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 116315128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 93236944 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 898 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7766 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 92270 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 109521 # Per bank write bursts -system.physmem.perBankRdBursts::1 125500 # Per bank write bursts -system.physmem.perBankRdBursts::2 109858 # Per bank write bursts -system.physmem.perBankRdBursts::3 118807 # Per bank write bursts -system.physmem.perBankRdBursts::4 114750 # Per bank write bursts -system.physmem.perBankRdBursts::5 133958 # Per bank write bursts -system.physmem.perBankRdBursts::6 108183 # Per bank write bursts -system.physmem.perBankRdBursts::7 109296 # Per bank write bursts -system.physmem.perBankRdBursts::8 104951 # Per bank write bursts -system.physmem.perBankRdBursts::9 157608 # Per bank write bursts -system.physmem.perBankRdBursts::10 96466 # Per bank write bursts -system.physmem.perBankRdBursts::11 111139 # Per bank write bursts -system.physmem.perBankRdBursts::12 103753 # Per bank write bursts -system.physmem.perBankRdBursts::13 116262 # Per bank write bursts -system.physmem.perBankRdBursts::14 95073 # Per bank write bursts -system.physmem.perBankRdBursts::15 101437 # Per bank write bursts -system.physmem.perBankWrBursts::0 88391 # Per bank write bursts -system.physmem.perBankWrBursts::1 94888 # Per bank write bursts -system.physmem.perBankWrBursts::2 89089 # Per bank write bursts -system.physmem.perBankWrBursts::3 94540 # Per bank write bursts -system.physmem.perBankWrBursts::4 92096 # Per bank write bursts -system.physmem.perBankWrBursts::5 104028 # Per bank write bursts -system.physmem.perBankWrBursts::6 87215 # Per bank write bursts -system.physmem.perBankWrBursts::7 89925 # Per bank write bursts -system.physmem.perBankWrBursts::8 85891 # Per bank write bursts -system.physmem.perBankWrBursts::9 90043 # Per bank write bursts -system.physmem.perBankWrBursts::10 85085 # Per bank write bursts -system.physmem.perBankWrBursts::11 94536 # Per bank write bursts -system.physmem.perBankWrBursts::12 86659 # Per bank write bursts -system.physmem.perBankWrBursts::13 94890 # Per bank write bursts -system.physmem.perBankWrBursts::14 85144 # Per bank write bursts -system.physmem.perBankWrBursts::15 88902 # Per bank write bursts +system.physmem.bw_write::total 1653174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1652734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 400078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 370768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 290734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 346302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3080131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1055887 # Number of read requests accepted +system.physmem.writeReqs 1888199 # Number of write requests accepted +system.physmem.readBursts 1055887 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1888199 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 67557888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue +system.physmem.bytesWritten 120408192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 67574456 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 120698960 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6789 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 114993 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 58784 # Per bank write bursts +system.physmem.perBankRdBursts::1 68771 # Per bank write bursts +system.physmem.perBankRdBursts::2 59130 # Per bank write bursts +system.physmem.perBankRdBursts::3 67531 # Per bank write bursts +system.physmem.perBankRdBursts::4 66855 # Per bank write bursts +system.physmem.perBankRdBursts::5 75133 # Per bank write bursts +system.physmem.perBankRdBursts::6 65903 # Per bank write bursts +system.physmem.perBankRdBursts::7 67407 # Per bank write bursts +system.physmem.perBankRdBursts::8 54196 # Per bank write bursts +system.physmem.perBankRdBursts::9 110706 # Per bank write bursts +system.physmem.perBankRdBursts::10 54461 # Per bank write bursts +system.physmem.perBankRdBursts::11 64104 # Per bank write bursts +system.physmem.perBankRdBursts::12 57097 # Per bank write bursts +system.physmem.perBankRdBursts::13 66166 # Per bank write bursts +system.physmem.perBankRdBursts::14 60751 # Per bank write bursts +system.physmem.perBankRdBursts::15 58597 # Per bank write bursts +system.physmem.perBankWrBursts::0 116651 # Per bank write bursts +system.physmem.perBankWrBursts::1 125865 # Per bank write bursts +system.physmem.perBankWrBursts::2 118664 # Per bank write bursts +system.physmem.perBankWrBursts::3 124773 # Per bank write bursts +system.physmem.perBankWrBursts::4 121001 # Per bank write bursts +system.physmem.perBankWrBursts::5 125597 # Per bank write bursts +system.physmem.perBankWrBursts::6 113710 # Per bank write bursts +system.physmem.perBankWrBursts::7 116980 # Per bank write bursts +system.physmem.perBankWrBursts::8 110183 # Per bank write bursts +system.physmem.perBankWrBursts::9 114411 # Per bank write bursts +system.physmem.perBankWrBursts::10 109841 # Per bank write bursts +system.physmem.perBankWrBursts::11 116847 # Per bank write bursts +system.physmem.perBankWrBursts::12 116927 # Per bank write bursts +system.physmem.perBankWrBursts::13 118874 # Per bank write bursts +system.physmem.perBankWrBursts::14 112844 # Per bank write bursts +system.physmem.perBankWrBursts::15 118210 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 47349386828500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 47355613259000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1817418 # Read request sizes (log2) +system.physmem.readPktSize::6 1055845 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1456502 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 724796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 275224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 218778 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 130576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 121480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 92297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 78276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 67824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 54542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29215 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 6539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 4680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 3658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1885596 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 695873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 103690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 49130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 41556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 38114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 34076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 21396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 5411 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3052 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2413 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -180,156 +180,180 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 20715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 37146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 48711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 55470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 75025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 82665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 93812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 97796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 101866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 103500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 107192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 100425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 105997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 102597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 17377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 13177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 9215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 41751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 61472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 87023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 107335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 120415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 125723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 127870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 127803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 120389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 118443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 115533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 109052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 105629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 105973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 96497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 93321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 90489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 85925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 894898 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 233.707153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.846498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 284.283402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 463489 51.79% 51.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 185877 20.77% 72.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 67737 7.57% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 36988 4.13% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 29329 3.28% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 22133 2.47% 90.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 15835 1.77% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13649 1.53% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 59861 6.69% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 894898 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 77790 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.351999 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 144.403085 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 77788 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::56 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1046123 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 179.678328 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 108.587927 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 250.922876 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 666099 63.67% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 200536 19.17% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50293 4.81% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24222 2.32% 89.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 17786 1.70% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12328 1.18% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8853 0.85% 93.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7558 0.72% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 58448 5.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1046123 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 79224 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.323930 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 140.057237 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 79222 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 77790 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 77790 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.656922 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.550932 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.537959 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 73893 94.99% 94.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 1079 1.39% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 616 0.79% 97.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 255 0.33% 97.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 611 0.79% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 159 0.20% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 204 0.26% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 127 0.16% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 198 0.25% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 57 0.07% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 225 0.29% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 47 0.06% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 57 0.07% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 49 0.06% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 102 0.13% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 22 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 26 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 10 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 13 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 9 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 77790 # Writes before turning the bus around for reads -system.physmem.totQLat 101322311265 # Total ticks spent queuing -system.physmem.totMemAccLat 135382848765 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9082810000 # Total ticks spent in databus transfers -system.physmem.avgQLat 55776.96 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 79224 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 79224 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.747576 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.323530 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.901705 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 65925 83.21% 83.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 5556 7.01% 90.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 2071 2.61% 92.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 1166 1.47% 94.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 1087 1.37% 95.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 456 0.58% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 393 0.50% 96.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 290 0.37% 97.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 329 0.42% 97.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 179 0.23% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 294 0.37% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 101 0.13% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 139 0.18% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 103 0.13% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 155 0.20% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 83 0.10% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 89 0.11% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 58 0.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 57 0.07% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 65 0.08% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 66 0.08% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 81 0.10% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 58 0.07% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 58 0.07% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 69 0.09% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 72 0.09% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 57 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 44 0.06% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 31 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 21 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 22 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 15 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 7 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::280-287 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-295 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::296-303 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-311 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::312-319 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-327 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::328-335 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-343 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::344-351 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-359 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::360-367 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-375 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::376-383 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-391 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::456-463 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-503 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 79224 # Writes before turning the bus around for reads +system.physmem.totQLat 39480003252 # Total ticks spent queuing +system.physmem.totMemAccLat 59272353252 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5277960000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37400.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 74526.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.46 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.97 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 56150.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.54 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.43 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.53 # Average write queue length when enqueuing -system.physmem.readRowHits 1479200 # Number of row buffer hits during reads -system.physmem.writeRowHits 893785 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.58 # Row buffer hit rate for writes -system.physmem.avgGap 14450922.48 # Average gap between requests -system.physmem.pageHitRate 72.61 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45452153624500 # Time in different power states -system.physmem.memoryStateTime::REF 1581100040000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 316134376000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3577346640 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3188082240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1951925250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1739529000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7253009400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 6916111800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 4796314560 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 4608252000 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3092631678240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3092631678240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1196963299980 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1185023558430 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27359663548500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27370137006000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31666837122570 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31664244217710 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.790877 # Core power per rank (mW) -system.physmem.averagePower::1 668.736116 # Core power per rank (mW) +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing +system.physmem.readRowHits 797783 # Number of row buffer hits during reads +system.physmem.writeRowHits 1093063 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.10 # Row buffer hit rate for writes +system.physmem.avgGap 16084996.59 # Average gap between requests +system.physmem.pageHitRate 64.38 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4126437000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2251528125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4130209200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6241801680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1193820708150 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27366157608000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31669766818395 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.764772 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45525574397500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581308040000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 248732168750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3782252880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2063729250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4103353800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5949527760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1183965961905 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27374802122250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31667705474085 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.721243 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45539970549502 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581308040000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 234336016748 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory @@ -354,16 +378,24 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 127854962 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91169153 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5795491 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 97464931 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 70565780 # Number of BTB hits +system.cpu0.branchPred.lookups 131272413 # Number of BP lookups +system.cpu0.branchPred.condPredicted 92904470 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6038757 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 98925935 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 71271707 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.401200 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 14662444 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 979053 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.045523 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15434878 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1076370 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -385,27 +417,75 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 271399 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 271399 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8182 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72706 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 271399 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 271399 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 271399 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 80888 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 17168.766430 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15272.701717 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 12980.054286 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 77350 95.63% 95.63% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2802 3.46% 99.09% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 370 0.46% 99.55% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 250 0.31% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 18 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 21 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 23 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 80888 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 644436704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 644436704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 644436704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 72706 89.88% 89.88% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8182 10.12% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 80888 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 271399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 271399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 80888 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 80888 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 352287 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 80634882 # DTB read hits -system.cpu0.dtb.read_misses 217470 # DTB read misses -system.cpu0.dtb.write_hits 71942682 # DTB write hits -system.cpu0.dtb.write_misses 47848 # DTB write misses +system.cpu0.dtb.read_hits 83830376 # DTB read hits +system.cpu0.dtb.read_misses 224800 # DTB read misses +system.cpu0.dtb.write_hits 74836136 # DTB write hits +system.cpu0.dtb.write_misses 46599 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 34852 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1874 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8493 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 31986 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8713 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11561 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 80852352 # DTB read accesses -system.cpu0.dtb.write_accesses 71990530 # DTB write accesses +system.cpu0.dtb.perms_faults 10302 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 84055176 # DTB read accesses +system.cpu0.dtb.write_accesses 74882735 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 152577564 # DTB hits -system.cpu0.dtb.misses 265318 # DTB misses -system.cpu0.dtb.accesses 152842882 # DTB accesses +system.cpu0.dtb.hits 158666512 # DTB hits +system.cpu0.dtb.misses 271399 # DTB misses +system.cpu0.dtb.accesses 158937911 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -427,145 +507,185 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 228743332 # ITB inst hits -system.cpu0.itb.inst_misses 63317 # ITB inst misses +system.cpu0.itb.walker.walks 59516 # Table walker walks requested +system.cpu0.itb.walker.walksLong 59516 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51758 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 59516 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 59516 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 59516 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 52388 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 19494.417176 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17354.171367 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 14602.329148 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 48500 92.58% 92.58% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3085 5.89% 98.47% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 277 0.53% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 436 0.83% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 31 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 52388 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 643764704 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 643764704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 643764704 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 51758 98.80% 98.80% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 630 1.20% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 52388 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59516 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59516 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52388 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52388 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 111904 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 234493726 # ITB inst hits +system.cpu0.itb.inst_misses 59516 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24510 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 22765 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 202277 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 197741 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 228806649 # ITB inst accesses -system.cpu0.itb.hits 228743332 # DTB hits -system.cpu0.itb.misses 63317 # DTB misses -system.cpu0.itb.accesses 228806649 # DTB accesses -system.cpu0.numCycles 867293351 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 234553242 # ITB inst accesses +system.cpu0.itb.hits 234493726 # DTB hits +system.cpu0.itb.misses 59516 # DTB misses +system.cpu0.itb.accesses 234553242 # DTB accesses +system.cpu0.numCycles 936626399 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 417325536 # Number of instructions committed -system.cpu0.committedOps 490736323 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 44793539 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4342 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93832115526 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.078218 # CPI: cycles per instruction -system.cpu0.ipc 0.481182 # IPC: instructions per cycle +system.cpu0.committedInsts 433367687 # Number of instructions committed +system.cpu0.committedOps 509515701 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 43981618 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 3754 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93775213530 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.161274 # CPI: cycles per instruction +system.cpu0.ipc 0.462690 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4790 # number of quiesce instructions executed -system.cpu0.tickCycles 682045150 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 185248201 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5375859 # number of replacements -system.cpu0.dcache.tags.tagsinuse 504.387778 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 144555742 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5376371 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.887233 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4951320000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 504.387778 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.985132 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.985132 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 12643 # number of quiesce instructions executed +system.cpu0.tickCycles 703108983 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 233517416 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5387052 # number of replacements +system.cpu0.dcache.tags.tagsinuse 501.034252 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 150576282 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5387564 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.948862 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4951668000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 501.034252 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.978583 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.978583 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 308078040 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 308078040 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 74032777 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 74032777 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 66638302 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 66638302 # 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number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 54382834533 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54382834533 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 36195221997 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 36195221997 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst 21037893950 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 21037893950 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1466052740 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 1466052740 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3737583856 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3737583856 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 3062000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3062000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 90578056530 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 90578056530 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 90578056530 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 90578056530 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 77896567 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 77896567 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 68957557 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 68957557 # 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number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.049602 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.049602 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.033633 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033633 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst 0.865725 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.865725 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.059049 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059049 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.099511 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099511 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.042103 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.042103 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.042103 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.042103 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14074.997485 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14074.997485 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15606.400330 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15606.400330 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 28326.806048 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 28326.806048 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13836.299065 # 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number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -574,88 +694,88 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3741617 # number of writebacks -system.cpu0.dcache.writebacks::total 3741617 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 374932 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 374932 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 967778 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 967778 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst 26 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 26 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 53 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 53 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 76 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 76 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 1342710 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1342710 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 1342710 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1342710 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3488858 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3488858 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1351477 # 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number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 42020078260 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42020078260 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 19120911908 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19120911908 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 19537847050 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 19537847050 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1252614238 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1252614238 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3369767592 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 3070097397 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3070097397 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 6019405287 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6019405287 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.044788 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.044788 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.019599 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019599 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.865695 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.865695 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.059019 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059019 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.099468 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099468 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.032960 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032960 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.032960 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032960 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12044.078108 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.078108 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14148.159316 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14148.159316 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 26307.965096 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26307.965096 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11827.827447 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11827.827447 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18893.067908 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18893.067908 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3733142 # 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number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 25755951436 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1293404753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1293404753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3399276642 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3399276642 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2291500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2291500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 64383402532 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 64383402532 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 64383402532 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 64383402532 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5824362996 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5824362996 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 5586865743 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5586865743 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 11411228739 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11411228739 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.043119 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043119 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.018436 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018436 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.752802 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.752802 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.056249 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056249 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.097359 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097359 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031535 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.031535 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031535 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031535 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12062.641038 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12062.641038 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 16868.973275 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16868.973275 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 33623.957488 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 33623.957488 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 12433.595318 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12433.595318 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18890.432416 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18890.432416 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12631.561693 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12631.561693 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12631.561693 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12631.561693 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 13381.441875 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 13381.441875 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -663,58 +783,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 8781546 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.937582 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 219752565 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 8782058 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 25.022901 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 16633914000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937582 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999878 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999878 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 9463678 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.932976 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 224826074 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9464190 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 23.755448 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 21621868750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932976 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999869 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 465851331 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 465851331 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 219752565 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 219752565 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 219752565 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 219752565 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 219752565 # number of overall hits -system.cpu0.icache.overall_hits::total 219752565 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 8782067 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 8782067 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 8782067 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 8782067 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 8782067 # number of overall misses -system.cpu0.icache.overall_misses::total 8782067 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 75181971221 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 75181971221 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 75181971221 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 75181971221 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 75181971221 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 75181971221 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 228534632 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 228534632 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 228534632 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 228534632 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 228534632 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 228534632 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038428 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.038428 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038428 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.038428 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038428 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.038428 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8560.851474 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8560.851474 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8560.851474 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8560.851474 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8560.851474 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8560.851474 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 478044747 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 478044747 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 224826074 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 224826074 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 224826074 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 224826074 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 224826074 # number of overall hits +system.cpu0.icache.overall_hits::total 224826074 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9464200 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9464200 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9464200 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9464200 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9464200 # number of overall misses +system.cpu0.icache.overall_misses::total 9464200 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93878607487 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 93878607487 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 93878607487 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 93878607487 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 93878607487 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 93878607487 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 234290274 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 234290274 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 234290274 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 234290274 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 234290274 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 234290274 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040395 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.040395 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040395 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.040395 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040395 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.040395 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9919.338928 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9919.338928 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9919.338928 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9919.338928 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -723,353 +843,346 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8782067 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 8782067 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 8782067 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 8782067 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 8782067 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 8782067 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 61997855741 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 61997855741 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 61997855741 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 61997855741 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 61997855741 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 61997855741 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9464200 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9464200 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9464200 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9464200 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9464200 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9464200 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 79648587963 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 79648587963 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 79648587963 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 79648587963 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 79648587963 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 79648587963 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713229500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4713229500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038428 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.038428 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.038428 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7059.597216 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040395 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.040395 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.040395 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8415.776079 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8415.776079 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8415.776079 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 84003023 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 4398912 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 74572645 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1090360 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 154166 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3786940 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6742713 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 4037603 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16229.874548 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15269588 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 4053811 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.766724 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 14918796500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 3465.639505 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 40.958286 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 27.625357 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2577.016988 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 10118.634411 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.211526 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002500 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001686 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.157289 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.617592 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.990593 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 10250 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5866 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 116 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 1048 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 4016 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3415 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1655 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 22 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 525 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2441 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1975 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 887 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.625610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.358032 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 311163440 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 311163440 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 470272 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 147367 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 11429450 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 12047089 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3741617 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3741617 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.inst 295044 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 295044 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 86443 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 86443 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 36465 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 36465 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 911350 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 911350 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 470272 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 147367 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 12340800 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 12958439 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 470272 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 147367 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 12340800 # number of overall hits -system.cpu0.l2cache.overall_hits::total 12958439 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13865 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10088 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 947171 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 971124 # number of ReadReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.inst 446451 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 446451 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 123568 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 123568 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 141888 # 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number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 195483 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 195483 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 179937 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 179937 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 10 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 1126447 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1126447 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 475185 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 146450 # 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miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.746551 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.648936 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.648936 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.813285 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.813285 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.202559 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.202559 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028639 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064069 # 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number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 5338553005 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5338553005 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15010557747 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15010557747 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.110666 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.107106 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.085266 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.085266 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.588388 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.588388 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.795546 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.795546 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.746347 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.746347 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.648936 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.648936 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813285 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813285 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.194529 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.194529 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.028634 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064037 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080589 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.078629 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.028634 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064037 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080589 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.231718 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231718 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.120279 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.116585 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.120279 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.346044 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23637.177128 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23726.676861 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 44479.809572 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22311.716595 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 22311.716595 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16850.081623 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16850.081623 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13956.633965 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13956.633965 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 269285.714286 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 269285.714286 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 28826.174828 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 28826.174828 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24695.991404 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 24744.850767 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24695.991404 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39995.599759 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.186617 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23772.172383 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23802.344928 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45624.567406 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 35111.301561 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 35111.301561 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16958.402220 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16958.402220 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13624.298374 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13624.298374 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 183500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 36521.098204 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36521.098204 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25722.497380 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25725.422121 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25722.497380 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33192.985440 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1077,68 +1190,77 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 17406363 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 13329872 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19688 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19687 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3741617 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 5530609 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 862152 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 741495 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 486160 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 325301 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 465486 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1278141 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1152631 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17668715 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15752783 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 346532 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1063511 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 34831541 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 565398848 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 598192623 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1259640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3873096 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1168724207 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 10729638 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 29561564 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.351841 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.477545 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 16482247 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 13994677 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 33105 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33105 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3733141 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1450559 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1135277 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 764525 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 439100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 331866 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 445825 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1265717 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1135924 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19032980 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15771109 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 324159 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1044893 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 36173141 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 609055296 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 597396947 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1171600 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3801480 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1211425323 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5254625 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 24752436 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.199831 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.399873 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 19160579 64.82% 64.82% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 10400985 35.18% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 19806132 80.02% 80.02% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 4946304 19.98% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 29561564 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14119794312 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 24752436 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14477877088 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 225496496 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 203336996 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 13269247990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14303799012 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7748577182 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7760036291 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 189385144 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 177959354 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 579874631 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 570171512 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 146637664 # Number of BP lookups -system.cpu1.branchPred.condPredicted 104244557 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6464776 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 109760718 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 80092874 # Number of BTB hits +system.cpu1.branchPred.lookups 141025153 # Number of BP lookups +system.cpu1.branchPred.condPredicted 100933183 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6236213 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 106937612 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 78176713 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.970436 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17287162 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1125459 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.104974 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16283768 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1021605 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1160,27 +1282,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 298651 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 298651 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11560 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94332 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 298651 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 298651 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 298651 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 105892 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 17805.770634 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 15803.828904 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14966.928967 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 104531 98.71% 98.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1148 1.08% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 61 0.06% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 63 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 105892 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1172907556 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1172907556 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1172907556 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 94332 89.08% 89.08% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11560 10.92% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 105892 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 298651 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 298651 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105892 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105892 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 404543 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 95196820 # DTB read hits -system.cpu1.dtb.read_misses 258683 # DTB read misses -system.cpu1.dtb.write_hits 82774540 # DTB write hits -system.cpu1.dtb.write_misses 48918 # DTB write misses +system.cpu1.dtb.read_hits 90905034 # DTB read hits +system.cpu1.dtb.read_misses 248418 # DTB read misses +system.cpu1.dtb.write_hits 78767149 # DTB write hits +system.cpu1.dtb.write_misses 50233 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 40938 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1166 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8454 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 43819 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 923 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8321 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11190 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 95455503 # DTB read accesses -system.cpu1.dtb.write_accesses 82823458 # DTB write accesses +system.cpu1.dtb.perms_faults 12272 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 91153452 # DTB read accesses +system.cpu1.dtb.write_accesses 78817382 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 177971360 # DTB hits -system.cpu1.dtb.misses 307601 # DTB misses -system.cpu1.dtb.accesses 178278961 # DTB accesses +system.cpu1.dtb.hits 169672183 # DTB hits +system.cpu1.dtb.misses 298651 # DTB misses +system.cpu1.dtb.accesses 169970834 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1202,145 +1366,179 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 262373201 # ITB inst hits -system.cpu1.itb.inst_misses 66107 # ITB inst misses +system.cpu1.itb.walker.walks 67610 # Table walker walks requested +system.cpu1.itb.walker.walksLong 67610 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 497 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58418 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 67610 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 67610 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 67610 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 58915 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 20253.386778 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 17562.612185 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17511.554701 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 57403 97.43% 97.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1356 2.30% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 66 0.11% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 56 0.10% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 58915 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1173450056 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1173450056 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1173450056 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 58418 99.16% 99.16% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 497 0.84% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 58915 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67610 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 67610 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58915 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58915 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 126525 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 252933263 # ITB inst hits +system.cpu1.itb.inst_misses 67610 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 29545 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 31594 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 222220 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 222493 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 262439308 # ITB inst accesses -system.cpu1.itb.hits 262373201 # DTB hits -system.cpu1.itb.misses 66107 # DTB misses -system.cpu1.itb.accesses 262439308 # DTB accesses -system.cpu1.numCycles 965776076 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 253000873 # ITB inst accesses +system.cpu1.itb.hits 252933263 # DTB hits +system.cpu1.itb.misses 67610 # DTB misses +system.cpu1.itb.accesses 253000873 # DTB accesses +system.cpu1.numCycles 943783669 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 483897990 # Number of instructions committed -system.cpu1.committedOps 569285719 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 49152054 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5850 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93733878410 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 1.995826 # CPI: cycles per instruction -system.cpu1.ipc 0.501046 # IPC: instructions per cycle +system.cpu1.committedInsts 461717275 # Number of instructions committed +system.cpu1.committedOps 543187389 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 49256164 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5826 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93768369123 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.044073 # CPI: cycles per instruction +system.cpu1.ipc 0.489219 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14403 # number of quiesce instructions executed -system.cpu1.tickCycles 777604637 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 188171439 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5691678 # number of replacements -system.cpu1.dcache.tags.tagsinuse 432.252247 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 169393329 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5692190 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.758903 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8364525946500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 432.252247 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.844243 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.844243 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 358720623 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 358720623 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 87552380 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 87552380 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 77214593 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 77214593 # number of WriteReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 211985 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 211985 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1994962 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1994962 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1944639 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1944639 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 164766973 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 164766973 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 164766973 # number of overall hits -system.cpu1.dcache.overall_hits::total 164766973 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 4362572 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 4362572 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 2362737 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2362737 # number of WriteReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst 497251 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 497251 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 139927 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 139927 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 188742 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 188742 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 6725309 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 6725309 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 6725309 # number of overall misses -system.cpu1.dcache.overall_misses::total 6725309 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 63153941750 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 63153941750 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 37295206516 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 37295206516 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst 9223332559 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 9223332559 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1921743254 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 1921743254 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3886161820 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3886161820 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 3267000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3267000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 100449148266 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 100449148266 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 100449148266 # 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number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1349,88 +1547,88 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3739270 # number of writebacks -system.cpu1.dcache.writebacks::total 3739270 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 400087 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 400087 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 959724 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 959724 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst 47 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 47 # 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mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.065512 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065512 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.088436 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088436 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.031287 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031287 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.031287 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031287 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12391.309416 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12391.309416 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14421.445075 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14421.445075 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 16533.144225 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 16533.144225 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11727.357515 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11727.357515 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18542.231190 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18542.231190 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3711348 # number of writebacks +system.cpu1.dcache.writebacks::total 3711348 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 397792 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 397792 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 970938 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 970938 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst 60 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 60 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 47 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 47 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst 68 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 68 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 1368730 # 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number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 193784 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 193784 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 5309488 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 5309488 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 5309488 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5309488 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 46779736993 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 46779736993 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 20386885918 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20386885918 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 10653380764 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10653380764 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1693632498 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1693632498 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3584420895 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3584420895 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 1830000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 67166622911 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 67166622911 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 67166622911 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 67166622911 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 548139751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 548139751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 613571252 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 613571252 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 1161711003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1161711003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.044572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.018407 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018407 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.868662 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.868662 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.068929 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068929 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.094612 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094612 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.032446 # 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average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11987.433099 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18496.990954 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18496.990954 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12922.165400 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12922.165400 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12922.165400 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12922.165400 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -1438,58 +1636,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # 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Cycle average of tags in use +system.cpu1.icache.tags.total_refs 243489253 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9215542 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 26.421588 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8367568177500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.228865 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990681 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990681 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 534294484 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 534294484 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 252141010 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 252141010 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 252141010 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 252141010 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 252141010 # number of overall hits -system.cpu1.icache.overall_hits::total 252141010 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 10004155 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 10004155 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 10004155 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 10004155 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 10004155 # number of overall misses -system.cpu1.icache.overall_misses::total 10004155 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 85019530358 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 85019530358 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 85019530358 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 85019530358 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 85019530358 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 85019530358 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 262145165 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 262145165 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 262145165 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 262145165 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 262145165 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 262145165 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038163 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.038163 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038163 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.038163 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038163 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.038163 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8498.421941 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8498.421941 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8498.421941 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8498.421941 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8498.421941 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8498.421941 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 514625132 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 514625132 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 243489253 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 243489253 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 243489253 # 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number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 91468274167 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 91468274167 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 91468274167 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 252704795 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 252704795 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 252704795 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 252704795 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 252704795 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 252704795 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036468 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.036468 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.036468 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.036468 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.036468 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.036468 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9925.436200 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9925.436200 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9925.436200 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9925.436200 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9925.436200 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9925.436200 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1498,353 +1696,355 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 10004155 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 10004155 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 10004155 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 10004155 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 10004155 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 10004155 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 70001431618 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 70001431618 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 70001431618 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 70001431618 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 70001431618 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 70001431618 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8751000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8751000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8751000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8751000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038163 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.038163 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.038163 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6997.235810 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6997.235810 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6997.235810 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9215542 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 9215542 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 9215542 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 9215542 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 9215542 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 9215542 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 77617743273 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 77617743273 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 77617743273 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 77617743273 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 77617743273 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 77617743273 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8388750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8388750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8388750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8388750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.036468 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.036468 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.036468 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8422.482722 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8422.482722 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8422.482722 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 91266400 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2590593 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 83739964 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1124296 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 159143 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 3652396 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 7945944 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 3964575 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13771.716542 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 17209014 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 3980703 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.323109 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9604482251250 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4186.861890 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.243250 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 63.010570 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2902.209445 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6553.391387 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.255546 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004043 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003846 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.177137 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.399987 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.840559 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9777 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6309 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 89 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 734 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4083 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 3317 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1554 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 691 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1911 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 531 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.596741 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.385071 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 336896441 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 336896441 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 545727 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 151675 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 13043643 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 13741045 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3739269 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3739269 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.inst 314994 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 314994 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 88927 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 88927 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 41659 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 41659 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 944385 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 944385 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 545727 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 151675 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 13988028 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 14685430 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 545727 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 151675 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 13988028 # number of overall hits -system.cpu1.l2cache.overall_hits::total 14685430 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 14704 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10320 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 1062508 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1087532 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.inst 180857 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 180857 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 132678 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 132678 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 147002 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 147002 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 238730 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 238730 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 14704 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10320 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 1301238 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1326262 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 14704 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10320 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 1301238 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1326262 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 525735124 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 414121710 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 33089400106 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 34029256940 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst 5173608568 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 5173608568 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2603383383 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2603383383 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 2990869344 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2990869344 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 2444000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2444000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9524400999 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 9524400999 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 525735124 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 414121710 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 42613801105 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 43553657939 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 525735124 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 414121710 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 42613801105 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 43553657939 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 560431 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 161995 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 14106151 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 14828577 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3739269 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3739269 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst 495851 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 495851 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 221605 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 221605 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 188661 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 188661 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 1183115 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1183115 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 560431 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 161995 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 15289266 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 16011692 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 560431 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 161995 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 15289266 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 16011692 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026237 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.063706 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.075322 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.073340 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst 0.364741 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.364741 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.598714 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.598714 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.779186 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.779186 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.num_hwpf_issued 11995647 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 12001276 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 4903 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 1360052 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2569302 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13533.660217 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 15700970 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2584965 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.073958 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9611078525000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5526.220513 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 77.627317 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 76.256480 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 6438.113983 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1415.441924 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.337294 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004738 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004654 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.392951 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086392 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.826029 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2491 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13080 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 600 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1302 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 576 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 72 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4875 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5316 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2499 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.152039 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.798340 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 321109712 # 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number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 1591427 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1612858 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.inst 272843 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::total 272843 # number of WriteInvalidateReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 137034 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 137034 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 151974 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 151974 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # 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number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 47206598788 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 48021453758 # number of ReadReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst 213581444 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 213581444 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2792930491 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 2792930491 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 3071034580 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3071034580 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 1783500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1783500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9626384839 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 9626384839 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 455863233 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 358991737 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 56832983627 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 57647838597 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 455863233 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 358991737 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 56832983627 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 57647838597 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 557078 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 167398 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 13270037 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 13994513 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3711346 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3711346 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst 475262 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 475262 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 214314 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 214314 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 193783 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 193783 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 1183240 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1183240 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 557078 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 167398 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 14453277 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 15177753 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 557078 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 167398 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 14453277 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 15177753 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052987 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.119926 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.115249 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst 0.574090 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.574090 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.639408 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.639408 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.784248 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.784248 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.201781 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.201781 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026237 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.063706 # 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average WriteInvalidateReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 28606.073130 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 19621.816601 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19621.816601 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20345.773146 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20345.773146 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 407333.333333 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 407333.333333 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 39896.121137 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39896.121137 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35754.565016 # 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mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.063687 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.078920 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.076921 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026235 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.063687 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.078920 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.200339 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.200339 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.126385 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.121764 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.126385 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.305025 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25061.739913 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25197.269516 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30135.091093 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 17739.767756 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 17739.767756 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16370.695888 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16370.695888 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13815.637468 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13815.637468 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 337333.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 337333.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30032.586754 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30032.586754 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26092.290194 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29115.574710 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.189778 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22582.384880 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22693.811450 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39997.101782 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 26038.478163 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 26038.478163 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16876.429733 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16876.429733 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13661.751912 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13661.751912 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 1461500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1461500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30747.372117 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30747.372117 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23641.963786 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23726.811542 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23641.963786 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29557.889053 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -1852,65 +2052,66 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 19283354 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 15081139 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 18583 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 18583 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3739269 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 5170827 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 625737 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 495851 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 477449 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 330499 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 473092 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1314338 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1188302 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 20008489 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16359278 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 359533 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1226091 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 37953391 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640271616 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 615594373 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1295960 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4483448 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1261645397 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 10423087 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 30921485 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.327379 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.469257 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 16597851 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 14230777 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5242 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5242 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3711346 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1418597 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1143341 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 475262 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 452039 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 340076 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 470072 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1342662 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1189275 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18431264 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16132557 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 369420 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1220438 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 36153679 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 589800448 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 609347251 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1339184 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4456624 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1204943507 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5386490 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 25000724 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.203488 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.402593 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 20798445 67.26% 67.26% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 10123040 32.74% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 19913365 79.65% 79.65% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 5087359 20.35% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 30921485 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 14664539498 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 25000724 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 14152090513 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 176010242 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 175296997 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 15012316370 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13837074197 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8461463125 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8360530852 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 197959664 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 202402154 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 666269864 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 663973984 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40348 # Transaction distribution -system.iobus.trans_dist::ReadResp 40348 # Transaction distribution -system.iobus.trans_dist::WriteReq 136740 # Transaction distribution -system.iobus.trans_dist::WriteResp 30012 # Transaction distribution +system.iobus.trans_dist::ReadReq 40424 # Transaction distribution +system.iobus.trans_dist::ReadResp 40424 # Transaction distribution +system.iobus.trans_dist::WriteReq 136766 # Transaction distribution +system.iobus.trans_dist::WriteResp 30038 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48186 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1925,13 +2126,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122926 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123068 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231232 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231232 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354176 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48206 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1946,13 +2147,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156198 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338944 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338944 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496838 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36517000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7497228 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36614000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1980,71 +2181,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042881499 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1043031468 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92917000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179159841 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179210230 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115566 # number of replacements -system.iocache.tags.tagsinuse 11.298842 # Cycle average of tags in use +system.iocache.tags.replacements 115597 # number of replacements +system.iocache.tags.tagsinuse 11.297216 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115582 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9120788284000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.841658 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.457184 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240104 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466074 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706178 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9126956441000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.841188 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.456028 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240074 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466002 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706076 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040622 # Number of tag accesses -system.iocache.tags.data_accesses 1040622 # Number of data accesses +system.iocache.tags.tag_accesses 1040901 # Number of tag accesses +system.iocache.tags.data_accesses 1040901 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8857 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8894 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8888 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8925 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8857 # number of demand (read+write) misses -system.iocache.demand_misses::total 8897 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8888 # number of demand (read+write) misses +system.iocache.demand_misses::total 8928 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8857 # number of overall misses -system.iocache.overall_misses::total 8897 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1971462847 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1977169847 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8888 # number of overall misses +system.iocache.overall_misses::total 8928 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5659000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1934548608 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1940207608 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28907198811 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28907198811 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1971462847 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1977526847 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1971462847 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1977526847 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28977416630 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28977416630 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6016000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1934548608 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1940564608 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6016000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1934548608 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1940564608 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8857 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8894 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8888 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8925 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8857 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8897 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8888 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8928 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8857 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8897 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8888 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8928 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2058,55 +2259,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 222588.105115 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 222303.783112 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152945.945946 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 217658.484248 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 217390.208179 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270849.250534 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270849.250534 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 222588.105115 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 222268.949871 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 222588.105115 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 222268.949871 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 228015 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271507.164287 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 271507.164287 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 150400 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 217357.146953 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 150400 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 217357.146953 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 228934 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27566 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27737 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.271603 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.253740 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8857 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8888 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8925 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8857 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8897 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8888 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8928 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8857 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8897 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1510755865 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1514538865 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8888 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8928 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3735000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1472256614 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1475991614 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23356679475 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23356679475 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1510755865 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1514739865 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1510755865 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1514739865 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427107084 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427107084 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3936000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1472256614 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1476192614 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3936000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1472256614 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1476192614 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2120,493 +2321,484 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170571.961725 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 170287.706881 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100945.945946 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165645.433618 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 165377.211653 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218843.035333 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218843.035333 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219502.914737 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219502.914737 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1797599 # number of replacements -system.l2c.tags.tagsinuse 64905.725288 # Cycle average of tags in use -system.l2c.tags.total_refs 8591301 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1860596 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.617499 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6896032000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 7600.616161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.639535 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 9.409863 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1890.006249 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16961.129535 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 324.497512 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 441.216776 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 10554.786238 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 27107.423418 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.115976 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000254 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000144 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.028839 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.258806 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004951 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006732 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.161053 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.413626 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.990383 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 43530 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 179 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 19288 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 252 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1656 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6242 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 35370 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 173 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1730 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 16555 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.664215 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.002731 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.294312 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 89688959 # Number of tag accesses -system.l2c.tags.data_accesses 89688959 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8987 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6604 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 578381 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 2301852 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 8168 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5333 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 630016 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 2353942 # number of ReadReq hits -system.l2c.ReadReq_hits::total 5893283 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2942617 # number of Writeback hits -system.l2c.Writeback_hits::total 2942617 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.inst 6235 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.inst 6750 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 12985 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.inst 39044 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 35229 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 74273 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 7514 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 7779 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 15293 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 64131 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 55187 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 119318 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8987 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6604 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 642512 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 2301852 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 8168 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5333 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 685203 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 2353942 # number of demand (read+write) hits -system.l2c.demand_hits::total 6012601 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8987 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6604 # number of overall hits -system.l2c.overall_hits::cpu0.inst 642512 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 2301852 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 8168 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5333 # number of overall hits -system.l2c.overall_hits::cpu1.inst 685203 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 2353942 # number of overall hits -system.l2c.overall_hits::total 6012601 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1978 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1693 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 95514 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 863521 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2685 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2512 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 131326 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 566480 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1665709 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.inst 16918 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.inst 7174 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 24092 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 36442 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 33251 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 69693 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 9494 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 9010 # 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number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1978 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1693 # number of overall misses -system.l2c.overall_misses::cpu0.inst 140854 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 863521 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2685 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2512 # number of overall misses -system.l2c.overall_misses::cpu1.inst 183367 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 566480 # number of overall misses -system.l2c.overall_misses::total 1763090 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 165226748 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 144557248 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 7974806913 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 129814567894 # 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number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 53447323 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 50683879 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 104131202 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 3468272337 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 3934530582 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7402802919 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 165226748 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 144557248 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 11443079250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 222345248 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 209364000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 14578667281 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 227453390829 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 165226748 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 144557248 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 11443079250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 222345248 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 209364000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 14578667281 # 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number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2942617 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2942617 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.inst 23153 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.inst 13924 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 37077 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 75486 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 68480 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 143966 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 17008 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 16789 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 33797 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 109471 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 107228 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 216699 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 10965 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 8297 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 783366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 3165373 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 10853 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7845 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 868570 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2920422 # 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average overall miss latency -system.l2c.demand_avg_miss_latency::total 129008.383480 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83532.228514 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85385.261666 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 81240.712014 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82810.148231 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83345.541401 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 79505.403268 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 129008.383480 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 43295 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 460.262003 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 14361.821399 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 19215.753624 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.253722 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000211 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000154 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.117232 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.087490 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005704 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.007023 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.219144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.293209 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983888 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 14505 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 200 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 45654 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 147 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 696 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 13662 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1737 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4894 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 38831 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.221329 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.696625 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 65568567 # Number of tag accesses +system.l2c.tags.data_accesses 65568567 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6731 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4742 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 1051842 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 521850 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6817 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4499 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 1187571 # 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number of overall hits +system.l2c.overall_hits::cpu0.inst 1108239 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 521850 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6817 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4499 # number of overall hits +system.l2c.overall_hits::cpu1.inst 1240908 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 530462 # number of overall hits +system.l2c.overall_hits::total 3424248 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1664 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1301 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 169093 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 274703 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2478 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2309 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 162223 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 256515 # number of ReadReq misses +system.l2c.ReadReq_misses::total 870286 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.inst 435530 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.inst 123517 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 559047 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.inst 44959 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.inst 45474 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 90433 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.inst 8261 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.inst 9038 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 17299 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.inst 76639 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.inst 55158 # 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number of overall misses +system.l2c.overall_misses::cpu0.inst 245732 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 274703 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2478 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2309 # number of overall misses +system.l2c.overall_misses::cpu1.inst 217381 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 256515 # number of overall misses +system.l2c.overall_misses::total 1002083 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 138961746 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 111055248 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 13556032080 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 202393999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 185177500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 12762094450 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 95981532857 # number of ReadReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu0.inst 36612963 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu1.inst 35758482 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::total 72371445 # number of WriteInvalidateReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.inst 213542030 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.inst 216684315 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 430226345 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 36699987 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 41305269 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 78005256 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.inst 6278532917 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.inst 4207751582 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10486284499 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 138961746 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 111055248 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 19834564997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 202393999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 185177500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 16969846032 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 106467817356 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 138961746 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 111055248 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 19834564997 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 202393999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 185177500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 16969846032 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of overall miss cycles +system.l2c.overall_miss_latency::total 106467817356 # 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number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.inst 561349 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.inst 264022 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 825371 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.inst 74724 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.inst 77877 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 152601 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.inst 14136 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.inst 15424 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 29560 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.inst 133036 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.inst 108495 # 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average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.inst 289.502514 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::total 129.455028 # average WriteInvalidateReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 4749.705954 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 4765.015503 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 4757.404321 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 4442.559860 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 4570.178026 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4509.234985 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 81923.471301 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 76285.426992 # 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average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85361.451191 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 80716.247770 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 80198.137722 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 78064.992028 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 106246.505884 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 5735 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 946 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 156 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 45.766385 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 36.762821 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1219289 # number of writebacks -system.l2c.writebacks::total 1219289 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 49 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 228 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 53 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 251 # 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number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 205814996987 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5245081248 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2881233750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 8126314998 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 2584862001 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 2667893000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5252755001 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7829943249 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5549126750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 13379069999 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.180392 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.204050 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.141662 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.272730 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.247397 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.320204 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.172423 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.193886 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.220284 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.730704 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.515226 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.649783 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.482765 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.485558 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.484093 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.558208 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.536661 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.547504 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.414174 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.485330 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.449384 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 94777748 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 16730475683 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 156241500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 14225741302 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 93996922312 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 7718194748 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 418305498 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 8136500246 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4773990997 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 484709502 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5258700499 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 12492185745 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 903015000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13395200745 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.138323 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.120052 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.207871 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.775863 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.467828 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.677328 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.601667 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.583921 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.592611 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.584394 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.585970 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.585217 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.576077 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.508392 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.545673 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.181335 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66114.279032 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 97907.212176 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22469.301798 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 20366.746845 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22004.758959 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10131.989012 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10134.836676 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10133.420953 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10275.715047 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10220.729033 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10246.987167 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69355.674069 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63675.021611 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 66978.279832 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2617,57 +2809,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1764688 # Transaction distribution -system.membus.trans_dist::ReadResp 1764688 # Transaction distribution -system.membus.trans_dist::WriteReq 38271 # Transaction distribution -system.membus.trans_dist::WriteResp 38271 # Transaction distribution -system.membus.trans_dist::Writeback 1325983 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 130519 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 130519 # Transaction distribution -system.membus.trans_dist::UpgradeReq 461811 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 273493 # Transaction distribution -system.membus.trans_dist::UpgradeResp 92294 # Transaction distribution -system.membus.trans_dist::ReadExReq 109929 # Transaction distribution -system.membus.trans_dist::ReadExResp 93588 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122926 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 969598 # Transaction distribution +system.membus.trans_dist::ReadResp 969598 # Transaction distribution +system.membus.trans_dist::WriteReq 38347 # Transaction distribution +system.membus.trans_dist::WriteResp 38347 # Transaction distribution +system.membus.trans_dist::Writeback 1222910 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 662686 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 662686 # Transaction distribution +system.membus.trans_dist::UpgradeReq 426453 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 285961 # Transaction distribution +system.membus.trans_dist::UpgradeResp 115017 # Transaction distribution +system.membus.trans_dist::ReadExReq 144468 # Transaction distribution +system.membus.trans_dist::ReadExResp 127604 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123068 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24884 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5737506 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5885368 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336109 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336109 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6221477 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25110 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5176712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5324942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335765 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335765 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5660707 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156198 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 195441096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 195648244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14110976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14110976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 209759220 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 661928 # Total snoops (count) -system.membus.snoop_fanout::samples 3975767 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50220 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174186440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 174394182 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14086976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14086976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 188481158 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 617229 # Total snoops (count) +system.membus.snoop_fanout::samples 3621307 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3975767 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3621307 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3975767 # Request fanout histogram -system.membus.reqLayer0.occupancy 109763969 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3621307 # Request fanout histogram +system.membus.reqLayer0.occupancy 109998990 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 34484 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20835993 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20906994 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 15443357238 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 18632739306 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 16944581187 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 10660858032 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187180159 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 187340770 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2711,45 +2903,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 8566773 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 8559524 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38271 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38271 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2942617 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 143810 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 37077 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 531990 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 288786 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 820776 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 117 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 266520 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 266520 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10703555 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10080815 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 20784370 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 361515951 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 330513413 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 692029364 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1718447 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 12650717 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.009140 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.095166 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5129422 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5122206 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38347 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38347 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2491671 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 932101 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 825371 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 481339 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 298222 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 779561 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 298688 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298688 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8006212 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7112719 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15118931 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267664595 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231600691 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 499265286 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1616950 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9541409 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012122 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.109429 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 12535087 99.09% 99.09% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115630 0.91% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9425751 98.79% 98.79% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115658 1.21% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 12650717 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 18290340474 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9541409 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 18624671874 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7404000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 7692000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20424320611 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 12569931680 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 19750107809 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 12640622488 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |