diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
| commit | 4bc7dfb697bd779b12f1fd95fbe72144ae134055 (patch) | |
| tree | 532cea8e118ac27336792282c7023bb1b2d01be4 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual | |
| parent | cea1d14a937f27fa49423bd01eb900e578993a43 (diff) | |
| download | gem5-4bc7dfb697bd779b12f1fd95fbe72144ae134055.tar.xz | |
stats: Update MinorCPU regressions after accounting fix
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 5143 |
1 files changed, 2553 insertions, 2590 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 5aa558433..99e4aebe7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.365947 # Number of seconds simulated -sim_ticks 47365946685500 # Number of ticks simulated -final_tick 47365946685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.477179 # Number of seconds simulated +sim_ticks 47477179149500 # Number of ticks simulated +final_tick 47477179149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 174192 # Simulator instruction rate (inst/s) -host_op_rate 204861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9672451523 # Simulator tick rate (ticks/s) -host_mem_usage 763596 # Number of bytes of host memory used -host_seconds 4897.00 # Real time elapsed on the host -sim_insts 853019792 # Number of instructions simulated -sim_ops 1003201701 # Number of ops (including micro ops) simulated +host_inst_rate 181000 # Simulator instruction rate (inst/s) +host_op_rate 212908 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9614368962 # Simulator tick rate (ticks/s) +host_mem_usage 772236 # Number of bytes of host memory used +host_seconds 4938.15 # Real time elapsed on the host +sim_insts 893806699 # Number of instructions simulated +sim_ops 1051369194 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 65472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7833792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 12003144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10766848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 71104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 69248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2839488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 7678416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 7994432 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 439552 # Number of bytes read from this memory -system.physmem.bytes_read::total 49825880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7833792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2839488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10673280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 62800512 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 125376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 108736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7965248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14333320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15086080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 149568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 136256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3627008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 11510096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 14847104 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 436288 # Number of bytes read from this memory +system.physmem.bytes_read::total 68325080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7965248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3627008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11592256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 80335616 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 62821096 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1006 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 122403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 187562 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 168232 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1111 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 44367 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 119988 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 124913 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6868 # Number of read requests responded to by this memory -system.physmem.num_reads::total 778555 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 981258 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 80356200 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 124457 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 223971 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 235720 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2129 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56672 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 179858 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 231986 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6817 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1067605 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1255244 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 983832 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 165389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 253413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 227312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 162108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 168780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1051935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 165389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 225337 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1325858 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1257818 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 167770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 301899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 317754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 76395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 242434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 312721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1439114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 167770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 76395 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 244165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1692089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1326292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1325858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 165389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 253847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 227312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 162108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 168780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2378227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 778555 # Number of read requests accepted -system.physmem.writeReqs 1622091 # Number of write requests accepted -system.physmem.readBursts 778555 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1622091 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 49803520 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue -system.physmem.bytesWritten 100652928 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 49825880 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 103669672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 49366 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 111816 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 42060 # Per bank write bursts -system.physmem.perBankRdBursts::1 53156 # Per bank write bursts -system.physmem.perBankRdBursts::2 42442 # Per bank write bursts -system.physmem.perBankRdBursts::3 47567 # Per bank write bursts -system.physmem.perBankRdBursts::4 45723 # Per bank write bursts -system.physmem.perBankRdBursts::5 54413 # Per bank write bursts -system.physmem.perBankRdBursts::6 50594 # Per bank write bursts -system.physmem.perBankRdBursts::7 44772 # Per bank write bursts -system.physmem.perBankRdBursts::8 41306 # Per bank write bursts -system.physmem.perBankRdBursts::9 93457 # Per bank write bursts -system.physmem.perBankRdBursts::10 34541 # Per bank write bursts -system.physmem.perBankRdBursts::11 47870 # Per bank write bursts -system.physmem.perBankRdBursts::12 47765 # Per bank write bursts -system.physmem.perBankRdBursts::13 46143 # Per bank write bursts -system.physmem.perBankRdBursts::14 39677 # Per bank write bursts -system.physmem.perBankRdBursts::15 46694 # Per bank write bursts -system.physmem.perBankWrBursts::0 94318 # Per bank write bursts -system.physmem.perBankWrBursts::1 104450 # Per bank write bursts -system.physmem.perBankWrBursts::2 99318 # Per bank write bursts -system.physmem.perBankWrBursts::3 101345 # Per bank write bursts -system.physmem.perBankWrBursts::4 99792 # Per bank write bursts -system.physmem.perBankWrBursts::5 104837 # Per bank write bursts -system.physmem.perBankWrBursts::6 100210 # Per bank write bursts -system.physmem.perBankWrBursts::7 98464 # Per bank write bursts -system.physmem.perBankWrBursts::8 93421 # Per bank write bursts -system.physmem.perBankWrBursts::9 95649 # Per bank write bursts -system.physmem.perBankWrBursts::10 88541 # Per bank write bursts -system.physmem.perBankWrBursts::11 99820 # Per bank write bursts -system.physmem.perBankWrBursts::12 96824 # Per bank write bursts -system.physmem.perBankWrBursts::13 96750 # Per bank write bursts -system.physmem.perBankWrBursts::14 94484 # Per bank write bursts -system.physmem.perBankWrBursts::15 104479 # Per bank write bursts +system.physmem.bw_write::total 1692523 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1692089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 167770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 302333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 317754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 76395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 242434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 312721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3131637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1067605 # Number of read requests accepted +system.physmem.writeReqs 1929186 # Number of write requests accepted +system.physmem.readBursts 1067605 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1929186 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 68309056 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue +system.physmem.bytesWritten 120257344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 68325080 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 123323752 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 50133 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 117648 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 62386 # Per bank write bursts +system.physmem.perBankRdBursts::1 65796 # Per bank write bursts +system.physmem.perBankRdBursts::2 60427 # Per bank write bursts +system.physmem.perBankRdBursts::3 63507 # Per bank write bursts +system.physmem.perBankRdBursts::4 66319 # Per bank write bursts +system.physmem.perBankRdBursts::5 73621 # Per bank write bursts +system.physmem.perBankRdBursts::6 69221 # Per bank write bursts +system.physmem.perBankRdBursts::7 63591 # Per bank write bursts +system.physmem.perBankRdBursts::8 61143 # Per bank write bursts +system.physmem.perBankRdBursts::9 115825 # Per bank write bursts +system.physmem.perBankRdBursts::10 59973 # Per bank write bursts +system.physmem.perBankRdBursts::11 66407 # Per bank write bursts +system.physmem.perBankRdBursts::12 58867 # Per bank write bursts +system.physmem.perBankRdBursts::13 61123 # Per bank write bursts +system.physmem.perBankRdBursts::14 58743 # Per bank write bursts +system.physmem.perBankRdBursts::15 60380 # Per bank write bursts +system.physmem.perBankWrBursts::0 115877 # Per bank write bursts +system.physmem.perBankWrBursts::1 122877 # Per bank write bursts +system.physmem.perBankWrBursts::2 115996 # Per bank write bursts +system.physmem.perBankWrBursts::3 119851 # Per bank write bursts +system.physmem.perBankWrBursts::4 119313 # Per bank write bursts +system.physmem.perBankWrBursts::5 126432 # Per bank write bursts +system.physmem.perBankWrBursts::6 119028 # Per bank write bursts +system.physmem.perBankWrBursts::7 120185 # Per bank write bursts +system.physmem.perBankWrBursts::8 118113 # Per bank write bursts +system.physmem.perBankWrBursts::9 119452 # Per bank write bursts +system.physmem.perBankWrBursts::10 113141 # Per bank write bursts +system.physmem.perBankWrBursts::11 117109 # Per bank write bursts +system.physmem.perBankWrBursts::12 112676 # Per bank write bursts +system.physmem.perBankWrBursts::13 113553 # Per bank write bursts +system.physmem.perBankWrBursts::14 112771 # Per bank write bursts +system.physmem.perBankWrBursts::15 112647 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 276 # Number of times write queue was full causing retry -system.physmem.totGap 47365944763000 # Total gap between requests +system.physmem.numWrRetry 226 # Number of times write queue was full causing retry +system.physmem.totGap 47477177227000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 778525 # Read request sizes (log2) +system.physmem.readPktSize::6 1067575 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1619517 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 550292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 82276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 20492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 18686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 17057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 12648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 158 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1926612 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 704225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 50762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 38076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 32557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 29624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 27261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 21025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 5650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 566 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -188,167 +188,153 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 40446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 59954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 84735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 94224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 98939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 95817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 91113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 85467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 82456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 78613 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 873 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 836953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 179.765373 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 108.063876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 253.948875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 534704 63.89% 63.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 162086 19.37% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 38261 4.57% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 18116 2.16% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12763 1.52% 91.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8799 1.05% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6603 0.79% 93.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6067 0.72% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 49554 5.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 836953 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 65558 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 11.869901 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 153.975731 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 65556 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 45205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 65288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 93465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 105702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 113971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 112162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 108444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 104050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 100974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 97727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 97663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 116214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 104741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 100206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 114790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 102548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 96204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 91928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1389 # 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What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1080190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 174.567156 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 106.861850 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.135229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 694007 64.25% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 206792 19.14% 83.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51978 4.81% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24974 2.31% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18580 1.72% 92.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11712 1.08% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8387 0.78% 94.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7821 0.72% 94.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 55939 5.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1080190 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 83578 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.770071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 136.461901 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 83575 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 65558 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 65558 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.989475 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.876910 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.036255 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 57911 88.34% 88.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 3625 5.53% 93.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 1537 2.34% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 756 1.15% 97.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 457 0.70% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 339 0.52% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 446 0.68% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 180 0.27% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 59 0.09% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 25 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 57 0.09% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 41 0.06% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 16 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 6 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.00% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 7 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 6 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 4 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 12 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 9 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 13 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 20 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 65558 # Writes before turning the bus around for reads -system.physmem.totQLat 24526926504 # Total ticks spent queuing -system.physmem.totMemAccLat 39117801504 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3890900000 # Total ticks spent in databus transfers -system.physmem.avgQLat 31518.32 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 83578 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 83578 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.482244 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.955849 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.755182 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 75860 90.77% 90.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 5202 6.22% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 1276 1.53% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 755 0.90% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 241 0.29% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 100 0.12% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 48 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 8 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 9 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 10 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 17 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 25 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-671 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1056-1087 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 83578 # Writes before turning the bus around for reads +system.physmem.totQLat 40962619238 # Total ticks spent queuing +system.physmem.totMemAccLat 60975037988 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5336645000 # Total ticks spent in databus transfers +system.physmem.avgQLat 38378.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 50268.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.19 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 57128.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.72 # Average write queue length when enqueuing -system.physmem.readRowHits 582169 # Number of row buffer hits during reads -system.physmem.writeRowHits 931750 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.24 # Row buffer hit rate for writes -system.physmem.avgGap 19730499.53 # Average gap between requests -system.physmem.pageHitRate 64.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3287730600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1793900625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2969101200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5201632080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1175633111385 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27388306372500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31670904725190 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.643023 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45562569995604 # Time in different power states -system.physmem_0.memoryStateTime::REF 1581652800000 # Time in different power states +system.physmem.avgRdQLen 1.20 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.74 # Average write queue length when enqueuing +system.physmem.readRowHits 799066 # Number of row buffer hits during reads +system.physmem.writeRowHits 1067089 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 56.79 # Row buffer hit rate for writes +system.physmem.avgGap 15842672.12 # Average gap between requests +system.physmem.pageHitRate 63.34 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4225820760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2305755375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4093954800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6217942320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3100978164960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1196990920755 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27436312080750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31751124639720 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.766110 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45642284556030 # Time in different power states +system.physmem_0.memoryStateTime::REF 1585367160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 221716854896 # Time in different power states +system.physmem_0.memoryStateTime::ACT 249523460470 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3039558480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1658489250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3100125600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4989373200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1167524389710 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27395419294500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31669444107540 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.612186 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45574402608448 # Time in different power states -system.physmem_1.memoryStateTime::REF 1581652800000 # Time in different power states +system.physmem_1.actEnergy 3940415640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2150028375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4231125600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5958113760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3100978164960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1192295919105 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27440430503250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31749984270690 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.742090 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45649112064952 # Time in different power states +system.physmem_1.memoryStateTime::REF 1585367160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 209885438552 # Time in different power states +system.physmem_1.memoryStateTime::ACT 242698243548 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -379,18 +365,18 @@ system.realview.nvmem.bw_total::total 28 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 133649210 # Number of BP lookups -system.cpu0.branchPred.condPredicted 93568356 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6412350 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 100434532 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 71867706 # Number of BTB hits +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 146228375 # Number of BP lookups +system.cpu0.branchPred.condPredicted 102974776 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6711039 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 109409110 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 78811291 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.556769 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16148203 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1115497 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.033573 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17518133 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1190785 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -421,67 +407,62 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 281840 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 281840 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8577 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76588 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 281840 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 281840 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 281840 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 85165 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 18850.134868 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17191.967454 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 12262.040349 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 80924 95.02% 95.02% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3552 4.17% 99.19% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 385 0.45% 99.64% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 20 0.02% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 25 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 16 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 85165 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 302414 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 302414 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9161 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80364 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 302414 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 302414 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 302414 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 89525 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 18873.046300 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17079.714221 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14739.219535 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 88579 98.94% 98.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 783 0.87% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 49 0.05% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 43 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 89525 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 76588 89.93% 89.93% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 8577 10.07% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 85165 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 281840 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 80364 89.77% 89.77% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9161 10.23% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 89525 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302414 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 281840 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85165 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302414 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89525 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85165 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 367005 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89525 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 391939 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 86621651 # DTB read hits -system.cpu0.dtb.read_misses 235326 # DTB read misses -system.cpu0.dtb.write_hits 77269391 # DTB write hits -system.cpu0.dtb.write_misses 46514 # DTB write misses +system.cpu0.dtb.read_hits 94852147 # DTB read hits +system.cpu0.dtb.read_misses 252189 # DTB read misses +system.cpu0.dtb.write_hits 83443537 # DTB write hits +system.cpu0.dtb.write_misses 50225 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36825 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2231 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9213 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36113 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2068 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9574 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11443 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 86856977 # DTB read accesses -system.cpu0.dtb.write_accesses 77315905 # DTB write accesses +system.cpu0.dtb.perms_faults 10663 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 95104336 # DTB read accesses +system.cpu0.dtb.write_accesses 83493762 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 163891042 # DTB hits -system.cpu0.dtb.misses 281840 # DTB misses -system.cpu0.dtb.accesses 164172882 # DTB accesses +system.cpu0.dtb.hits 178295684 # DTB hits +system.cpu0.dtb.misses 302414 # DTB misses +system.cpu0.dtb.accesses 178598098 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -511,191 +492,187 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 66347 # Table walker walks requested -system.cpu0.itb.walker.walksLong 66347 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 679 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58898 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 66347 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 66347 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 66347 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 59577 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 21233.631049 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 19420.255520 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 13392.583355 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 54894 92.14% 92.14% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3878 6.51% 98.65% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 278 0.47% 99.12% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 464 0.78% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 21 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 10 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 59577 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 66598 # Table walker walks requested +system.cpu0.itb.walker.walksLong 66598 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 516 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54284 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 66598 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 66598 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 66598 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 54800 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 21262.637080 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 19017.155066 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 16721.874177 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 53728 98.04% 98.04% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 946 1.73% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 48 0.09% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 54 0.10% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 9 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 54800 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 58898 98.86% 98.86% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 679 1.14% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 59577 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 54284 99.06% 99.06% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 516 0.94% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 54800 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66347 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66347 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66598 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66598 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59577 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59577 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 125924 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 239632917 # ITB inst hits -system.cpu0.itb.inst_misses 66347 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54800 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54800 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 121398 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 261387859 # ITB inst hits +system.cpu0.itb.inst_misses 66598 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26379 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 25865 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 196328 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 223375 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 239699264 # ITB inst accesses -system.cpu0.itb.hits 239632917 # DTB hits -system.cpu0.itb.misses 66347 # DTB misses -system.cpu0.itb.accesses 239699264 # DTB accesses -system.cpu0.numCycles 955623985 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 261454457 # ITB inst accesses +system.cpu0.itb.hits 261387859 # DTB hits +system.cpu0.itb.misses 66598 # DTB misses +system.cpu0.itb.accesses 261454457 # DTB accesses +system.cpu0.numCycles 1029830596 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 445844997 # Number of instructions committed -system.cpu0.committedOps 524389125 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 43457031 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4220 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93776986984 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.143400 # CPI: cycles per instruction -system.cpu0.ipc 0.466549 # IPC: instructions per cycle +system.cpu0.committedInsts 487755400 # Number of instructions committed +system.cpu0.committedOps 573075495 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 47715438 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4391 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93925247519 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.111367 # CPI: cycles per instruction +system.cpu0.ipc 0.473627 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13187 # number of quiesce instructions executed -system.cpu0.tickCycles 717454138 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 238169847 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5506052 # number of replacements -system.cpu0.dcache.tags.tagsinuse 502.001203 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155497940 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5506563 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.238656 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 13314 # number of quiesce instructions executed +system.cpu0.tickCycles 777849504 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 251981092 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5902107 # number of replacements +system.cpu0.dcache.tags.tagsinuse 475.000126 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 169363182 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5902609 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.692936 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 5093256500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.001203 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980471 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.980471 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 330491760 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 330491760 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79543100 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 79543100 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 71719508 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 71719508 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 278613 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 278613 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 256505 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 256505 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1617523 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1617523 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1589938 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1589938 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 151262608 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 151262608 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 151541221 # number of overall hits -system.cpu0.dcache.overall_hits::total 151541221 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3339841 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3339841 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2311852 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2311852 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 620748 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 620748 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 822680 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 822680 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 157499 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 157499 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 183638 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 183638 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5651693 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5651693 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6272441 # number of overall misses -system.cpu0.dcache.overall_misses::total 6272441 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 49670372012 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 49670372012 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 43497452544 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 43497452544 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 32835554230 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32835554230 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2312206455 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2312206455 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3898320876 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3898320876 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3663000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3663000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 93167824556 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 93167824556 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 93167824556 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 93167824556 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 82882941 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 82882941 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74031360 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74031360 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899361 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 899361 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1079185 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1079185 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1775022 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1775022 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1773576 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1773576 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 156914301 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 156914301 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 157813662 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 157813662 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040296 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.040296 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031228 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.031228 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.690210 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.690210 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.762316 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.762316 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088731 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088731 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103541 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103541 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036018 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.036018 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039746 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.039746 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14872.076848 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14872.076848 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18814.981471 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18814.981471 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 39912.911740 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39912.911740 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14680.769116 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14680.769116 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21228.290855 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21228.290855 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.000126 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.927735 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.927735 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 502 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 153 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.980469 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 359562725 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 359562725 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 86974547 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86974547 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 77401946 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 77401946 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 298185 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 298185 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 275916 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 275916 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1961524 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1961524 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1923644 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1923644 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 164376493 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 164376493 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 164674678 # number of overall hits +system.cpu0.dcache.overall_hits::total 164674678 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3650210 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3650210 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2435892 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2435892 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670224 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 670224 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 817849 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 817849 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 165967 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 165967 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202383 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 202383 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 6086102 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6086102 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6756326 # number of overall misses +system.cpu0.dcache.overall_misses::total 6756326 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 55969500387 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 55969500387 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 47032436273 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 47032436273 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 33507618312 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 33507618312 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2441854002 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2441854002 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4283229947 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4283229947 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1855000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1855000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 103001936660 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 103001936660 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 103001936660 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 103001936660 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 90624757 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 90624757 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 79837838 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 79837838 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 968409 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 968409 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093765 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1093765 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2127491 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2127491 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2126027 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2126027 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 170462595 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 170462595 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 171431004 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 171431004 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040278 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.040278 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030510 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.030510 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.692088 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.692088 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.747737 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.747737 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.078011 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078011 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095193 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095193 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.035703 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.035703 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039411 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.039411 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15333.227509 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15333.227509 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19308.095873 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19308.095873 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40970.421572 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 40970.421572 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14712.888719 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14712.888719 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21163.980903 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21163.980903 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16484.940806 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16484.940806 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14853.519476 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14853.519476 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16924.122642 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16924.122642 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15245.258541 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15245.258541 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -704,161 +681,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3760610 # number of writebacks -system.cpu0.dcache.writebacks::total 3760610 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 413115 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 413115 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 966709 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 966709 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 96 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 96 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 42490 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 42490 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 52 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 52 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1379824 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1379824 # 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number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1454810141 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1454810141 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3611856094 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3611856094 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3160000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3160000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61199923420 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 61199923420 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74408242859 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 74408242859 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5916157251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5916157251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5692664250 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5692664250 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11608821501 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11608821501 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035312 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035312 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018170 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018170 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.683798 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.683798 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762227 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.762227 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064793 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064793 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103512 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103512 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027224 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027224 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030966 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030966 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12868.566149 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12868.566149 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17497.884083 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17497.884083 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21477.605713 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21477.605713 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38406.254280 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 38406.254280 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12649.533002 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12649.533002 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19673.919003 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19673.919003 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3966592 # number of writebacks +system.cpu0.dcache.writebacks::total 3966592 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 443574 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 443574 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1010368 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1010368 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 102 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 102 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43626 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43626 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 27 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 27 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1453942 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1453942 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1453942 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1453942 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3206636 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3206636 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1425524 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1425524 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664815 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 664815 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 817747 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 817747 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122341 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 122341 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202356 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 202356 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4632160 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4632160 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5296975 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5296975 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31604 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31604 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30977 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 30977 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62581 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62581 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42580313466 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42580313466 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25667045166 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25667045166 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14837829930 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14837829930 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 32271814438 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 32271814438 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1568491891 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1568491891 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3969414040 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3969414040 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1696000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1696000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 68247358632 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 68247358632 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 83085188562 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 83085188562 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5612600750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5612600750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5285393252 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5285393252 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10897994002 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10897994002 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035384 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035384 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017855 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017855 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.686502 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.686502 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.747644 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.747644 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057505 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057505 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095180 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095180 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027174 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027174 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030899 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030899 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13278.811024 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13278.811024 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18005.340609 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18005.340609 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22318.735182 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22318.735182 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39464.301842 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39464.301842 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12820.656125 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12820.656125 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19615.993793 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19615.993793 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14326.264083 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14326.264083 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15226.217882 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15226.217882 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177881.393036 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177881.393036 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171657.095257 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171657.095257 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174773.742149 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174773.742149 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14733.376790 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14733.376790 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15685.403190 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15685.403190 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177591.467852 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177591.467852 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170623.147884 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170623.147884 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174142.215720 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174142.215720 # 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Cycle average of tags in use +system.cpu0.icache.tags.total_refs 250868144 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 10290248 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.379213 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 24018555250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930282 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 266 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 488854379 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 488854379 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 229434949 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 229434949 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 229434949 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 229434949 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 229434949 # number of overall hits -system.cpu0.icache.overall_hits::total 229434949 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9994827 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9994827 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9994827 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9994827 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9994827 # number of overall misses -system.cpu0.icache.overall_misses::total 9994827 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 98560798487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 98560798487 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 98560798487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 98560798487 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 98560798487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 98560798487 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 239429776 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 239429776 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 239429776 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 239429776 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 239429776 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 239429776 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.041744 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.041744 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.041744 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.041744 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.041744 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.041744 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9861.181038 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9861.181038 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9861.181038 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9861.181038 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9861.181038 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9861.181038 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 532607059 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 532607059 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 250868144 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 250868144 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 250868144 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 250868144 # 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number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 101454150461 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 101454150461 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 261158401 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 261158401 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 261158401 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 261158401 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 261158401 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 261158401 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039402 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.039402 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039402 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.039402 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039402 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.039402 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9859.243599 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9859.243599 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9859.243599 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9859.243599 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9859.243599 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9859.243599 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -867,467 +844,462 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9994827 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9994827 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9994827 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9994827 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9994827 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9994827 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10290257 # 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number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88537189453 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 88537189453 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 88537189453 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 88537189453 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 91134485035 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 91134485035 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 91134485035 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 91134485035 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 91134485035 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 91134485035 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.041744 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.041744 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.041744 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8858.301345 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8858.301345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8858.301345 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039402 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039402 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039402 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.039402 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039402 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.039402 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8856.385709 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8856.385709 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8856.385709 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8856.385709 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8856.385709 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8856.385709 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92413.964670 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92413.964670 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7230073 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7233896 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 3309 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8031555 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8035489 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 3395 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # 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Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3504.905506 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 877.594600 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.353636 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004504 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004493 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.352642 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.213922 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.053564 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982762 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1351 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14265 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 52 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 263 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 985 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 705 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5210 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7781 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 446 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082458 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.870667 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 331999507 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 331999507 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 494334 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 160804 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 9208783 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2710357 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 12574278 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3760607 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3760607 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 232072 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 232072 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 101378 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 101378 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33994 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 33994 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 863447 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 863447 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 494334 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 160804 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 9208783 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3573804 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 13437725 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 494334 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 160804 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 9208783 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3573804 # number of overall hits -system.cpu0.l2cache.overall_hits::total 13437725 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10659 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7834 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 786043 # 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number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3121911280 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3089998 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3089998 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12386704821 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 12386704821 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 318928487 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 253391761 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23635812248 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 43306876902 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 67515009398 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 318928487 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 253391761 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23635812248 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 43306876902 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 67515009398 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 504993 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 168638 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 9994826 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3656387 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 14324844 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3760609 # 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Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.479413 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4176.151665 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3206.986567 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 995.905932 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.459673 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005048 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004851 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.254892 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.195739 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.060785 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 671 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4595 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6778 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2297 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.084167 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.885559 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 347615506 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 347615506 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522089 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 157285 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 9486915 # 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mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252041 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.217482 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.217482 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022499 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049763 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078067 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.251858 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.131688 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022499 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049763 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078067 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.251858 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.174466 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26070.333025 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24914.421505 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39284.329024 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 39284.329024 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42944.709754 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42944.709754 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20269.613166 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20269.613166 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14936.844150 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14936.844150 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 441333 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 441333 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 37752.863775 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 37752.863775 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28603.508173 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26584.661076 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28603.508173 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39284.329024 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 29812.315639 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.178514 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27473.220807 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25880.813515 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48160.836260 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48160.836260 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43640.937143 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43640.937143 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20345.789725 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20345.789725 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14744.179820 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14744.179820 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 712749.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 712749.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41400.167567 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41400.167567 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30245.364016 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27775.872116 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30245.364016 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48160.836260 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33122.966054 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169879.438648 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117349.075567 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164156.605253 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164156.605253 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169590.676813 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 116204.246166 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163122.558640 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163122.558640 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 167022.157568 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130423.203261 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 166389.019814 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128854.728074 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 16764997 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14635279 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33163 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3760609 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 997781 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1159753 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 821059 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 475624 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 336764 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 482191 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1257493 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1141567 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20094267 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16118866 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1099589 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 37679488 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 643016512 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 607271415 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1349104 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4039944 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1255676975 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4414025 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 24791334 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.197604 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.398192 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 17664917 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 15307376 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 30977 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3966591 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1103078 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166462 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 816287 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 481802 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368927 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 516230 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1338230 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1206066 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20685127 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17177406 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 364539 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1170846 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 39397918 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 661924032 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 645723507 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1324200 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4272848 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1313244587 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4794163 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 26128529 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.203121 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.402322 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 19892474 80.24% 80.24% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4898860 19.76% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 20821287 79.69% 79.69% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 5307242 20.31% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 24791334 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14940946397 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 26128529 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 15626998682 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 210442490 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 207003480 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 15097277267 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 15540735463 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7911607131 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8534595583 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 198319454 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 199309237 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 594828175 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 637104704 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 123549187 # Number of BP lookups -system.cpu1.branchPred.condPredicted 87841692 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5708078 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 93157119 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 67436708 # Number of BTB hits +system.cpu1.branchPred.lookups 125576312 # Number of BP lookups +system.cpu1.branchPred.condPredicted 90437850 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5588126 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 96414800 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 70448335 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.390289 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 14460012 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 934859 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.067968 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 14240452 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 921306 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1357,65 +1329,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 259362 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 259362 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8416 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76621 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 259362 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 259362 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 259362 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 85037 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 18225.042946 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 16628.571422 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 11774.469557 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 81545 95.89% 95.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2790 3.28% 99.17% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 403 0.47% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 25 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 11 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 9 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 14 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 85037 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1261494444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1261494444 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1261494444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 76621 90.10% 90.10% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8416 9.90% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 85037 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259362 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 267188 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 267188 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10577 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85745 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 267188 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 267188 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 267188 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 96322 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19417.832759 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17582.202051 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14852.958051 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 91721 95.22% 95.22% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3398 3.53% 98.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 602 0.62% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 416 0.43% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 24 0.02% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 24 0.02% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 36 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 19 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 31 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 34 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 96322 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1244507444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1244507444 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1244507444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 85745 89.02% 89.02% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10577 10.98% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 96322 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 267188 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259362 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85037 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 267188 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 96322 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85037 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 344399 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 96322 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 363510 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 80542266 # DTB read hits -system.cpu1.dtb.read_misses 214982 # DTB read misses -system.cpu1.dtb.write_hits 69249357 # DTB write hits -system.cpu1.dtb.write_misses 44380 # DTB write misses +system.cpu1.dtb.read_hits 79480191 # DTB read hits +system.cpu1.dtb.read_misses 220503 # DTB read misses +system.cpu1.dtb.write_hits 69950509 # DTB write hits +system.cpu1.dtb.write_misses 46685 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 35601 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 736 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6438 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 40279 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1007 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7671 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9960 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 80757248 # DTB read accesses -system.cpu1.dtb.write_accesses 69293737 # DTB write accesses +system.cpu1.dtb.perms_faults 12807 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 79700694 # DTB read accesses +system.cpu1.dtb.write_accesses 69997194 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 149791623 # DTB hits -system.cpu1.dtb.misses 259362 # DTB misses -system.cpu1.dtb.accesses 150050985 # DTB accesses +system.cpu1.dtb.hits 149430700 # DTB hits +system.cpu1.dtb.misses 267188 # DTB misses +system.cpu1.dtb.accesses 149697888 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1445,191 +1419,187 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 60478 # Table walker walks requested -system.cpu1.itb.walker.walksLong 60478 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 478 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50972 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 60478 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 60478 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 60478 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 51450 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 20568.513975 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 18499.951285 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 14805.800668 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 47723 92.76% 92.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 2940 5.71% 98.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 278 0.54% 99.01% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 425 0.83% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 16 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 27 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 51450 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1260837944 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1260837944 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1260837944 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 50972 99.07% 99.07% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 478 0.93% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 51450 # Table walker page sizes translated +system.cpu1.itb.walker.walks 64917 # Table walker walks requested +system.cpu1.itb.walker.walksLong 64917 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 645 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55496 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 64917 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 64917 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 64917 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 56141 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 22418.994977 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19682.840516 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 19289.014659 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 54677 97.39% 97.39% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1297 2.31% 99.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 81 0.14% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 18 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 56141 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1243919944 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1243919944 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1243919944 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 55496 98.85% 98.85% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 645 1.15% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 56141 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60478 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60478 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64917 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64917 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51450 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51450 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 111928 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 220701471 # ITB inst hits -system.cpu1.itb.inst_misses 60478 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56141 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56141 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 121058 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 225481249 # ITB inst hits +system.cpu1.itb.inst_misses 64917 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25765 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 28543 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 203408 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 202570 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 220761949 # ITB inst accesses -system.cpu1.itb.hits 220701471 # DTB hits -system.cpu1.itb.misses 60478 # DTB misses -system.cpu1.itb.accesses 220761949 # DTB accesses -system.cpu1.numCycles 819495419 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 225546166 # ITB inst accesses +system.cpu1.itb.hits 225481249 # DTB hits +system.cpu1.itb.misses 64917 # DTB misses +system.cpu1.itb.accesses 225546166 # DTB accesses +system.cpu1.numCycles 849119079 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 407174795 # Number of instructions committed -system.cpu1.committedOps 478812576 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 42038613 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5231 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93913157476 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.012638 # CPI: cycles per instruction -system.cpu1.ipc 0.496860 # IPC: instructions per cycle +system.cpu1.committedInsts 406051299 # Number of instructions committed +system.cpu1.committedOps 478293699 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 46606937 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5644 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 94106060514 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.091162 # CPI: cycles per instruction +system.cpu1.ipc 0.478203 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5271 # number of quiesce instructions executed -system.cpu1.tickCycles 656184177 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 163311242 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 4776829 # number of replacements -system.cpu1.dcache.tags.tagsinuse 427.655512 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 142582647 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4777341 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.845608 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8380053198500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 427.655512 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.835265 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.835265 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 5757 # number of quiesce instructions executed +system.cpu1.tickCycles 666946808 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 182172271 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5052284 # number of replacements +system.cpu1.dcache.tags.tagsinuse 457.990994 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 141727438 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5052796 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.049309 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8380007678500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.990994 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.894514 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.894514 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 302037341 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 302037341 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 73896099 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 73896099 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 64629380 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 64629380 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 204586 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 204586 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 67650 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 67650 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1684264 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1684264 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1653940 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1653940 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 138525479 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 138525479 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 138730065 # number of overall hits -system.cpu1.dcache.overall_hits::total 138730065 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3123049 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3123049 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2001792 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2001792 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 560125 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 560125 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 418714 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 418714 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158898 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 158898 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187849 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 187849 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5124841 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5124841 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5684966 # number of overall misses -system.cpu1.dcache.overall_misses::total 5684966 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43997999443 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 43997999443 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 34323796172 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 34323796172 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11321642584 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11321642584 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2327905715 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2327905715 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3931505754 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3931505754 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3098000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3098000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 78321795615 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 78321795615 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 78321795615 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 78321795615 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 77019148 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 77019148 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 66631172 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 66631172 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 764711 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 764711 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 486364 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 486364 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1843162 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1843162 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1841789 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1841789 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 143650320 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 143650320 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 144415031 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 144415031 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040549 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.040549 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030043 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030043 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.732466 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.732466 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.860907 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.860907 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086209 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086209 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101993 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101993 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035676 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035676 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039365 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.039365 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14088.155339 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14088.155339 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17146.534791 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17146.534791 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27039.082964 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27039.082964 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14650.314762 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14650.314762 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20929.074704 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20929.074704 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 301466109 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 301466109 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 72704936 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 72704936 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 65165576 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 65165576 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 206723 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 206723 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 46881 # 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number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1256500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1256500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 89649293045 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 89649293045 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 89649293045 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 89649293045 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 75912122 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 75912122 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 67414735 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 67414735 # 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average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28390.678490 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 28390.678490 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15751.617962 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15751.617962 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21175.726324 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21175.726324 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15282.775722 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15282.775722 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13777.003348 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13777.003348 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16430.283101 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16430.283101 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14656.775030 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14656.775030 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1638,161 +1608,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3038485 # number of writebacks -system.cpu1.dcache.writebacks::total 3038485 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 341138 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 341138 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 817934 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 817934 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 47 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 47 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39869 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39869 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 63 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 63 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1159072 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1159072 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1159072 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1159072 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2781911 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2781911 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1183858 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1183858 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 559909 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 559909 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 418667 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 418667 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119029 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119029 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 187786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 3965769 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 3965769 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4525678 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4525678 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5083 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5083 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5087 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5087 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10170 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10170 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34163110205 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34163110205 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 18897365962 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18897365962 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10922522145 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 10922522145 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10687856416 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10687856416 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1507570159 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1507570159 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640144702 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640144702 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2571500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2571500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 53060476167 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 53060476167 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 63982998312 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 63982998312 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 518115500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 518115500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 583373999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 583373999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1101489499 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1101489499 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036120 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036120 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017767 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017767 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.732184 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.732184 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.860810 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.860810 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064579 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064579 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101958 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101958 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027607 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027607 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031338 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031338 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12280.446860 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12280.446860 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15962.527568 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15962.527568 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19507.673827 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19507.673827 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25528.299140 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25528.299140 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12665.570231 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12665.570231 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19384.537197 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19384.537197 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3294639 # number of writebacks +system.cpu1.dcache.writebacks::total 3294639 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 376716 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 376716 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 934861 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 934861 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 50 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 50 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39920 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39920 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 26 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 26 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1311577 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1311577 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1311577 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1311577 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2830470 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2830470 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1314298 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1314298 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 659943 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 659943 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 426357 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 426357 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 121056 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 121056 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 201939 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 201939 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4144768 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4144768 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4804711 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4804711 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7026 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7026 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7515 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7515 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14541 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14541 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38398702439 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38398702439 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21764603493 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21764603493 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13372610673 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13372610673 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11459992206 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11459992206 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1620200910 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1620200910 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3963729421 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3963729421 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1148000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1148000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60163305932 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 60163305932 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 73535916605 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 73535916605 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 828088750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 828088750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 987688750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 987688750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1815777500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1815777500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037286 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037286 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019496 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019496 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.761219 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.761219 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.900841 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.900841 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069281 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069281 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.115653 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.115653 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028918 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028918 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033321 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033321 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13566.193049 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13566.193049 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16559.869598 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16559.869598 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20263.281333 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20263.281333 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26878.864909 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26878.864909 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13383.895966 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13383.895966 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19628.350249 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19628.350249 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13379.618472 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13379.618472 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14137.770807 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14137.770807 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 101931.044659 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 101931.044659 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114679.378612 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 114679.378612 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 108307.718682 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 108307.718682 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14515.482153 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14515.482153 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15304.961444 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15304.961444 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117860.624822 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 117860.624822 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 131428.975383 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 131428.975383 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124872.945465 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124872.945465 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 8549825 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.203595 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 211942190 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8550337 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 24.787583 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8370006207500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.203595 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990632 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990632 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 8512500 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.044267 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 216759728 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8513012 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.462166 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8369990866500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.044267 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990321 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990321 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 449535393 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 449535393 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 211942190 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 211942190 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 211942190 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 211942190 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 211942190 # number of overall hits -system.cpu1.icache.overall_hits::total 211942190 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8550338 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8550338 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8550338 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8550338 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8550338 # number of overall misses -system.cpu1.icache.overall_misses::total 8550338 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 84064963562 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 84064963562 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 84064963562 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 84064963562 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 84064963562 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 84064963562 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 220492528 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 220492528 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 220492528 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 220492528 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 220492528 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 220492528 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038778 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.038778 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038778 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.038778 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038778 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.038778 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9831.770810 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9831.770810 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9831.770810 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9831.770810 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9831.770810 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9831.770810 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 459058494 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 459058494 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 216759728 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 216759728 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 216759728 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 216759728 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 216759728 # number of overall hits +system.cpu1.icache.overall_hits::total 216759728 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8513013 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8513013 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8513013 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 8513013 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 8513013 # number of overall misses +system.cpu1.icache.overall_misses::total 8513013 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 85304905568 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 85304905568 # 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miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.037790 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037790 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.037790 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037790 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.037790 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10020.530401 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10020.530401 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10020.530401 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10020.530401 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10020.530401 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10020.530401 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1801,241 +1771,241 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8550338 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8550338 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8550338 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8550338 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8550338 # 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number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 75495426368 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 75495426368 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 75495426368 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 75495426368 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 75495426368 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 75495426368 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8549000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8549000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8549000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8549000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038778 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.038778 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.038778 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8829.525379 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8829.525379 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8829.525379 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94988.888889 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94988.888889 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94988.888889 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94988.888889 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 76768195856 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 76768195856 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 76768195856 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 76768195856 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 76768195856 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 76768195856 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8107000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8107000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8107000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8107000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037790 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037790 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037790 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.037790 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037790 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.037790 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9017.746814 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9017.746814 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9017.746814 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9017.746814 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9017.746814 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9017.746814 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90077.777778 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90077.777778 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90077.777778 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90077.777778 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6602862 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6604361 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 1239 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7158191 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7159863 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 1351 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 840391 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2149670 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13538.161783 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 13667574 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2165890 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.310373 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9806309103500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5443.099185 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 82.941597 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 88.885416 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3832.023077 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3147.321084 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 943.891423 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.332220 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005062 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005425 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.233888 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.192097 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057611 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.826304 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1444 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14725 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 436 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 846 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 141 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1094 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5482 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7066 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 978 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.088135 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.898743 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 283341479 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 283341479 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 455761 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 138301 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 7823529 # 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average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24691.283229 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48574.921562 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32389.394609 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32389.394609 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19532.523541 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19532.523541 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14695.402755 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14695.402755 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 937500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 937500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33990.973225 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33990.973225 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27653.845407 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25788.930330 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27653.845407 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31864.283112 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 109853.793054 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109497.154300 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123927.811045 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 123927.811045 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 117127.449969 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 116909.250906 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 15242466 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 12851003 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5087 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3038484 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 900400 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105427 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 417532 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 439071 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337307 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 446846 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1140783 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 991898 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17100855 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13710565 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 326713 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1037575 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 32175708 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 547227328 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 511521449 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1168464 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3734152 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1063651393 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4928167 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 22242259 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.242416 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.428544 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 15573132 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13012901 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7515 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3294638 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1065592 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1119456 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 424954 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 452600 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 368137 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 473527 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1269149 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1115295 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17026205 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14595450 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 357835 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1096931 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 33076421 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 544838528 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 546511254 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1311792 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4013488 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1096675062 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5302361 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 23181233 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.250406 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.433247 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 16850390 75.76% 75.76% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 5391869 24.24% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 17376502 74.96% 74.96% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 5804731 25.04% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 22242259 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 12259577677 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 23181233 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 12806281931 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 163507981 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 180531485 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 12835259097 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 12781520856 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7129308669 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7568960857 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 180853196 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 194234943 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 571040175 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 595690418 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40383 # Transaction distribution -system.iobus.trans_dist::ReadResp 40383 # Transaction distribution -system.iobus.trans_dist::WriteReq 136956 # Transaction distribution -system.iobus.trans_dist::WriteResp 29972 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106984 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47768 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40349 # Transaction distribution +system.iobus.trans_dist::ReadResp 40349 # Transaction distribution +system.iobus.trans_dist::WriteReq 136610 # Transaction distribution +system.iobus.trans_dist::WriteResp 29882 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47640 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2263,18 +2231,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122858 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231740 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122574 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354678 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47788 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47660 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2284,18 +2252,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155896 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155681 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513294 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36287000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496839 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36172000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2315,7 +2283,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2323,71 +2291,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 608916622 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607512131 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92889000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92695000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148804483 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148588668 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115850 # number of replacements -system.iocache.tags.tagsinuse 11.297267 # Cycle average of tags in use +system.iocache.tags.replacements 115637 # number of replacements +system.iocache.tags.tagsinuse 11.310069 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115866 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115653 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9129662020000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.840346 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.456922 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240022 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466058 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706079 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9129457632000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.399895 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.910174 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.462493 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.244386 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706879 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043187 # Number of tag accesses -system.iocache.tags.data_accesses 1043187 # Number of data accesses +system.iocache.tags.tag_accesses 1041045 # Number of tag accesses +system.iocache.tags.data_accesses 1041045 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8941 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106984 # 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number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1628429667 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1622865167 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1628429667 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8941 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106984 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106984 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8886 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8926 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8904 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8944 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8886 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8926 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2401,55 +2369,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141067.567568 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 185184.130317 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185001.197131 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182262.485063 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182089.326362 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186495.307308 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 186495.307308 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 184980.358727 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 184980.358727 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 111929 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185917.671989 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185917.671989 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182262.485063 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 182069.506597 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 182262.485063 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 182069.506597 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110288 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16372 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16227 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.836611 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.796574 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106949 # number of writebacks -system.iocache.writebacks::total 106949 # number of writebacks +system.iocache.writebacks::writebacks 106703 # number of writebacks +system.iocache.writebacks::total 106703 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8904 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8941 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106984 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106984 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8886 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8926 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8904 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8944 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8886 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8926 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3294500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1182279102 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1185573602 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8904 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8944 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1158690425 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1161960925 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14388800003 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14388800003 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3507500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1182279102 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1185786602 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3507500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1182279102 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1185786602 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14292687374 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14292687374 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1158690425 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1162173925 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1158690425 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1162173925 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2463,643 +2431,638 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 89040.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133049.640108 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 132867.152527 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130131.449349 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 129958.721060 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134494.877767 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134494.877767 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87687.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 133049.640108 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 132846.359175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87687.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 133049.640108 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 132846.359175 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133916.941890 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133916.941890 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 130131.449349 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 129938.945103 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 130131.449349 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 129938.945103 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1147719 # number of replacements -system.l2c.tags.tagsinuse 64326.028489 # Cycle average of tags in use -system.l2c.tags.total_refs 4694874 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1208975 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.883351 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8775850000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 21201.345204 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 99.174306 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 102.969089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6287.304380 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9789.287555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7119.681672 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 173.781032 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 211.002205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4753.478760 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6062.523137 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8525.481150 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.323507 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001513 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001571 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.095937 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.149373 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.108638 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002652 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003220 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.072532 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.092507 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.130089 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.981537 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9955 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 51081 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 63 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 299 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 192 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1433 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 7968 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 215 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2117 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 11769 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 36932 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.151901 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.779434 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 59123537 # Number of tag accesses -system.l2c.tags.data_accesses 59123537 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6743 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4986 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 715760 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 559628 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 328609 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6048 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4129 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 682361 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 522413 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 303271 # number of ReadReq hits -system.l2c.ReadReq_hits::total 3133948 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2214381 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.291814 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.182720 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 77530.939959 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75096.383201 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 93115.223128 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33593.299323 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31988.946630 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33294.710494 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17811.639681 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17792.369934 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17802.261793 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17820.316999 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17806.465496 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17814.164007 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76820.995171 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69205.261160 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 73892.985025 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77267.222173 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72970.748431 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 90070.760890 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77267.222173 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72970.748431 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 90070.760890 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9221859751 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5282500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1425966751 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13841121752 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.237974 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.295941 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.089846 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.192710 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.427262 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.269643 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.315641 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.074539 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.181320 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.431627 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.212132 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.770238 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.472421 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.683033 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.635002 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.589189 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.612759 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.601971 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590924 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.596503 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.618691 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.515549 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.571866 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.237974 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.295941 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.089846 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.256324 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.427262 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.269643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.315641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.074539 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.226930 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.431627 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.232022 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.237974 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.295941 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.089846 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.256324 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.427262 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.269643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.315641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.074539 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.226930 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.431627 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.232022 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72093.700926 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80918.630618 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71909.797212 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78953.022931 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 100443.793085 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33548.050591 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32025.022175 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33239.596409 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17799.416115 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.188394 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17801.177159 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17787.396188 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17809.571812 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17798.269170 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77295.267829 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72023.520979 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75137.639645 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72093.700926 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79612.576422 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71909.797212 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76804.697197 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 96995.072864 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72093.700926 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79612.576422 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71909.797212 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76804.697197 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 96995.072864 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 150351.356024 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63611.111111 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 74287.640228 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 94467.846634 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145636.010011 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88614.605858 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138052.535948 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 150061.012846 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58694.444444 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 90265.980923 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 94148.330129 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144601.849792 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 105381.038057 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 136944.559961 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147997.090572 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63611.111111 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81455.350118 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 107392.516300 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147358.779038 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58694.444444 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 98078.736571 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 106867.220149 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 709274 # Transaction distribution -system.membus.trans_dist::ReadResp 709274 # Transaction distribution -system.membus.trans_dist::WriteReq 38250 # Transaction distribution -system.membus.trans_dist::WriteResp 38250 # Transaction distribution -system.membus.trans_dist::Writeback 981258 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 638260 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 638259 # Transaction distribution -system.membus.trans_dist::UpgradeReq 441618 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 290995 # Transaction distribution -system.membus.trans_dist::UpgradeResp 111840 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 38 # Transaction distribution -system.membus.trans_dist::ReadExReq 127489 # Transaction distribution -system.membus.trans_dist::ReadExResp 110378 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122858 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 975380 # Transaction distribution +system.membus.trans_dist::ReadResp 975380 # Transaction distribution +system.membus.trans_dist::WriteReq 38492 # Transaction distribution +system.membus.trans_dist::WriteResp 38492 # Transaction distribution +system.membus.trans_dist::Writeback 1255244 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 671368 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 671368 # Transaction distribution +system.membus.trans_dist::UpgradeReq 435292 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 320448 # Transaction distribution +system.membus.trans_dist::UpgradeResp 117663 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution +system.membus.trans_dist::ReadExReq 151367 # Transaction distribution +system.membus.trans_dist::ReadExResp 133687 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122574 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25102 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4347669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4495681 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336711 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336711 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4832392 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5296349 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5445421 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5781341 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155681 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139364352 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 139571776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14131264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14131264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 153703040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 640714 # Total snoops (count) -system.membus.snoop_fanout::samples 3227461 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52892 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177552960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 177762857 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14095872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14095872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191858729 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 658635 # Total snoops (count) +system.membus.snoop_fanout::samples 3847839 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3227461 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3847839 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3227461 # Request fanout histogram -system.membus.reqLayer0.occupancy 110051499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3847839 # Request fanout histogram +system.membus.reqLayer0.occupancy 109654500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20984500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21898998 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9462597488 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 11397821385 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4943193797 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6506682845 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 152223017 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 152058832 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3143,45 +3106,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 4701983 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4694752 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38250 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2214381 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 919435 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 812281 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 489803 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 302708 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 792511 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 280473 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 280473 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7857713 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6052239 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 13909952 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 261128039 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 189974361 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 451102400 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1657293 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8947338 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012974 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.113161 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5105910 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5098639 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38492 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2490573 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 937823 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 830969 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 486096 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 332772 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 818868 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302211 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302211 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8322623 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6766752 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15089375 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 277489443 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 218349254 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 495838697 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1695482 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9694113 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.011945 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.108639 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 8831258 98.70% 98.70% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 116080 1.30% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9578315 98.81% 98.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115798 1.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8947338 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 7728831785 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9694113 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8435746901 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2539500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2506500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4493592227 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4797228870 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3891101888 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4287100444 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |