diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
| commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
| tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual | |
| parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
| download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual')
5 files changed, 3378 insertions, 3011 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini index 30060be32..ce640090c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -24,12 +25,12 @@ exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -59,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -87,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -109,6 +121,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -153,12 +166,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false system=system +threadPolicy=RoundRobin tracer=system.cpu0.tracer workload= dcache_port=system.cpu0.dcache.cpu_side @@ -174,11 +192,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu0.dcache] type=Cache @@ -187,12 +212,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -211,8 +241,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -235,9 +270,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -251,9 +291,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[3] @@ -647,12 +692,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -671,8 +721,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -730,9 +785,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -746,9 +806,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[2] @@ -759,12 +824,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu0.l2cache.prefetcher response_latency=12 @@ -782,6 +852,7 @@ mem_side=system.toL2Bus.slave[0] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -792,6 +863,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -808,8 +883,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -817,10 +897,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 @@ -852,6 +937,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -896,12 +982,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false system=system +threadPolicy=RoundRobin tracer=system.cpu1.tracer workload= dcache_port=system.cpu1.dcache.cpu_side @@ -917,11 +1008,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu1.dcache] type=Cache @@ -930,12 +1028,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -954,8 +1057,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -978,9 +1086,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -994,9 +1107,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[3] @@ -1390,12 +1508,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -1414,8 +1537,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -1473,9 +1601,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -1489,9 +1622,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[2] @@ -1502,12 +1640,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu1.l2cache.prefetcher response_latency=12 @@ -1525,6 +1668,7 @@ mem_side=system.toL2Bus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -1535,6 +1679,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -1551,8 +1699,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -1560,10 +1713,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 @@ -1608,9 +1766,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -1624,12 +1787,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -1648,8 +1816,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -1660,12 +1833,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -1684,21 +1862,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -1710,11 +1898,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1725,6 +1918,13 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl IDD0=0.075000 @@ -1759,6 +1959,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1770,7 +1971,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1813,10 +2018,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1897,14 +2107,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1913,13 +2128,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1929,6 +2149,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1999,10 +2220,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -2082,17 +2308,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -2118,12 +2349,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -2131,14 +2368,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -2224,14 +2466,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -2240,13 +2487,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -2255,13 +2507,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -2269,11 +2526,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2287,11 +2549,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2305,19 +2572,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -2363,14 +2636,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -2379,11 +2667,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -2393,21 +2686,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -2417,12 +2720,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -2431,10 +2739,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -2444,12 +2757,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -2459,26 +2777,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -2487,10 +2815,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -2498,10 +2831,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -2509,21 +2847,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2537,11 +2885,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -2552,11 +2905,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -2564,10 +2922,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -2583,10 +2946,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr index 3c2cf37c0..8786c1b6c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr @@ -3,6 +3,8 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout index 9920acce4..2aa1c9ae0 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout @@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 21:26:42 -gem5 started Mar 15 2016 21:34:31 -gem5 executing on phenom, pid 15970 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 15:03:52 +gem5 executing on e108600-lin, pid 24173 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47454492026000 because m5_exit instruction encountered +Exiting @ tick 47445489241000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index f2d1708bd..864e3d209 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.355903 # Number of seconds simulated -sim_ticks 47355903328000 # Number of ticks simulated -final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.445489 # Number of seconds simulated +sim_ticks 47445489241000 # Number of ticks simulated +final_tick 47445489241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170836 # Simulator instruction rate (inst/s) -host_op_rate 200933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9157476763 # Simulator tick rate (ticks/s) -host_mem_usage 772600 # Number of bytes of host memory used -host_seconds 5171.28 # Real time elapsed on the host -sim_insts 883443630 # Number of instructions simulated -sim_ops 1039082168 # Number of ops (including micro ops) simulated +host_inst_rate 208966 # Simulator instruction rate (inst/s) +host_op_rate 245756 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10881126125 # Simulator tick rate (ticks/s) +host_mem_usage 759660 # Number of bytes of host memory used +host_seconds 4360.35 # Real time elapsed on the host +sim_insts 911162440 # Number of instructions simulated +sim_ops 1071583187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 14160840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 16409728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 122112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 100992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3330560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9705936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 10452736 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 444224 # Number of bytes read from this memory -system.physmem.bytes_read::total 62549528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7567040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3330560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10897600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75633728 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 163648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 157696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 8375360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 16685256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 18550592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 100224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 74048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2844864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 7994832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 10895744 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory +system.physmem.bytes_read::total 66279064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 8375360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2844864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11220224 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78621824 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 75654312 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2056 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1934 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 118235 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 221276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 256402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1908 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1578 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 52040 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 151668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 163324 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6941 # Number of read requests responded to by this memory -system.physmem.num_reads::total 977362 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1181777 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78642408 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2464 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 130865 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 260720 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 289853 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1566 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1157 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 124932 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 170246 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1035636 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1228466 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1184351 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 159791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 299030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 346519 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2579 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 70330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 204957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 220727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1320839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 159791 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 70330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 230121 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1597134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1231040 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 176526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 351672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 390987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 168506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 229648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1396952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 176526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 236487 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1657098 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1597569 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1597134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 159791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 299465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 346519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 70330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 204957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 220727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2918408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 977362 # Number of read requests accepted -system.physmem.writeReqs 1184351 # Number of write requests accepted -system.physmem.readBursts 977362 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1184351 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62527296 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue -system.physmem.bytesWritten 75653504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62549528 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 75654312 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1657532 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1657098 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 176526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 352106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 390987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 168506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 229648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3054484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1035636 # Number of read requests accepted +system.physmem.writeReqs 1231040 # Number of write requests accepted +system.physmem.readBursts 1035636 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1231040 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 66252160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 28544 # Total number of bytes read from write queue +system.physmem.bytesWritten 78640192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 66279064 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78642408 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 446 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 54912 # Per bank write bursts -system.physmem.perBankRdBursts::1 56908 # Per bank write bursts -system.physmem.perBankRdBursts::2 51582 # Per bank write bursts -system.physmem.perBankRdBursts::3 63469 # Per bank write bursts -system.physmem.perBankRdBursts::4 61411 # Per bank write bursts -system.physmem.perBankRdBursts::5 61841 # Per bank write bursts -system.physmem.perBankRdBursts::6 57272 # Per bank write bursts -system.physmem.perBankRdBursts::7 62841 # Per bank write bursts -system.physmem.perBankRdBursts::8 51834 # Per bank write bursts -system.physmem.perBankRdBursts::9 112088 # Per bank write bursts -system.physmem.perBankRdBursts::10 55237 # Per bank write bursts -system.physmem.perBankRdBursts::11 58857 # Per bank write bursts -system.physmem.perBankRdBursts::12 56745 # Per bank write bursts -system.physmem.perBankRdBursts::13 58205 # Per bank write bursts -system.physmem.perBankRdBursts::14 53859 # Per bank write bursts -system.physmem.perBankRdBursts::15 59928 # Per bank write bursts -system.physmem.perBankWrBursts::0 69820 # Per bank write bursts -system.physmem.perBankWrBursts::1 73385 # Per bank write bursts -system.physmem.perBankWrBursts::2 70846 # Per bank write bursts -system.physmem.perBankWrBursts::3 76844 # Per bank write bursts -system.physmem.perBankWrBursts::4 76655 # Per bank write bursts -system.physmem.perBankWrBursts::5 78828 # Per bank write bursts -system.physmem.perBankWrBursts::6 72793 # Per bank write bursts -system.physmem.perBankWrBursts::7 76848 # Per bank write bursts -system.physmem.perBankWrBursts::8 69899 # Per bank write bursts -system.physmem.perBankWrBursts::9 74878 # Per bank write bursts -system.physmem.perBankWrBursts::10 69893 # Per bank write bursts -system.physmem.perBankWrBursts::11 73658 # Per bank write bursts -system.physmem.perBankWrBursts::12 73258 # Per bank write bursts -system.physmem.perBankWrBursts::13 76164 # Per bank write bursts -system.physmem.perBankWrBursts::14 72361 # Per bank write bursts -system.physmem.perBankWrBursts::15 75956 # Per bank write bursts +system.physmem.perBankRdBursts::0 59521 # Per bank write bursts +system.physmem.perBankRdBursts::1 66808 # Per bank write bursts +system.physmem.perBankRdBursts::2 62154 # Per bank write bursts +system.physmem.perBankRdBursts::3 70128 # Per bank write bursts +system.physmem.perBankRdBursts::4 60732 # Per bank write bursts +system.physmem.perBankRdBursts::5 72109 # Per bank write bursts +system.physmem.perBankRdBursts::6 58717 # Per bank write bursts +system.physmem.perBankRdBursts::7 62140 # Per bank write bursts +system.physmem.perBankRdBursts::8 50595 # Per bank write bursts +system.physmem.perBankRdBursts::9 107916 # Per bank write bursts +system.physmem.perBankRdBursts::10 54809 # Per bank write bursts +system.physmem.perBankRdBursts::11 63010 # Per bank write bursts +system.physmem.perBankRdBursts::12 57730 # Per bank write bursts +system.physmem.perBankRdBursts::13 64314 # Per bank write bursts +system.physmem.perBankRdBursts::14 61474 # Per bank write bursts +system.physmem.perBankRdBursts::15 63033 # Per bank write bursts +system.physmem.perBankWrBursts::0 75175 # Per bank write bursts +system.physmem.perBankWrBursts::1 80913 # Per bank write bursts +system.physmem.perBankWrBursts::2 75568 # Per bank write bursts +system.physmem.perBankWrBursts::3 82272 # Per bank write bursts +system.physmem.perBankWrBursts::4 75546 # Per bank write bursts +system.physmem.perBankWrBursts::5 83102 # Per bank write bursts +system.physmem.perBankWrBursts::6 75765 # Per bank write bursts +system.physmem.perBankWrBursts::7 76740 # Per bank write bursts +system.physmem.perBankWrBursts::8 69114 # Per bank write bursts +system.physmem.perBankWrBursts::9 73138 # Per bank write bursts +system.physmem.perBankWrBursts::10 71733 # Per bank write bursts +system.physmem.perBankWrBursts::11 77960 # Per bank write bursts +system.physmem.perBankWrBursts::12 74616 # Per bank write bursts +system.physmem.perBankWrBursts::13 78881 # Per bank write bursts +system.physmem.perBankWrBursts::14 78631 # Per bank write bursts +system.physmem.perBankWrBursts::15 79599 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 28 # Number of times write queue was full causing retry -system.physmem.totGap 47355901307500 # Total gap between requests +system.physmem.numWrRetry 48 # Number of times write queue was full causing retry +system.physmem.totGap 47445487151500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 977332 # Read request sizes (log2) +system.physmem.readPktSize::6 1035606 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1181777 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 653624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28719 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 26608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 24389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 21172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 19081 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 791 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1228466 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 692790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45775 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 30940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 28399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 26620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 20889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1663 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -189,226 +189,224 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 50320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 57992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 63163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 65860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 68534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 70437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 72935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 73131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 75636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 78760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 75174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 74381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 78953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 69890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 64098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 102 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 973522 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.938602 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 96.538228 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 191.263762 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 662821 68.08% 68.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 188353 19.35% 87.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 43865 4.51% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 19742 2.03% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14303 1.47% 95.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9443 0.97% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6391 0.66% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5216 0.54% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23388 2.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 973522 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 57494 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.992747 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 164.605284 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 57491 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 27376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 51705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 65779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 68512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 70877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 72860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 75714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 75511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 79365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 82384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 78677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 77306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 82372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 73265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 67472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 64363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 144 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1012110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 143.157878 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 97.072288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 192.644368 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 686114 67.79% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 195882 19.35% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 47037 4.65% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20980 2.07% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15295 1.51% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9865 0.97% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6724 0.66% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5499 0.54% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24714 2.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1012110 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60277 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.173764 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.670576 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60274 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 57494 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 57494 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.560163 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.793170 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.728131 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49230 85.63% 85.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2347 4.08% 89.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 805 1.40% 91.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 601 1.05% 92.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 998 1.74% 93.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 486 0.85% 94.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 329 0.57% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 263 0.46% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 216 0.38% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 180 0.31% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 129 0.22% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 154 0.27% 96.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 478 0.83% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 131 0.23% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 143 0.25% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 111 0.19% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 107 0.19% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 71 0.12% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 85 0.15% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 71 0.12% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 101 0.18% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 73 0.13% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 62 0.11% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 52 0.09% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 38 0.07% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 47 0.08% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 26 0.05% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 37 0.06% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 49 0.09% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 22 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 8 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 12 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60277 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60277 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.385105 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.691366 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.394945 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 52026 86.31% 86.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2335 3.87% 90.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 778 1.29% 91.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 614 1.02% 92.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 994 1.65% 94.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 490 0.81% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 334 0.55% 95.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 282 0.47% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 206 0.34% 96.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 170 0.28% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 135 0.22% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 158 0.26% 97.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 477 0.79% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 137 0.23% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 123 0.20% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 110 0.18% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 87 0.14% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 84 0.14% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 91 0.15% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 102 0.17% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 72 0.12% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 71 0.12% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 64 0.11% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 59 0.10% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 43 0.07% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 45 0.07% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 41 0.07% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 40 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 47 0.08% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 20 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 11 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 57494 # Writes before turning the bus around for reads -system.physmem.totQLat 32578317305 # Total ticks spent queuing -system.physmem.totMemAccLat 50896861055 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4884945000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33345.63 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::156-159 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 8 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60277 # Writes before turning the bus around for reads +system.physmem.totQLat 35377622933 # Total ticks spent queuing +system.physmem.totMemAccLat 54787435433 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5175950000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34175.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52095.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52925.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.66 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing -system.physmem.readRowHits 734277 # Number of row buffer hits during reads -system.physmem.writeRowHits 451275 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.18 # Row buffer hit rate for writes -system.physmem.avgGap 21906655.19 # Average gap between requests -system.physmem.pageHitRate 54.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3752269920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2047369500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3667786200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3862203120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1180767055500 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27377781027000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31664935054200 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.658673 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45545161867023 # Time in different power states -system.physmem_0.memoryStateTime::REF 1581317660000 # Time in different power states +system.physmem.avgWrQLen 27.61 # Average write queue length when enqueuing +system.physmem.readRowHits 780044 # Number of row buffer hits during reads +system.physmem.writeRowHits 471783 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.35 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.39 # Row buffer hit rate for writes +system.physmem.avgGap 20931746.38 # Average gap between requests +system.physmem.pageHitRate 55.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3937837680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2148621750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3995955600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4050479520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3098908325760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1191842451045 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27421814259750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31726697931105 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.697958 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45618359398995 # Time in different power states +system.physmem_0.memoryStateTime::REF 1584308960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 229423166977 # Time in different power states +system.physmem_0.memoryStateTime::ACT 242820245005 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3607556400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1968408750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3952673400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3797714160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1177905490200 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27380291180250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31664580366120 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.651183 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45549316476567 # Time in different power states -system.physmem_1.memoryStateTime::REF 1581317660000 # Time in different power states +system.physmem_1.actEnergy 3713615640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2026278375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4078440600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3911723280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3098908325760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1186342158240 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27426639078000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31725619619895 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.675231 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45626361005854 # Time in different power states +system.physmem_1.memoryStateTime::REF 1584308960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 225268560933 # Time in different power states +system.physmem_1.memoryStateTime::ACT 234814164146 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 13 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 13 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 13 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 145452632 # Number of BP lookups -system.cpu0.branchPred.condPredicted 102233764 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6537956 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 107843095 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75495824 # Number of BTB hits +system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 160314756 # Number of BP lookups +system.cpu0.branchPred.condPredicted 112651620 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7238532 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 119384108 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 83018284 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 70.005246 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17327542 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1162135 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 3835403 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2658726 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1176677 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 420775 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 69.538807 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 19042266 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1248322 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4272460 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2939923 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1332537 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 468796 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -438,63 +436,63 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 298304 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 298304 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10716 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85635 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 298304 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 298304 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 298304 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 96351 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22754.257870 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21300.315388 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14215.969550 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 95122 98.72% 98.72% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1073 1.11% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 26 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 56 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 56 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 329365 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 329365 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11619 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95372 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 329365 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 329365 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 329365 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 106991 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23090.091690 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21491.120734 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15706.739319 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 105441 98.55% 98.55% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1327 1.24% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 42 0.04% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 76 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 69 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 96351 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 734209704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 734209704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 734209704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 85635 88.88% 88.88% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10716 11.12% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 96351 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 298304 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 106991 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 734573704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 734573704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 734573704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 95372 89.14% 89.14% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11619 10.86% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 106991 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 329365 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 298304 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96351 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 329365 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106991 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96351 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 394655 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106991 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 436356 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 93899745 # DTB read hits -system.cpu0.dtb.read_misses 250404 # DTB read misses -system.cpu0.dtb.write_hits 82108561 # DTB write hits -system.cpu0.dtb.write_misses 47900 # DTB write misses +system.cpu0.dtb.read_hits 103710651 # DTB read hits +system.cpu0.dtb.read_misses 276993 # DTB read misses +system.cpu0.dtb.write_hits 90811723 # DTB write hits +system.cpu0.dtb.write_misses 52372 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 39092 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2185 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 10307 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 42132 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2205 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 11314 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10956 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 94150149 # DTB read accesses -system.cpu0.dtb.write_accesses 82156461 # DTB write accesses +system.cpu0.dtb.perms_faults 11590 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 103987644 # DTB read accesses +system.cpu0.dtb.write_accesses 90864095 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 176008306 # DTB hits -system.cpu0.dtb.misses 298304 # DTB misses -system.cpu0.dtb.accesses 176306610 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 194522374 # DTB hits +system.cpu0.dtb.misses 329365 # DTB misses +system.cpu0.dtb.accesses 194851739 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -524,904 +522,912 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 65048 # Table walker walks requested -system.cpu0.itb.walker.walksLong 65048 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 515 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52970 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 65048 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 65048 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 65048 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 53485 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25497.494625 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23453.450778 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17328.133028 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 49469 92.49% 92.49% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 2789 5.21% 97.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 9 0.02% 97.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 1088 2.03% 99.76% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 53485 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 733487204 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 733487204 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 733487204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 52970 99.04% 99.04% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 515 0.96% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 53485 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 72209 # Table walker walks requested +system.cpu0.itb.walker.walksLong 72209 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 611 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59557 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 72209 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 72209 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 72209 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 60168 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25971.338585 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23756.230706 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17963.019846 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 55134 91.63% 91.63% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3439 5.72% 97.35% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 6 0.01% 97.36% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 1442 2.40% 99.76% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 23 0.04% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 52 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 23 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 12 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 60168 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 733851204 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 733851204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 733851204 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 59557 98.98% 98.98% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 611 1.02% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 60168 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65048 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65048 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 72209 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 72209 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53485 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53485 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 118533 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 259203584 # ITB inst hits -system.cpu0.itb.inst_misses 65048 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60168 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60168 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 132377 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 285203366 # ITB inst hits +system.cpu0.itb.inst_misses 72209 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28269 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 30424 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 171713 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 190431 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 259268632 # ITB inst accesses -system.cpu0.itb.hits 259203584 # DTB hits -system.cpu0.itb.misses 65048 # DTB misses -system.cpu0.itb.accesses 259268632 # DTB accesses -system.cpu0.numPwrStateTransitions 26040 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13020 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3597852748.702535 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 96451622625.318069 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3172 24.36% 24.36% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 9818 75.41% 99.77% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 13 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7033291450000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13020 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 511860539893 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46844042788107 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 1023758481 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 285275575 # ITB inst accesses +system.cpu0.itb.hits 285203366 # DTB hits +system.cpu0.itb.misses 72209 # DTB misses +system.cpu0.itb.accesses 285275575 # DTB accesses +system.cpu0.numPwrStateTransitions 26302 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13151 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3564690271.200593 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 65409151988.663887 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3759 28.58% 28.58% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 9361 71.18% 99.76% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.77% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 4 0.03% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.82% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 2 0.02% 99.84% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 1988779311380 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13151 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 566247484441 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46879241756559 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 1132534446 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 483101155 # Number of instructions committed -system.cpu0.committedOps 567019823 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 47457065 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4178 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93688785177 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.119139 # CPI: cycles per instruction -system.cpu0.ipc 0.471890 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 393333975 69.37% 69.37% # Class of committed instruction -system.cpu0.op_class_0::IntMult 1298911 0.23% 69.60% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 62117 0.01% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 39633 0.01% 69.62% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction -system.cpu0.op_class_0::MemRead 90520623 15.96% 85.58% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 81764563 14.42% 100.00% # Class of committed instruction +system.cpu0.committedInsts 532076805 # Number of instructions committed +system.cpu0.committedOps 624758290 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 52154793 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4664 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93759282538 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.128517 # CPI: cycles per instruction +system.cpu0.ipc 0.469811 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 432780145 69.27% 69.27% # Class of committed instruction +system.cpu0.op_class_0::IntMult 1412970 0.23% 69.50% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 69899 0.01% 69.51% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 79522 0.01% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::MemRead 99981749 16.00% 85.52% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 90434005 14.48% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 567019823 # Class of committed instruction +system.cpu0.op_class_0::total 624758290 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13020 # number of quiesce instructions executed -system.cpu0.tickCycles 768761843 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 254996638 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6026209 # number of replacements -system.cpu0.dcache.tags.tagsinuse 478.505782 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 166971566 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6026721 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.705209 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 5039130000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.505782 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934582 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.934582 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 13151 # number of quiesce instructions executed +system.cpu0.tickCycles 847175236 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 285359210 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6574289 # number of replacements +system.cpu0.dcache.tags.tagsinuse 508.066535 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 184992173 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6574801 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.136543 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 5039429000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.066535 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992317 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.992317 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 355154483 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 355154483 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 85976696 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 85976696 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 76051356 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 76051356 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300861 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 300861 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 281214 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 281214 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1915398 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1915398 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1894723 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1894723 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 162309266 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 162309266 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 162610127 # number of overall hits -system.cpu0.dcache.overall_hits::total 162610127 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3729679 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3729679 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2481919 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2481919 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 681303 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 681303 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 827220 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 827220 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 176003 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 176003 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195484 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 7038818 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 7038818 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 7720121 # number of overall misses -system.cpu0.dcache.overall_misses::total 7720121 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57503024000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 57503024000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 50806938500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 50806938500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 27591387500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 27591387500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2577956500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2577956500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4885048500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4885048500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3405000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3405000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 135901350000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 135901350000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 135901350000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 135901350000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 89706375 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 89706375 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 78533275 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 78533275 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 982164 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 982164 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1108434 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1108434 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2091401 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2091401 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2090207 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2090207 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 169348084 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 169348084 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 170330248 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 170330248 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041577 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.041577 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031603 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.031603 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.693675 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.693675 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.746296 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.746296 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084156 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084156 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.093524 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.093524 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041564 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.041564 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045324 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.045324 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15417.687152 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15417.687152 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20470.828621 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20470.828621 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33354.352530 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33354.352530 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.230445 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.230445 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24989.505535 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24989.505535 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 392594755 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 392594755 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 95401287 # 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number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 197397 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 7416545 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 7416545 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 8150274 # number of overall misses +system.cpu0.dcache.overall_misses::total 8150274 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 59779296000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 59779296000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 54754909500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 54754909500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 28457275000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 28457275000 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2995014000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2995014000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4953933500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4953933500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3818500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3818500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 142991480500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 142991480500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 142991480500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 142991480500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 99241504 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 99241504 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 87005772 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 87005772 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1055694 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1055694 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1138868 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1138868 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2259846 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2259846 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2258522 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2258522 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 187386144 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 187386144 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 188441838 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 188441838 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038696 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.038696 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031243 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.031243 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.695021 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.695021 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.753399 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.753399 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088350 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088350 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.087401 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.087401 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.039579 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.039579 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.043251 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.043251 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15566.645322 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15566.645322 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20143.026392 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20143.026392 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33166.136766 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33166.136766 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15000.721233 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15000.721233 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25096.295790 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25096.295790 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19307.410704 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19307.410704 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17603.525903 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17603.525903 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19280.066460 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19280.066460 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17544.377097 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17544.377097 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6026220 # number of writebacks -system.cpu0.dcache.writebacks::total 6026220 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 447326 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 447326 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1020420 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1020420 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 73 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 73 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44988 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44988 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1467819 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1467819 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1467819 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1467819 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3282353 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3282353 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1461499 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1461499 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 679841 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 679841 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 827147 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 827147 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 131015 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 131015 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195417 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 195417 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5570999 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5570999 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6250840 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6250840 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31702 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62927 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45702695000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45702695000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29281044500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29281044500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14665959000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14665959000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 26759895500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26759895500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1703041500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1703041500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4687173500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4687173500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3267500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3267500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 101743635000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 101743635000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116409594000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 116409594000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6136923000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6136923000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6136923000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6136923000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036590 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036590 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018610 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018610 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.692187 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.692187 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746230 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746230 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062645 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062645 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093492 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093492 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032897 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032897 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036698 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.036698 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13923.759876 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13923.759876 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20034.939812 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20034.939812 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21572.630953 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21572.630953 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32352.043228 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32352.043228 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12998.828378 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12998.828378 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23985.495121 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23985.495121 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 6574291 # number of writebacks +system.cpu0.dcache.writebacks::total 6574291 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 237792 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 237792 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1117306 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1117306 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 90 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 90 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 48445 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 48445 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 60 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 60 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1355188 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1355188 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1355188 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1355188 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3602425 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3602425 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1601000 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1601000 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 732137 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 732137 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 857932 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 857932 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 151213 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 151213 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197337 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 197337 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 6061357 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 6061357 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6793494 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6793494 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29793 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29793 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29400 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29400 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59193 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59193 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50925119500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50925119500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 31536308500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 31536308500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16544300500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16544300500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 27594364000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 27594364000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1964885000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1964885000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4754516500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4754516500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3441500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3441500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110055792000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 110055792000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 126600092500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 126600092500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5675765000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5675765000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5675765000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5675765000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036300 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036300 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018401 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018401 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.693513 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.693513 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.753320 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.753320 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.066913 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.066913 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.087374 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.087374 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032347 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032347 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036051 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.036051 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14136.344129 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14136.344129 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19697.881636 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19697.881636 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22597.274144 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22597.274144 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32163.812517 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32163.812517 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12994.153942 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12994.153942 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24093.385934 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24093.385934 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18263.086208 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18263.086208 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18623.032104 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18623.032104 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193581.572141 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193581.572141 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97524.480748 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97524.480748 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 9817579 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.932451 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 249208397 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9818091 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 25.382572 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 22021065000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932451 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18156.955942 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18156.955942 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18635.490441 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18635.490441 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190506.662639 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190506.662639 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95885.746625 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95885.746625 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 10998491 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.932591 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 274007938 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 10999003 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.912070 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 22037323000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932591 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 527871096 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 527871096 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 249208397 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 249208397 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 249208397 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 249208397 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 249208397 # number of overall hits -system.cpu0.icache.overall_hits::total 249208397 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9818101 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9818101 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9818101 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9818101 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9818101 # number of overall misses -system.cpu0.icache.overall_misses::total 9818101 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 99002118000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 99002118000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 99002118000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 99002118000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 99002118000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 99002118000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 259026498 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 259026498 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 259026498 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 259026498 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 259026498 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 259026498 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037904 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.037904 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037904 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.037904 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037904 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.037904 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10083.632059 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10083.632059 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10083.632059 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10083.632059 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 581012885 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 581012885 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 274007938 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 274007938 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 274007938 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 274007938 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 274007938 # 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number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 105929935500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4836784500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 4836784500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038592 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.038592 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038592 # 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average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92481.539197 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8833822 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8835143 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 1166 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1073071 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2829183 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16163.343057 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 24764914 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2845343 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 8.703666 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5659477500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15257.249232 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.561913 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 60.708141 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 787.823770 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.931229 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003513 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003705 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.048085 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.986532 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1356 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14748 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 1192777 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 3147716 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16192.217188 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 27546589 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 3163437 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 8.707804 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5661168000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15379.701531 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 70.199902 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 67.449935 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 674.865820 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.938702 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004285 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004117 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.041191 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.988295 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1251 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 80 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14390 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 7 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 123 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 574 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 643 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1176 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2616 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5298 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5548 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082764 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900146 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 533961635 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 533961635 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 561309 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167224 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 728533 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3942058 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3942058 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 11898812 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 11898812 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 611 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 933174 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 933174 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9093916 # 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average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28921.697098 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33385.840298 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33385.840298 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30196.275404 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34883.677504 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185576.446281 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122640.778086 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93491.577542 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89406.453405 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 32574371 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16625689 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2229520 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2229086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 913111 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14927613 # Transaction distribution +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177578 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33942.280254 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48247.921077 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20579.127566 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20579.127566 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16567.541334 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16567.541334 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 588999.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588999.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41547.435606 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41547.435606 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27916.187063 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30232.016808 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30232.016808 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33273.354564 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33273.354564 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32548.114608 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30864.262300 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32548.114608 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35770.124238 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182497.298023 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 120053.189675 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91854.476036 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 88395.921717 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 36072564 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 18399437 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3515 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2427957 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2427386 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 571 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 1003133 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 16585926 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31225 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31225 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5591471 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 11901739 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2979875 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1058098 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 473129 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352230 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 525861 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1247048 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1223348 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9818101 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5127973 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 875849 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 825149 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29558377 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19506589 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370132 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1208276 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 50643374 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1260030528 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 732739948 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1405536 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4588864 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1998764876 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7447074 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 24526103 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.104449 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.305900 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::WriteReq 29400 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 29400 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 6083435 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 13283967 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 3350152 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1133444 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 490495 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 347636 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 543136 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1366077 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1342549 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10999003 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5499511 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 903440 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 855584 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 33101096 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21166131 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 412052 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1345098 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 56024377 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1411186752 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 800229141 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1569912 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5118984 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 2218104789 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7999072 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 122429440 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 26916994 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.103450 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.304616 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 21964812 89.56% 89.56% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2560857 10.44% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 434 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 24132997 89.66% 89.66% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2783426 10.34% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 571 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 24526103 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 32454354981 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 26916994 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 35963769502 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 208052919 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 196401052 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14809077024 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 16580139110 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8648892723 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9441182874 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 194486906 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 215851922 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 634782270 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 705346257 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 123875539 # Number of BP lookups -system.cpu1.branchPred.condPredicted 88073767 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5721607 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 93465185 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 65276742 # Number of BTB hits +system.cpu1.branchPred.lookups 118915951 # Number of BP lookups +system.cpu1.branchPred.condPredicted 85033049 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5367569 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 89750040 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 63411692 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 69.840703 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 14217829 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 926540 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3290763 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2135700 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1155063 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 419705 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 70.653664 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 13468810 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 887929 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3084567 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 1998882 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1085685 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 396796 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1451,63 +1457,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 255224 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 255224 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8861 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76574 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 255224 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 255224 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 255224 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 85435 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22815.538128 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21300.261475 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14551.493747 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 84387 98.77% 98.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 897 1.05% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 42 0.05% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 51 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 31 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 85435 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -788977056 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -788977056 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -788977056 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 76574 89.63% 89.63% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8861 10.37% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 85435 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 255224 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 246313 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 246313 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8582 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75463 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 246313 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 246313 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 246313 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 84045 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22346.070557 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21064.042846 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 12361.258067 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 79296 94.35% 94.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 4004 4.76% 99.11% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 175 0.21% 99.32% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 458 0.54% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 22 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 12 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 27 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 13 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 13 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 84045 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -766256056 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -766256056 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -766256056 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 75463 89.79% 89.79% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8582 10.21% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 84045 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 246313 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 255224 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85435 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 246313 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84045 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85435 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 340659 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84045 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 330358 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 78594683 # DTB read hits -system.cpu1.dtb.read_misses 208094 # DTB read misses -system.cpu1.dtb.write_hits 69544419 # DTB write hits -system.cpu1.dtb.write_misses 47130 # DTB write misses +system.cpu1.dtb.read_hits 74020776 # DTB read hits +system.cpu1.dtb.read_misses 200548 # DTB read misses +system.cpu1.dtb.write_hits 65603987 # DTB write hits +system.cpu1.dtb.write_misses 45765 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 35782 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 839 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 34845 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 889 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6796 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11450 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 78802777 # DTB read accesses -system.cpu1.dtb.write_accesses 69591549 # DTB write accesses +system.cpu1.dtb.perms_faults 11277 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 74221324 # DTB read accesses +system.cpu1.dtb.write_accesses 65649752 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 148139102 # DTB hits -system.cpu1.dtb.misses 255224 # DTB misses -system.cpu1.dtb.accesses 148394326 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 139624763 # DTB hits +system.cpu1.dtb.misses 246313 # DTB misses +system.cpu1.dtb.accesses 139871076 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1537,911 +1549,899 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 62177 # Table walker walks requested -system.cpu1.itb.walker.walksLong 62177 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54596 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 62177 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 62177 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 62177 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 55226 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25650.988665 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23787.605646 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 16059.408850 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 49961 90.47% 90.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 4236 7.67% 98.14% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 9 0.02% 98.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 906 1.64% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 28 0.05% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 55226 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -789630556 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -789630556 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -789630556 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54596 98.86% 98.86% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 630 1.14% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55226 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 60327 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60327 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52409 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60327 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60327 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60327 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 52954 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24879.980738 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23402.458623 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 13318.614145 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 48523 91.63% 91.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 3764 7.11% 98.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 13 0.02% 98.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 577 1.09% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 8 0.02% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 20 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 52954 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -766782556 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -766782556 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -766782556 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 52409 98.97% 98.97% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 545 1.03% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 52954 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62177 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62177 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60327 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60327 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55226 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55226 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 117403 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 219337574 # ITB inst hits -system.cpu1.itb.inst_misses 62177 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 52954 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 52954 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 113281 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 210682225 # ITB inst hits +system.cpu1.itb.inst_misses 60327 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25319 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 24520 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 167002 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 163777 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 219399751 # ITB inst accesses -system.cpu1.itb.hits 219337574 # DTB hits -system.cpu1.itb.misses 62177 # DTB misses -system.cpu1.itb.accesses 219399751 # DTB accesses -system.cpu1.numPwrStateTransitions 10996 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 5498 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 8537078490.682248 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 139542991677.263855 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3923 71.35% 71.35% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1550 28.19% 99.55% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.56% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.09% 99.65% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 14 0.25% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7470355729396 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 5498 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 419045786229 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46936857541771 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 838096745 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 210742552 # ITB inst accesses +system.cpu1.itb.hits 210682225 # DTB hits +system.cpu1.itb.misses 60327 # DTB misses +system.cpu1.itb.accesses 210742552 # DTB accesses +system.cpu1.numPwrStateTransitions 10392 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 5196 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 9053828227.255966 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 188730440437.234528 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3531 67.96% 67.96% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1645 31.66% 99.62% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 9 0.17% 99.79% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.81% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.87% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 7 0.13% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 7351146453012 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 5196 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 401797772178 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47043691468822 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 803603609 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 400342475 # Number of instructions committed -system.cpu1.committedOps 472062345 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 44700411 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5381 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93874475142 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.093449 # CPI: cycles per instruction -system.cpu1.ipc 0.477681 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 326101667 69.08% 69.08% # Class of committed instruction -system.cpu1.op_class_0::IntMult 925373 0.20% 69.28% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 54057 0.01% 69.29% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 72329 0.02% 69.30% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::MemRead 75664367 16.03% 85.33% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 69244510 14.67% 100.00% # Class of committed instruction +system.cpu1.committedInsts 379085635 # Number of instructions committed +system.cpu1.committedOps 446824897 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 44295367 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4823 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 94088042190 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.119847 # CPI: cycles per instruction +system.cpu1.ipc 0.471732 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 309274392 69.22% 69.22% # Class of committed instruction +system.cpu1.op_class_0::IntMult 866353 0.19% 69.41% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 49212 0.01% 69.42% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 34424 0.01% 69.43% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu1.op_class_0::MemRead 71272038 15.95% 85.38% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 65328435 14.62% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 472062345 # Class of committed instruction +system.cpu1.op_class_0::total 446824897 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5498 # number of quiesce instructions executed -system.cpu1.tickCycles 657140254 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 180956491 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 4810857 # number of replacements -system.cpu1.dcache.tags.tagsinuse 458.623346 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 140763490 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4811366 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.256450 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8377530544000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.623346 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895749 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.895749 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 298669128 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 298669128 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 72030058 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 72030058 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 64877267 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 64877267 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 197389 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 197389 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 40268 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 40268 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1587155 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1587155 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1543611 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1543611 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 136947593 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 136947593 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 137144982 # number of overall hits -system.cpu1.dcache.overall_hits::total 137144982 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3077185 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3077185 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2162319 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2162319 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 609138 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 609138 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 415243 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 415243 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150447 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 150447 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 192941 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 192941 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5654747 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5654747 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6263885 # number of overall misses -system.cpu1.dcache.overall_misses::total 6263885 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46366444000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 46366444000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40662976500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 40662976500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10070349000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 10070349000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2311960000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2311960000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4775235000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4775235000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2623000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2623000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 97099769500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 97099769500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 97099769500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 97099769500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 75107243 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 75107243 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 67039586 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 67039586 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 806527 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 806527 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 455511 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 455511 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1737602 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1737602 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1736552 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1736552 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 142602340 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 142602340 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 143408867 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 143408867 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040971 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.040971 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032254 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.032254 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.755261 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.755261 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.911598 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.911598 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086583 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086583 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111106 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.111106 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039654 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.039654 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043679 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043679 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15067.811653 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15067.811653 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18805.262545 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18805.262545 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24251.700811 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24251.700811 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15367.272196 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15367.272196 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24749.716234 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24749.716234 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5196 # number of quiesce instructions executed +system.cpu1.tickCycles 627540865 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 176062744 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 4660684 # number of replacements +system.cpu1.dcache.tags.tagsinuse 434.489996 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 132775101 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4661196 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.485200 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8377585211000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 434.489996 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.848613 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.848613 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 281793929 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 281793929 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 67965873 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 67965873 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 61015488 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 61015488 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 190971 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 190971 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 44349 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 44349 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1561438 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1561438 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1518539 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1518539 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 129025710 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 129025710 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 129216681 # number of overall hits +system.cpu1.dcache.overall_hits::total 129216681 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2729495 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2729495 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2149690 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2149690 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 616052 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 616052 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 399927 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 399927 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 143085 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 143085 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 184951 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 184951 # 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number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2101168500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4571201000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4571201000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4144500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4144500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 89566973500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 89566973500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 89566973500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 89566973500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 70695368 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 70695368 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 63165178 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 63165178 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 807023 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 807023 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 444276 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 444276 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1704523 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1704523 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1703490 # 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average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14551.126490 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18651.073178 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18651.073178 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24393.754360 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24393.754360 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14684.757312 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14684.757312 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24715.740926 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24715.740926 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # 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number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 4810864 # number of writebacks -system.cpu1.dcache.writebacks::total 4810864 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 357052 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 357052 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 892415 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 892415 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40665 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40665 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1249541 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1249541 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1249541 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1249541 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2720133 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2720133 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1269904 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1269904 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 608760 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 608760 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 415169 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 415169 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 109782 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 109782 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192883 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 192883 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4405206 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4405206 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5013966 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5013966 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6941 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14221 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36972803500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36972803500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23335803000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23335803000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13834846000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13834846000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9650155000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9650155000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1512082000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1512082000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4580259000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4580259000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2341500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69958761500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 69958761500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83793607500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 83793607500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 837242500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 837242500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 837242500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 837242500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036217 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036217 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018943 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018943 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754792 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.754792 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.911436 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.911436 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063180 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063180 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111072 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111072 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030892 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030892 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034963 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034963 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13592.277841 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13592.277841 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18376.037086 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18376.037086 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22726.273080 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22726.273080 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23243.919946 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23243.919946 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13773.496566 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13773.496566 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23746.307347 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23746.307347 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 4660691 # number of writebacks +system.cpu1.dcache.writebacks::total 4660691 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 132278 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 132278 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 894898 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 894898 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 69 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 69 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 37558 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 37558 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 59 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1027245 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1027245 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1027245 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1027245 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2597217 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2597217 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1254792 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1254792 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 615702 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 615702 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 399858 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 399858 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 105527 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 105527 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 184892 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 184892 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4251867 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4251867 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4867569 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4867569 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8793 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8793 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9091 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9091 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17884 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17884 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34245614000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34245614000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22880344500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22880344500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13431113500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13431113500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9350661500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9350661500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1405417000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1405417000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4384302500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4384302500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3898500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3898500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 66476620000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 66476620000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 79907733500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 79907733500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1305175500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1305175500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1305175500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1305175500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036738 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036738 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019865 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019865 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762930 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.762930 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.900022 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.900022 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061910 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108537 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108537 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031658 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031658 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036026 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.036026 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13185.503560 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13185.503560 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18234.372310 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18234.372310 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21814.308708 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21814.308708 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23384.955409 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23384.955409 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13318.079733 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.079733 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23712.775566 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23712.775566 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15880.928497 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15880.928497 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16712.041426 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16712.041426 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120622.748883 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120622.748883 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 58873.672738 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 58873.672738 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 8744967 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.224680 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 210419103 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8745479 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 24.060329 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8367967785000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.224680 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990673 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990673 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15634.689420 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15634.689420 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16416.353523 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16416.353523 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148433.469806 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 148433.469806 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 72980.065981 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 72980.065981 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 8014386 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.062567 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 202497896 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8014898 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.265187 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8368004575000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.062567 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990357 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990357 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 447074643 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 447074643 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 210419103 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 210419103 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 210419103 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 210419103 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 210419103 # number of overall hits -system.cpu1.icache.overall_hits::total 210419103 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8745479 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8745479 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8745479 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8745479 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8745479 # number of overall misses -system.cpu1.icache.overall_misses::total 8745479 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 88268174500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 88268174500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 88268174500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 88268174500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 88268174500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 88268174500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 219164582 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 219164582 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 219164582 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 219164582 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 219164582 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 219164582 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039904 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.039904 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039904 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.039904 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039904 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.039904 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10093.006284 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10093.006284 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10093.006284 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10093.006284 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 429040515 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 429040515 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 202497896 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 202497896 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 202497896 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 202497896 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 202497896 # number of overall hits +system.cpu1.icache.overall_hits::total 202497896 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8014908 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8014908 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8014908 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 8014908 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 8014908 # number of overall misses +system.cpu1.icache.overall_misses::total 8014908 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 81330977500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 81330977500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 81330977500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 81330977500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 81330977500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 81330977500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 210512804 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 210512804 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 210512804 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 210512804 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 210512804 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 210512804 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038073 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.038073 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038073 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.038073 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038073 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.038073 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10147.462391 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10147.462391 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10147.462391 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10147.462391 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10147.462391 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10147.462391 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 8744967 # number of writebacks -system.cpu1.icache.writebacks::total 8744967 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8745479 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8745479 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8745479 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8745479 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8745479 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 8745479 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 83895435000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 83895435000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 83895435000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 83895435000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 83895435000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 83895435000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8450000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8450000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8450000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8450000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039904 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.039904 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.039904 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9593.006284 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90860.215054 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90860.215054 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6641051 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6641093 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 36 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.writebacks::writebacks 8014386 # number of writebacks +system.cpu1.icache.writebacks::total 8014386 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8014908 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 8014908 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 8014908 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 8014908 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 8014908 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 8014908 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 77323524000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 77323524000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 77323524000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 77323524000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 77323524000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 77323524000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8766500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8766500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8766500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8766500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038073 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.038073 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.038073 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9647.462454 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9647.462454 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9647.462454 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92278.947368 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92278.947368 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6532358 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6532555 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 172 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 796339 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2218428 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13419.558556 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 21617433 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2233865 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 9.677144 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10005238958500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12516.094704 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 63.377354 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 44.102544 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 795.983954 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.763922 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003868 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002692 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048583 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.819065 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1192 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14164 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 771 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 263 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 54 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6319 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2682 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004944 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864502 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 457671450 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 457671450 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 494400 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160613 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 655013 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3026488 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3026488 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 10527430 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 10527430 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 434 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 434 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 789107 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 789107 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8072877 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 8072877 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2507088 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2507088 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 171056 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 171056 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 494400 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 160613 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 8072877 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3296195 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 12024085 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 494400 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 160613 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 8072877 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3296195 # number of overall hits -system.cpu1.l2cache.overall_hits::total 12024085 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11721 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8689 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 20410 # number of ReadReq misses -system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses -system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses -system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses -system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 220631 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 220631 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 192879 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 192879 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 261966 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 261966 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 672602 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 672602 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 931427 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 931427 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 242391 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 242391 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11721 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8689 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 672602 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1193393 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1886405 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11721 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8689 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 672602 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1193393 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1886405 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 429270500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 326619000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 755889500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1918862500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 1918862500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1442678000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1442678000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2273499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2273499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10385042497 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 10385042497 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22017991000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 22017991000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 30592821494 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 30592821494 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 352126000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 352126000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 429270500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 326619000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22017991000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 40977863991 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 63751744491 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 429270500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 326619000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22017991000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 40977863991 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 63751744491 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 506121 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 169302 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 675423 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3026489 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3026489 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 10527431 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 10527431 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 221065 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 221065 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 192879 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 192879 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1051073 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1051073 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8745479 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 8745479 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3438515 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3438515 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 413447 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 413447 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 506121 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 169302 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 55 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1161 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5545 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7510 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 574 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.909119 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 428778233 # 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number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 227423500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 551503000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 26884842389 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 26884842389 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4561523494 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4561523494 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2993192497 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2993192497 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3356499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3356499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7853418999 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7853418999 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16948153000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16948153000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 22723854990 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 22723854990 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6164226500 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6164226500 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 324079500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 227423500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16948153000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 30577273989 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 48076929989 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 324079500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 227423500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16948153000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 30577273989 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 26884842389 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 74961772378 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8006500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1234720500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1242727000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8006500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1234720500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1242727000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029644 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998037 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998037 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998117 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998117 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.244771 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.244771 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.076908 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.270718 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270718 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.586269 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.586269 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135232 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.239653 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.239653 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080980 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.272149 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.272149 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.584803 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.584803 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264406 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139801 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264406 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186208 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 31037.609644 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35918.637723 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20808.816504 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20808.816504 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16224.436051 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16224.436051 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500874.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500874.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32120.644676 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32120.644676 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26735.574243 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26815.018004 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26815.018004 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26186.131086 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26186.131086 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27558.035864 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29846.821834 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112606.396773 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112213.107762 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 54961.043527 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 55142.308230 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 27911552 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14263179 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 2035614 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2035313 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 755700 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13030335 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 7280 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7280 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4134671 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 10529340 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2783515 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 903944 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 426493 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348519 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 477830 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1080105 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1057121 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8745479 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4495606 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 466229 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 413447 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26236111 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15633953 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 355051 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1069038 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 43294153 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1119394496 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 601463021 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1354416 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4048968 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1726260901 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6529606 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 21121122 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.110367 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.313393 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.192823 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28725.610709 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38948.299055 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20841.626813 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20841.626813 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16189.657767 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16189.657767 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 372944.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 372944.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31574.707002 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31574.707002 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26112.486981 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25163.535220 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25163.535220 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26480.228622 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26480.228622 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26548.026857 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26415.677887 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26548.026857 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29861.857270 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140420.846128 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139820.769577 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69040.511071 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 69121.030091 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 26150144 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 13381244 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1981 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1969364 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1969026 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 338 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 732517 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 12156991 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 9091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 9091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4007359 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 9735300 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2694691 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 886167 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 430328 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337223 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 468486 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1067899 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1044213 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8014908 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4433895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 458319 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 398059 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 24044391 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15175224 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 343569 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1027712 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 40590896 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1025880832 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 583383788 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1306120 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3875096 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1614445836 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6456023 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 75189768 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 20132697 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.112928 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.316558 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 18790338 88.96% 88.96% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2330483 11.03% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 301 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 17859482 88.71% 88.71% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2272877 11.29% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 338 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 21121122 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 27750114484 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 20132697 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 25974578977 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 177306545 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 179053447 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13121677843 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 12025219550 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7163335235 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 6952751265 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 185802393 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 180351405 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 563017795 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 543399850 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40337 # Transaction distribution -system.iobus.trans_dist::ReadResp 40337 # Transaction distribution -system.iobus.trans_dist::WriteReq 136616 # Transaction distribution -system.iobus.trans_dist::WriteResp 136616 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47664 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40387 # Transaction distribution +system.iobus.trans_dist::ReadResp 40387 # Transaction distribution +system.iobus.trans_dist::WriteReq 136979 # Transaction distribution +system.iobus.trans_dist::WriteResp 136979 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2452,15 +2452,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122598 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231228 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231228 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231702 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231702 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353906 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47684 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47828 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2471,105 +2471,105 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155705 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338928 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338928 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155965 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496719 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43180502 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513211 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42458502 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 311001 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25595502 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26063002 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36402501 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34444001 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569469754 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 570734934 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92958000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147924000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148142000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115611 # number of replacements -system.iocache.tags.tagsinuse 11.284790 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115832 # number of replacements +system.iocache.tags.tagsinuse 11.305903 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115627 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115848 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9167417766000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.418888 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.865902 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463681 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.241619 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705299 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9127528857000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.833923 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.471980 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239620 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466999 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706619 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040883 # Number of tag accesses -system.iocache.tags.data_accesses 1040883 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1043016 # Number of tag accesses +system.iocache.tags.data_accesses 1043016 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8867 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8904 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115614 # number of demand (read+write) misses -system.iocache.demand_misses::total 115654 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115851 # number of demand (read+write) misses +system.iocache.demand_misses::total 115891 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115614 # number of overall misses -system.iocache.overall_misses::total 115654 # number of overall misses +system.iocache.overall_misses::realview.ide 115851 # number of overall misses +system.iocache.overall_misses::total 115891 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1668794518 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1673992518 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1647274031 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1652472031 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12857701236 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12857701236 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12886794903 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12886794903 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14526495754 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14532062754 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14534068934 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14539635934 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14526495754 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14532062754 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14534068934 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14539635934 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8867 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115614 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115654 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115851 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115891 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115614 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115654 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115851 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115891 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2584,52 +2584,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 187800.418411 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 187604.227054 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 185775.801398 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 185587.604560 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120471.677873 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120471.677873 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120455.347557 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120455.347557 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125651.190223 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125454.842289 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125459.577827 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125651.190223 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33480 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 125454.842289 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125459.577827 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32243 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3531 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3515 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.481733 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.172973 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106695 # number of writebacks -system.iocache.writebacks::total 106695 # number of writebacks +system.iocache.writebacks::writebacks 106950 # number of writebacks +system.iocache.writebacks::total 106950 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8867 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8904 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115614 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115654 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115851 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115891 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115614 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115654 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 115851 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115891 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1224494518 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1227842518 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1203924031 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1207272031 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7512769435 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7512769435 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7528956843 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7528956843 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8737263953 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8740830953 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8732880874 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8736447874 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8737263953 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8740830953 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8732880874 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8736447874 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2644,662 +2644,659 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137800.418411 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 137604.227054 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135775.801398 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 135587.604560 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.738204 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.738204 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70374.605950 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70374.605950 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75380.280481 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75385.041755 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1371243 # number of replacements -system.l2c.tags.tagsinuse 63411.869664 # Cycle average of tags in use -system.l2c.tags.total_refs 6460055 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1430877 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.514752 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7876910500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 21329.379338 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 243.549056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 346.213430 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5332.164924 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9972.711960 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14780.287325 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 85.709675 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 92.474711 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3611.694384 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3808.494767 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3809.190093 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.325461 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003716 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.005283 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081362 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.152172 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.225529 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001308 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001411 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.055110 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.058113 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058124 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.967588 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9222 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50157 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 98 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 408 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 8708 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1961 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5894 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 42105 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.140717 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.765335 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 79235647 # Number of tag accesses -system.l2c.tags.data_accesses 79235647 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2747527 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2747527 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 170119 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 132427 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 302546 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 41747 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 38038 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 79785 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 52086 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59057 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 111143 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6348 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3788 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 658119 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 620329 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 316694 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6918 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5196 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 620556 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 563518 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 312616 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3114082 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 130339 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 134354 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 264693 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6348 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3788 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 658119 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 672415 # 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Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 197 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49413 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 162 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 3598 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 6999 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 179 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2209 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 15374 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 31482 # 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average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72651.227338 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 76684.798346 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79699.783619 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81643.583511 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98118.647459 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20918.654291 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20760.842224 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20891.805966 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167570.579301 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94623.649229 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102107.944449 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84420.399908 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46177.192630 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 71756.492357 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3789204 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2296931 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.262097 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.318773 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.286593 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.211304 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.225618 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.217588 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.595463 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.451567 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.535333 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.206892 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.125236 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.206266 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.775396 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.429860 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.684337 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.263538 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.170778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.225148 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.263538 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.170778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.225148 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21504.428630 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21588.308809 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21544.753533 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.736546 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24607.311801 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24602.095240 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78922.059614 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72763.810098 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 76751.364510 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79262.094163 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83037.216747 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98969.705542 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20911.097724 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20861.825980 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20902.941631 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79150.090720 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79246.180478 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 95938.382922 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79150.090720 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79246.180478 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 95938.382922 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164491.491592 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122437.265840 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102255.861386 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82791.799858 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 60191.589531 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 71855.534201 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3914348 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2362357 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2871 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 91033 # Transaction distribution -system.membus.trans_dist::ReadResp 892432 # Transaction distribution -system.membus.trans_dist::WriteReq 38505 # Transaction distribution -system.membus.trans_dist::WriteResp 38505 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1181777 # Transaction distribution -system.membus.trans_dist::CleanEvict 252869 # Transaction distribution -system.membus.trans_dist::UpgradeReq 437143 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 308404 # Transaction distribution -system.membus.trans_dist::UpgradeResp 22 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 90979 # Transaction distribution +system.membus.trans_dist::ReadResp 948459 # Transaction distribution +system.membus.trans_dist::WriteReq 38491 # Transaction distribution +system.membus.trans_dist::WriteResp 38491 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1228466 # Transaction distribution +system.membus.trans_dist::CleanEvict 265252 # Transaction distribution +system.membus.trans_dist::UpgradeReq 443986 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 298688 # Transaction distribution +system.membus.trans_dist::UpgradeResp 23 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 143945 # Transaction distribution -system.membus.trans_dist::ReadExResp 126263 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 801399 # Transaction distribution -system.membus.trans_dist::InvalidateReq 663637 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122598 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4585882 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4735006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4973212 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155705 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 130931136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 131141113 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7272704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 138413817 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 608511 # Total snoops (count) -system.membus.snoop_fanout::samples 2484071 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012278 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.110125 # Request fanout histogram +system.membus.trans_dist::ReadExReq 145286 # Transaction distribution +system.membus.trans_dist::ReadExResp 128554 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 857480 # Transaction distribution +system.membus.trans_dist::InvalidateReq 675140 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122950 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4768940 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4917924 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238548 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238548 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5156472 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155965 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 137639872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 137849185 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7281600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 145130785 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 603530 # Total snoops (count) +system.membus.snoopTraffic 179328 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2550056 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011955 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.108685 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2453571 98.77% 98.77% # Request fanout histogram -system.membus.snoop_fanout::1 30500 1.23% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2519569 98.80% 98.80% # Request fanout histogram +system.membus.snoop_fanout::1 30487 1.20% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2484071 # Request fanout histogram -system.membus.reqLayer0.occupancy 105594995 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2550056 # Request fanout histogram +system.membus.reqLayer0.occupancy 103375494 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22316500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21768496 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8304045809 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8632891321 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5231778477 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5537724663 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45499333 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45395946 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3342,78 +3339,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 12326432 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6670511 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2086069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 130580 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 118652 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11928 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 91035 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4782322 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38505 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38505 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3822609 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2941580 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 730122 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 388189 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1118311 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 299700 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 299700 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4691812 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 853093 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 825528 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10130133 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7962376 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18092509 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250257116 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194861853 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 445118969 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2830390 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8463866 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.368667 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.485356 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 12809826 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6934559 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2124865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 137043 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 124917 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 12126 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 90981 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4987806 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38491 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38491 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3972958 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 3104635 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 749262 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 382090 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1131352 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 138 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 306540 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 306540 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4897318 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 863164 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 835591 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11082342 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7735233 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18817575 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 276628165 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 188875292 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 465503457 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2889580 # Total snoops (count) +system.toL2Bus.snoopTraffic 125478224 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 8764836 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.360858 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.483121 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5355444 63.27% 63.27% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3096494 36.58% 99.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11928 0.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5614105 64.05% 64.05% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3138605 35.81% 99.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 12126 0.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8463866 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9400124055 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8764836 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9763497454 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2566916 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2559907 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4651836575 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5082599079 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3960751843 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3859782501 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal index 049b0949c..74f9afa7a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000028] Console: colour dummy device 80x25
-[ 0.000031] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000032] pid_max: default: 32768 minimum: 301
-[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000046] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000199] hw perfevents: no hardware support available
-[ 0.060051] CPU1: Booted secondary processor
-[ 1.080085] CPU2: failed to come online
-[ 2.100161] CPU3: failed to come online
-[ 2.100164] Brought up 2 CPUs
-[ 2.100165] SMP: Total of 2 processors activated.
-[ 2.100234] devtmpfs: initialized
-[ 2.100742] atomic64_test: passed
-[ 2.100794] regulator-dummy: no parameters
-[ 2.101157] NET: Registered protocol family 16
-[ 2.101296] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 2.101304] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 2.102113] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 2.102117] Serial: AMBA PL011 UART driver
-[ 2.102318] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 2.102358] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 2.102933] console [ttyAMA0] enabled
-[ 2.103072] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 2.103132] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 2.103192] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 2.103250] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 2.140336] 3V3: 3300 mV
-[ 2.140383] vgaarb: loaded
-[ 2.140429] SCSI subsystem initialized
-[ 2.140466] libata version 3.00 loaded.
-[ 2.140524] usbcore: registered new interface driver usbfs
-[ 2.140543] usbcore: registered new interface driver hub
-[ 2.140567] usbcore: registered new device driver usb
-[ 2.140593] pps_core: LinuxPPS API ver. 1 registered
-[ 2.140602] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 2.140621] PTP clock support registered
-[ 2.140762] Switched to clocksource arch_sys_counter
-[ 2.141783] NET: Registered protocol family 2
-[ 2.141863] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 2.141880] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 2.141897] TCP: Hash tables configured (established 2048 bind 2048)
-[ 2.141925] TCP: reno registered
-[ 2.141932] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.141945] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.141981] NET: Registered protocol family 1
-[ 2.142034] RPC: Registered named UNIX socket transport module.
-[ 2.142044] RPC: Registered udp transport module.
-[ 2.142052] RPC: Registered tcp transport module.
-[ 2.142061] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 2.142073] PCI: CLS 0 bytes, default 64
-[ 2.142235] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 2.142334] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 2.144468] fuse init (API version 7.23)
-[ 2.144588] msgmni has been set to 469
-[ 2.144697] io scheduler noop registered
-[ 2.144749] io scheduler cfq registered (default)
-[ 2.145214] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 2.145228] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 2.145239] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.145252] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 2.145262] pci_bus 0000:00: scanning bus
-[ 2.145274] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 2.145288] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 2.145302] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.145340] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 2.145352] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 2.145363] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 2.145373] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.145384] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 2.145395] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 2.145406] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.145441] pci_bus 0000:00: fixups for bus
-[ 2.145450] pci_bus 0000:00: bus scan returning with max=00
-[ 2.145462] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 2.145483] pci 0000:00:00.0: fixup irq: got 33
-[ 2.145492] pci 0000:00:00.0: assigning IRQ 33
-[ 2.145502] pci 0000:00:01.0: fixup irq: got 34
-[ 2.145511] pci 0000:00:01.0: assigning IRQ 34
-[ 2.145524] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 2.145538] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.145551] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 2.145564] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 2.145576] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.145587] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 2.145599] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 2.145610] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 2.146274] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.146553] ata_piix 0000:00:01.0: version 2.13
-[ 2.146565] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.146593] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.146864] scsi0 : ata_piix
-[ 2.146948] scsi1 : ata_piix
-[ 2.146979] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.146991] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.147095] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 2.147108] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 2.147123] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.147134] e1000 0000:00:00.0: enabling bus mastering
-[ 2.290805] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.290816] ata1.00: 2096640 sectors, multi 0: LBA
-[ 2.290846] ata1.00: configured for UDMA/33
-[ 2.290909] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.291028] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 2.291029] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.291056] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.291067] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.291092] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.291248] sda: sda1
-[ 2.291370] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 2.411068] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 2.411082] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 2.411104] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 2.411115] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 2.411135] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 2.411147] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 2.411217] usbcore: registered new interface driver usb-storage
-[ 2.411286] mousedev: PS/2 mouse device common for all mice
-[ 2.411453] usbcore: registered new interface driver usbhid
-[ 2.411463] usbhid: USB HID core driver
-[ 2.411495] TCP: cubic registered
-[ 2.411502] NET: Registered protocol family 17
- -[ 2.411975] devtmpfs: mounted
-[ 2.412025] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000023] Console: colour dummy device 80x25
+[ 0.000025] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000027] pid_max: default: 32768 minimum: 301
+[ 0.000038] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000039] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000155] hw perfevents: no hardware support available
+[ 0.060041] CPU1: Booted secondary processor
+[ 1.080079] CPU2: failed to come online
+[ 2.100151] CPU3: failed to come online
+[ 2.100154] Brought up 2 CPUs
+[ 2.100155] SMP: Total of 2 processors activated.
+[ 2.100226] devtmpfs: initialized
+[ 2.100722] atomic64_test: passed
+[ 2.100767] regulator-dummy: no parameters
+[ 2.101110] NET: Registered protocol family 16
+[ 2.101240] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.101248] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.101651] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.101655] Serial: AMBA PL011 UART driver
+[ 2.101841] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.101878] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.102452] console [ttyAMA0] enabled
+[ 2.102605] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.102668] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.102733] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.102790] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.140329] 3V3: 3300 mV
+[ 2.140389] vgaarb: loaded
+[ 2.140455] SCSI subsystem initialized
+[ 2.140504] libata version 3.00 loaded.
+[ 2.140588] usbcore: registered new interface driver usbfs
+[ 2.140613] usbcore: registered new interface driver hub
+[ 2.140641] usbcore: registered new device driver usb
+[ 2.140687] pps_core: LinuxPPS API ver. 1 registered
+[ 2.140698] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.140722] PTP clock support registered
+[ 2.140900] Switched to clocksource arch_sys_counter
+[ 2.142431] NET: Registered protocol family 2
+[ 2.142518] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.142535] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.142552] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.142574] TCP: reno registered
+[ 2.142581] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.142593] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.142627] NET: Registered protocol family 1
+[ 2.142670] RPC: Registered named UNIX socket transport module.
+[ 2.142681] RPC: Registered udp transport module.
+[ 2.142689] RPC: Registered tcp transport module.
+[ 2.142698] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.142710] PCI: CLS 0 bytes, default 64
+[ 2.142942] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.143052] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.145204] fuse init (API version 7.23)
+[ 2.145320] msgmni has been set to 469
+[ 2.145427] io scheduler noop registered
+[ 2.145479] io scheduler cfq registered (default)
+[ 2.145859] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.145872] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.145883] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.145896] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.145906] pci_bus 0000:00: scanning bus
+[ 2.145917] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.145930] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.145945] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.145979] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.145991] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.146002] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.146013] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.146024] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.146035] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.146046] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.146081] pci_bus 0000:00: fixups for bus
+[ 2.146089] pci_bus 0000:00: bus scan returning with max=00
+[ 2.146101] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.146121] pci 0000:00:00.0: fixup irq: got 33
+[ 2.146129] pci 0000:00:00.0: assigning IRQ 33
+[ 2.146140] pci 0000:00:01.0: fixup irq: got 34
+[ 2.146149] pci 0000:00:01.0: assigning IRQ 34
+[ 2.146160] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.146173] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.146186] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.146199] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.146211] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.146222] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.146234] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.146245] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.146902] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.147174] ata_piix 0000:00:01.0: version 2.13
+[ 2.147184] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.147208] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.147469] scsi0 : ata_piix
+[ 2.147563] scsi1 : ata_piix
+[ 2.147592] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.147605] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.147706] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.147719] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.147733] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.147745] e1000 0000:00:00.0: enabling bus mastering
+[ 2.290935] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.290946] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.290974] ata1.00: configured for UDMA/33
+[ 2.291028] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.291135] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.291142] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.291184] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.291194] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.291214] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.291351] sda: sda1
+[ 2.291468] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.411201] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.411215] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.411238] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.411249] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.411270] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.411282] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.411355] usbcore: registered new interface driver usb-storage
+[ 2.411408] mousedev: PS/2 mouse device common for all mice
+[ 2.411558] usbcore: registered new interface driver usbhid
+[ 2.411568] usbhid: USB HID core driver
+[ 2.411600] TCP: cubic registered
+[ 2.411608] NET: Registered protocol family 17
+ +[ 2.411985] devtmpfs: mounted
+[ 2.412018] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.460540] udevd[609]: starting version 182
+[ 2.450547] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.553667] random: dd urandom read with 18 bits of entropy available
+[ 2.513635] random: dd urandom read with 17 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.680995] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.641130] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
|