diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:50:15 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:50:15 -0500 |
| commit | 29cd50e14e0709c28200bcbdbc08c1093ba300d7 (patch) | |
| tree | ce3db836e947d154cbd0e4d7e1959f7617a7cc0c /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor | |
| parent | 7a0bf814b6eb2db57f37977a0cca6c442f957d68 (diff) | |
| download | gem5-29cd50e14e0709c28200bcbdbc08c1093ba300d7.tar.xz | |
arm, tests: Add 64-bit ARM regression tests
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor')
4 files changed, 2997 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini new file mode 100644 index 000000000..f34f6e208 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini @@ -0,0 +1,1647 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain +atags_addr=134217728 +boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=timing +mem_ranges=2147483648:2415919103 +memories=system.realview.vram system.physmem system.realview.nvmem +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5.latest/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload= +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=true +width=8 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr new file mode 100644 index 000000000..744db2c76 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr @@ -0,0 +1,11 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout new file mode 100644 index 000000000..9642d869b --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout @@ -0,0 +1,16 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:29:11 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 + 0: system.cpu.isa: ISA system set to: 0x5c61b00 0x5c61b00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80080000 +info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 51727209160500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt new file mode 100644 index 000000000..19a412b67 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -0,0 +1,1323 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 51.727209 # Number of seconds simulated +sim_ticks 51727209160500 # Number of ticks simulated +final_tick 51727209160500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 180889 # Simulator instruction rate (inst/s) +host_op_rate 212546 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9849373518 # Simulator tick rate (ticks/s) +host_mem_usage 656984 # Number of bytes of host memory used +host_seconds 5251.83 # Real time elapsed on the host +sim_insts 949996153 # Number of instructions simulated +sim_ops 1116252474 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::realview.ide 424768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 725248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 1005696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 91312008 # Number of bytes read from this memory +system.physmem.bytes_read::total 93467720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 9575168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 9575168 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 57345920 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.inst 101255460 # Number of bytes written to this memory +system.physmem.bytes_written::total 165427876 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 6637 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 11332 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 15714 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1426763 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1460446 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 896030 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.inst 1584368 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2587062 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 8212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 14021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 19442 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1765261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1806935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 185109 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 185109 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1108622 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 131971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.inst 1957489 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3198082 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1108622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 140183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 14021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 19442 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3722750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5005018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1460446 # Number of read requests accepted +system.physmem.writeReqs 2587062 # Number of write requests accepted +system.physmem.readBursts 1460446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2587062 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 93277376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 191168 # Total number of bytes read from write queue +system.physmem.bytesWritten 160708736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 93467720 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 165427876 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2987 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 75973 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 39020 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 90929 # Per bank write bursts +system.physmem.perBankRdBursts::1 88965 # Per bank write bursts +system.physmem.perBankRdBursts::2 84770 # Per bank write bursts +system.physmem.perBankRdBursts::3 81753 # Per bank write bursts +system.physmem.perBankRdBursts::4 95872 # Per bank write bursts +system.physmem.perBankRdBursts::5 100020 # Per bank write bursts +system.physmem.perBankRdBursts::6 87194 # Per bank write bursts +system.physmem.perBankRdBursts::7 85191 # Per bank write bursts +system.physmem.perBankRdBursts::8 88300 # Per bank write bursts +system.physmem.perBankRdBursts::9 142631 # Per bank write bursts +system.physmem.perBankRdBursts::10 90249 # Per bank write bursts +system.physmem.perBankRdBursts::11 90988 # Per bank write bursts +system.physmem.perBankRdBursts::12 86795 # Per bank write bursts +system.physmem.perBankRdBursts::13 81108 # Per bank write bursts +system.physmem.perBankRdBursts::14 81197 # Per bank write bursts +system.physmem.perBankRdBursts::15 81497 # Per bank write bursts +system.physmem.perBankWrBursts::0 153488 # Per bank write bursts +system.physmem.perBankWrBursts::1 130402 # Per bank write bursts +system.physmem.perBankWrBursts::2 156905 # Per bank write bursts +system.physmem.perBankWrBursts::3 130743 # Per bank write bursts +system.physmem.perBankWrBursts::4 190154 # Per bank write bursts +system.physmem.perBankWrBursts::5 164896 # Per bank write bursts +system.physmem.perBankWrBursts::6 144797 # Per bank write bursts +system.physmem.perBankWrBursts::7 175639 # Per bank write bursts +system.physmem.perBankWrBursts::8 162274 # Per bank write bursts +system.physmem.perBankWrBursts::9 194391 # Per bank write bursts +system.physmem.perBankWrBursts::10 215398 # Per bank write bursts +system.physmem.perBankWrBursts::11 156932 # Per bank write bursts +system.physmem.perBankWrBursts::12 147011 # Per bank write bursts +system.physmem.perBankWrBursts::13 124629 # Per bank write bursts +system.physmem.perBankWrBursts::14 132966 # Per bank write bursts +system.physmem.perBankWrBursts::15 130449 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 51727207457500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 13 # Read request sizes (log2) +system.physmem.readPktSize::4 2 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1460431 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 1 # Write request sizes (log2) +system.physmem.writePktSize::3 2572 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 2584489 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1416507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 34555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 627 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 780499 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 325.414218 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.439490 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 353.699104 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 309228 39.62% 39.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 174811 22.40% 62.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 65731 8.42% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 36715 4.70% 75.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 26784 3.43% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 18838 2.41% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14160 1.81% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 15996 2.05% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 118236 15.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 780499 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 115810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.584803 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 189.442624 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 115806 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-30719 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::49152-51199 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 115810 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 115810 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.682704 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.755419 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.614982 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 58231 50.28% 50.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 24453 21.11% 71.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 18350 15.84% 87.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 9042 7.81% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1932 1.67% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 855 0.74% 97.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 730 0.63% 98.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 458 0.40% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 355 0.31% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 216 0.19% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 209 0.18% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 191 0.16% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 504 0.44% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 74 0.06% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 53 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 51 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 44 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 5 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 14 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 5 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 8 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 115810 # Writes before turning the bus around for reads +system.physmem.totQLat 16665773749 # Total ticks spent queuing +system.physmem.totMemAccLat 43993129999 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7287295000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11434.81 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30184.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.20 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing +system.physmem.readRowHits 1137142 # Number of row buffer hits during reads +system.physmem.writeRowHits 2050889 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.67 # Row buffer hit rate for writes +system.physmem.avgGap 12780013.64 # Average gap between requests +system.physmem.pageHitRate 80.33 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49431156944750 # Time in different power states +system.physmem.memoryStateTime::REF 1727285040000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 568765880250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 2969235360 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 2931337080 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1620118500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1599439875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 5574566400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 5793535800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 8080715520 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 8191044000 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3378569538240 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3378569538240 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1383201002250 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1386870926445 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29822988580500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29819769348750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34603003756770 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34603725170190 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.951744 # Core power per rank (mW) +system.physmem.averagePower::1 668.965690 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 740 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 16 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 594629 # Transaction distribution +system.membus.trans_dist::ReadResp 594629 # Transaction distribution +system.membus.trans_dist::WriteReq 33870 # Transaction distribution +system.membus.trans_dist::WriteResp 33870 # Transaction distribution +system.membus.trans_dist::Writeback 896030 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 1688459 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 1688459 # Transaction distribution +system.membus.trans_dist::UpgradeReq 39025 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 39026 # Transaction distribution +system.membus.trans_dist::ReadExReq 901834 # Transaction distribution +system.membus.trans_dist::ReadExResp 901834 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7050430 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7180576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 228843 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 228843 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7409419 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 251644332 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 251815240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7251264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7251264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 259066504 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2247 # Total snoops (count) +system.membus.snoop_fanout::samples 4033943 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 4033943 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 4033943 # Request fanout histogram +system.membus.reqLayer0.occupancy 113743500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5505500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 25619760742 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 15669502469 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 186602993 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1669 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 40404 # Transaction distribution +system.iobus.trans_dist::ReadResp 40404 # Transaction distribution +system.iobus.trans_dist::WriteReq 136687 # Transaction distribution +system.iobus.trans_dist::WriteResp 136733 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 46 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354274 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492854 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 981194482 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179049007 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 259878452 # Number of BP lookups +system.cpu.branchPred.condPredicted 182434681 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12106293 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 193171007 # Number of BTB lookups +system.cpu.branchPred.BTBHits 136122005 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 70.467099 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31463060 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2055318 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 183357098 # DTB read hits +system.cpu.dtb.read_misses 476791 # DTB read misses +system.cpu.dtb.write_hits 162738381 # DTB write hits +system.cpu.dtb.write_misses 102414 # DTB write misses +system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 47228 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 80239 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 828 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14730 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 23395 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 183833889 # DTB read accesses +system.cpu.dtb.write_accesses 162840795 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 346095479 # DTB hits +system.cpu.dtb.misses 579205 # DTB misses +system.cpu.dtb.accesses 346674684 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 453041166 # ITB inst hits +system.cpu.itb.inst_misses 137089 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 47228 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 57684 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 391598 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 453178255 # ITB inst accesses +system.cpu.itb.hits 453041166 # DTB hits +system.cpu.itb.misses 137089 # DTB misses +system.cpu.itb.accesses 453178255 # DTB accesses +system.cpu.numCycles 2529291390 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 949996153 # Number of instructions committed +system.cpu.committedOps 1116252474 # Number of ops (including micro ops) committed +system.cpu.discardedOps 97459423 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7746 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100926289028 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.662423 # CPI: cycles per instruction +system.cpu.ipc 0.375598 # IPC: instructions per cycle +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 16606 # number of quiesce instructions executed +system.cpu.tickCycles 1758931949 # Number of cycles that the object actually ticked +system.cpu.idleCycles 770359441 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 24421267 # number of replacements +system.cpu.icache.tags.tagsinuse 511.933272 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 428216370 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24421779 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.534201 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20287456250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.933272 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 477059947 # Number of tag accesses +system.cpu.icache.tags.data_accesses 477059947 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 428216370 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 428216370 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 428216370 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 428216370 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 428216370 # number of overall hits +system.cpu.icache.overall_hits::total 428216370 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24421789 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24421789 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24421789 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24421789 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24421789 # number of overall misses +system.cpu.icache.overall_misses::total 24421789 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 323902842267 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 323902842267 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 323902842267 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 323902842267 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 323902842267 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 323902842267 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 452638159 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 452638159 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 452638159 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 452638159 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 452638159 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 452638159 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.053954 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.053954 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.053954 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.053954 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.053954 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.053954 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13262.863022 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13262.863022 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13262.863022 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13262.863022 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13262.863022 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13262.863022 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24421789 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 24421789 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 24421789 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 24421789 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 24421789 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 24421789 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275014410207 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 275014410207 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275014410207 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 275014410207 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275014410207 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 275014410207 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3812415750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3812415750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3812415750 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 3812415750 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053954 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053954 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053954 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.053954 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053954 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.053954 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11261.026381 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11261.026381 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11261.026381 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11261.026381 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11261.026381 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11261.026381 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 33751616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33743319 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33870 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33870 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7503603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1688467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1581795 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 49741 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 49742 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2372919 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2372919 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 48947837 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30709223 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 697396 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2259044 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 82613500 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1566322176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1215506888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2302360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7713224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2791844648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 568944 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 45280303 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.002552 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.050452 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 45164753 99.74% 99.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115550 0.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 45280303 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 31745616637 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 870000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 36745726780 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 15986739626 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 411079115 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 1295977131 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 1126830 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64583.745426 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 39448197 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1188930 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 33.179579 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 13946888021000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 34952.581213 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 365.608431 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 461.071203 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 28804.484579 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.533334 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005579 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007035 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.439522 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.985470 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 475 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 61625 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 455 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1805 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5403 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54172 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.007248 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.940323 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 361655243 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 361655243 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 952821 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 272081 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 31479251 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73103.103621 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78365.006177 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77181.366934 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73013.138455 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73103.103621 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 11332 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 15714 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1375107 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1402153 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 747069250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 1017596000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29199771041 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 30964436291 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 31915763266 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 31915763266 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 84641270374 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 747069250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 1017596000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 82876605124 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 84641270374 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007389750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8007389750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 5176574500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176574500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 13183964250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13183964250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011753 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.054601 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014793 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015050 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.772307 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.772307 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.380309 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.380309 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011753 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.054601 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040062 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.039412 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011753 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.054601 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040062 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039412 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65925.630957 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64757.286496 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61777.015049 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61964.812173 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst inf # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10015.186499 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.186499 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 10001 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60269.204596 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60365.217187 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 11147587 # 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number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 26501 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 292182960210 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 292182960210 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 292182960210 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 292182960210 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 176940842 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 176940842 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 156230510 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 156230510 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst 1581795 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1581795 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 4337484 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4337484 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 4335752 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4335752 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 333171352 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 333171352 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 333171352 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 333171352 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.045427 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.045427 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.027600 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027600 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.057000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.037068 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037068 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.037068 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037068 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16194.433569 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16194.433569 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 37572.915110 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37572.915110 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14477.437558 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14477.437558 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26501 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23658.769171 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23658.769171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23658.769171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23658.769171 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 1581795 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 7503603 # number of writebacks +system.cpu.dcache.writebacks::total 7503603 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 754441 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 754441 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1888429 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1888429 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 2642870 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2642870 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 2642870 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2642870 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7283456 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7283456 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2422384 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2422384 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 247233 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 247233 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9705840 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9705840 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9705840 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9705840 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 104220169248 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 104220169248 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 83386178898 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83386178898 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 50958353731 # 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number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5728567000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5728567000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 5584485000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5584485000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 11313052000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11313052000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.041163 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041163 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015505 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015505 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.056999 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056999 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.029132 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029132 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.029132 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029132 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14309.164392 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14309.164392 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 34423.187611 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34423.187611 # average WriteReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst inf # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12470.909013 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12470.909013 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24499 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 19329.223246 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19329.223246 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 19329.223246 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19329.223246 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.tags.replacements 115484 # number of replacements +system.iocache.tags.tagsinuse 10.452726 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 13140359698000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.516791 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.935936 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219799 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433496 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653295 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 1040243 # Number of tag accesses +system.iocache.tags.data_accesses 1040243 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses +system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses +system.iocache.WriteReq_misses::total 3 # number of WriteReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 46 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 46 # 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number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1936499108 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1942323108 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1936499108 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1942323108 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106710 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106710 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8838 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8878 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8838 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8878 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000431 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000431 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 219110.557592 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 218815.110761 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 219110.557592 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 218779.354359 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 219110.557592 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 218779.354359 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 53642 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.770856 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8838 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8878 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8838 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8878 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1476815114 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1480376114 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6530998375 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6530998375 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1476815114 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1480559114 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1476815114 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1480559114 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167098.338312 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 166802.942423 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 167098.338312 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 166767.190133 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 167098.338312 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 166767.190133 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- |