diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
| commit | c6cede244b431c167ac0213d89ad2bd7a0abbd96 (patch) | |
| tree | fb0e63d4172746d5b1a8edeb859f7ee68cfe13a6 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor | |
| parent | 83a5977481d55916b200740cf03748a20777bdf1 (diff) | |
| download | gem5-c6cede244b431c167ac0213d89ad2bd7a0abbd96.tar.xz | |
stats: Update stats to reflect changes to cache and crossbar
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt | 2063 |
1 files changed, 1037 insertions, 1026 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 46040b9b9..1a67ea010 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.667482 # Number of seconds simulated -sim_ticks 51667481628000 # Number of ticks simulated -final_tick 51667481628000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.667476 # Number of seconds simulated +sim_ticks 51667476471000 # Number of ticks simulated +final_tick 51667476471000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173876 # Simulator instruction rate (inst/s) -host_op_rate 204307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9745015544 # Simulator tick rate (ticks/s) -host_mem_usage 682548 # Number of bytes of host memory used -host_seconds 5301.94 # Real time elapsed on the host -sim_insts 921877826 # Number of instructions simulated -sim_ops 1083223459 # Number of ops (including micro ops) simulated +host_inst_rate 274767 # Simulator instruction rate (inst/s) +host_op_rate 322852 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15389929524 # Simulator tick rate (ticks/s) +host_mem_usage 683068 # Number of bytes of host memory used +host_seconds 3357.23 # Real time elapsed on the host +sim_insts 922453344 # Number of instructions simulated +sim_ops 1083887959 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 355328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 294720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10221184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 93611976 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 405568 # Number of bytes read from this memory -system.physmem.bytes_read::total 104888776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10221184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10221184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 87378688 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 349632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 295488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10205120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 93689288 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 408000 # Number of bytes read from this memory +system.physmem.bytes_read::total 104947528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10205120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10205120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 87402048 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 87399268 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 5552 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 159706 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1462700 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6337 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1638900 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1365292 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 87422628 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 5463 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 159455 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1463908 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6375 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1639818 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1365657 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1367865 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 6877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 197826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1811816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2030073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1691174 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1368230 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 6767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 197515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1813313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2031211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197515 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197515 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1691626 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1691572 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1691174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 6877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1812214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3721645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1638900 # Number of read requests accepted -system.physmem.writeReqs 1367865 # Number of write requests accepted -system.physmem.readBursts 1638900 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1367865 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 104832704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 56896 # Total number of bytes read from write queue -system.physmem.bytesWritten 87398080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 104888776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 87399268 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 889 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1692024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1691626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 6767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1813711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3723235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1639818 # Number of read requests accepted +system.physmem.writeReqs 1368230 # Number of write requests accepted +system.physmem.readBursts 1639818 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1368230 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 104895040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 53312 # Total number of bytes read from write queue +system.physmem.bytesWritten 87421376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 104947528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 87422628 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 833 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2255 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 381658 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 98450 # Per bank write bursts -system.physmem.perBankRdBursts::1 107251 # Per bank write bursts -system.physmem.perBankRdBursts::2 99188 # Per bank write bursts -system.physmem.perBankRdBursts::3 95203 # Per bank write bursts -system.physmem.perBankRdBursts::4 99955 # Per bank write bursts -system.physmem.perBankRdBursts::5 109194 # Per bank write bursts -system.physmem.perBankRdBursts::6 96838 # Per bank write bursts -system.physmem.perBankRdBursts::7 98371 # Per bank write bursts -system.physmem.perBankRdBursts::8 94736 # Per bank write bursts -system.physmem.perBankRdBursts::9 155242 # Per bank write bursts -system.physmem.perBankRdBursts::10 99865 # Per bank write bursts -system.physmem.perBankRdBursts::11 104170 # Per bank write bursts -system.physmem.perBankRdBursts::12 95009 # Per bank write bursts -system.physmem.perBankRdBursts::13 96057 # Per bank write bursts -system.physmem.perBankRdBursts::14 92133 # Per bank write bursts -system.physmem.perBankRdBursts::15 96349 # Per bank write bursts -system.physmem.perBankWrBursts::0 83734 # Per bank write bursts -system.physmem.perBankWrBursts::1 87693 # Per bank write bursts -system.physmem.perBankWrBursts::2 84639 # Per bank write bursts -system.physmem.perBankWrBursts::3 83186 # Per bank write bursts -system.physmem.perBankWrBursts::4 87134 # Per bank write bursts -system.physmem.perBankWrBursts::5 92701 # Per bank write bursts -system.physmem.perBankWrBursts::6 83787 # Per bank write bursts -system.physmem.perBankWrBursts::7 85921 # Per bank write bursts -system.physmem.perBankWrBursts::8 83051 # Per bank write bursts -system.physmem.perBankWrBursts::9 88932 # Per bank write bursts -system.physmem.perBankWrBursts::10 85543 # Per bank write bursts -system.physmem.perBankWrBursts::11 89009 # Per bank write bursts -system.physmem.perBankWrBursts::12 82580 # Per bank write bursts -system.physmem.perBankWrBursts::13 83353 # Per bank write bursts -system.physmem.perBankWrBursts::14 81127 # Per bank write bursts -system.physmem.perBankWrBursts::15 83205 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 99403 # Per bank write bursts +system.physmem.perBankRdBursts::1 105228 # Per bank write bursts +system.physmem.perBankRdBursts::2 100047 # Per bank write bursts +system.physmem.perBankRdBursts::3 95494 # Per bank write bursts +system.physmem.perBankRdBursts::4 102929 # Per bank write bursts +system.physmem.perBankRdBursts::5 111535 # Per bank write bursts +system.physmem.perBankRdBursts::6 97078 # Per bank write bursts +system.physmem.perBankRdBursts::7 98055 # Per bank write bursts +system.physmem.perBankRdBursts::8 92724 # Per bank write bursts +system.physmem.perBankRdBursts::9 154002 # Per bank write bursts +system.physmem.perBankRdBursts::10 99475 # Per bank write bursts +system.physmem.perBankRdBursts::11 105000 # Per bank write bursts +system.physmem.perBankRdBursts::12 94287 # Per bank write bursts +system.physmem.perBankRdBursts::13 95690 # Per bank write bursts +system.physmem.perBankRdBursts::14 90913 # Per bank write bursts +system.physmem.perBankRdBursts::15 97125 # Per bank write bursts +system.physmem.perBankWrBursts::0 83951 # Per bank write bursts +system.physmem.perBankWrBursts::1 87043 # Per bank write bursts +system.physmem.perBankWrBursts::2 85245 # Per bank write bursts +system.physmem.perBankWrBursts::3 83208 # Per bank write bursts +system.physmem.perBankWrBursts::4 88814 # Per bank write bursts +system.physmem.perBankWrBursts::5 93904 # Per bank write bursts +system.physmem.perBankWrBursts::6 83820 # Per bank write bursts +system.physmem.perBankWrBursts::7 85248 # Per bank write bursts +system.physmem.perBankWrBursts::8 81467 # Per bank write bursts +system.physmem.perBankWrBursts::9 88240 # Per bank write bursts +system.physmem.perBankWrBursts::10 85354 # Per bank write bursts +system.physmem.perBankWrBursts::11 89463 # Per bank write bursts +system.physmem.perBankWrBursts::12 82403 # Per bank write bursts +system.physmem.perBankWrBursts::13 83577 # Per bank write bursts +system.physmem.perBankWrBursts::14 80367 # Per bank write bursts +system.physmem.perBankWrBursts::15 83855 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 16 # Number of times write queue was full causing retry -system.physmem.totGap 51667479848500 # Total gap between requests +system.physmem.numWrRetry 37 # Number of times write queue was full causing retry +system.physmem.totGap 51667474307000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1638885 # Read request sizes (log2) +system.physmem.readPktSize::6 1639803 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1365292 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1312759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 318962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 673 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1365657 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1314237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 318417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,117 +159,124 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 65606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 80418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 82482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 82286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 83182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 83357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 85216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 84108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 84794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 89394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 84174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 82879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 91789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 82005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 83224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 79922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 647624 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.824083 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.411154 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.640423 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 254912 39.36% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 156143 24.11% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 60053 9.27% 72.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34984 5.40% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25631 3.96% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 18733 2.89% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14068 2.17% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 12825 1.98% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 70275 10.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 647624 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 79231 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.673638 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 283.409553 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 79228 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 14698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 18189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 67736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 80790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 82454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 81257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 81296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 82033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 83039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 82637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 83634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 86681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 83517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 83880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 94578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 83323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 84131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 81331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 109 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 646147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.635603 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 173.901229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.036577 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 253673 39.26% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 155474 24.06% 63.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 60360 9.34% 72.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 34960 5.41% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 25496 3.95% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 18768 2.90% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14047 2.17% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13088 2.03% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 70281 10.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 646147 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 79019 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.741467 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 283.796699 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 79016 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 79231 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 79231 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.235615 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.796201 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.303380 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 76926 97.09% 97.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 319 0.40% 97.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 70 0.09% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 321 0.41% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 45 0.06% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 342 0.43% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 202 0.25% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 22 0.03% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 52 0.07% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 126 0.16% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 31 0.04% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 49 0.06% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 483 0.61% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 14 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 128 0.16% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 11 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 79231 # Writes before turning the bus around for reads -system.physmem.totQLat 26417109815 # Total ticks spent queuing -system.physmem.totMemAccLat 57129816065 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8190055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16127.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 79019 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 79019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.286463 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.794878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.949851 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 76956 97.39% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 330 0.42% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 47 0.06% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 101 0.13% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 35 0.04% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 85 0.11% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 245 0.31% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 21 0.03% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 324 0.41% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 69 0.09% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 26 0.03% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 53 0.07% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 312 0.39% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 39 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 28 0.04% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 118 0.15% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 171 0.22% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 79019 # Writes before turning the bus around for reads +system.physmem.totQLat 26490910104 # Total ticks spent queuing +system.physmem.totMemAccLat 57221878854 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8194925000 # Total ticks spent in databus transfers +system.physmem.avgQLat 16163.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34877.55 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34913.00 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.03 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.69 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.03 # Average system read bandwidth in MiByte/s @@ -279,40 +286,40 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.24 # Average write queue length when enqueuing -system.physmem.readRowHits 1331553 # Number of row buffer hits during reads -system.physmem.writeRowHits 1024428 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.02 # Row buffer hit rate for writes -system.physmem.avgGap 17183743.94 # Average gap between requests -system.physmem.pageHitRate 78.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2488253040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1357677750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6274663200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4463391600 # Energy for write commands per rank (pJ) +system.physmem.avgWrQLen 25.57 # Average write queue length when enqueuing +system.physmem.readRowHits 1332864 # Number of row buffer hits during reads +system.physmem.writeRowHits 1025932 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes +system.physmem.avgGap 17176412.85 # Average gap between requests +system.physmem.pageHitRate 78.50 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2496243960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1362037875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6316198200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4479189840 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1321909933950 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29840915681250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34552077975270 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.739417 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49642099754241 # Time in different power states +system.physmem_0.actBackEnergy 1323055672425 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29839910639250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34552288356030 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.743489 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49640417958020 # Time in different power states system.physmem_0.memoryStateTime::REF 1725290580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 300090521259 # Time in different power states +system.physmem_0.memoryStateTime::ACT 301767793230 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2407784400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1313771250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6501775800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4385664000 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 2388627360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1303318500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6467877000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4372224480 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1318271769585 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29844107045250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34551656184765 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.731253 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49647373564820 # Time in different power states +system.physmem_1.actBackEnergy 1316624734350 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29845551821250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34551376977420 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.725849 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49649780004526 # Time in different power states system.physmem_1.memoryStateTime::REF 1725290580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 294812186430 # Time in different power states +system.physmem_1.memoryStateTime::ACT 292405760474 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -336,15 +343,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 252485837 # Number of BP lookups -system.cpu.branchPred.condPredicted 176433570 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11949823 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 185211535 # Number of BTB lookups -system.cpu.branchPred.BTBHits 131480802 # Number of BTB hits +system.cpu.branchPred.lookups 252598760 # Number of BP lookups +system.cpu.branchPred.condPredicted 176508431 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11957032 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 185598793 # Number of BTB lookups +system.cpu.branchPred.BTBHits 131565493 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.989532 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30949299 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2133828 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.887041 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30959293 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2131771 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -375,63 +382,63 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 560555 # Table walker walks requested -system.cpu.dtb.walker.walksLong 560555 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20820 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178520 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 560555 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 560555 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 560555 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 199340 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 27109.310725 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 22940.792106 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20958.396260 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 197062 98.86% 98.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 8 0.00% 98.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1944 0.98% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 53 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 116 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 50 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 75 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 560635 # Table walker walks requested +system.cpu.dtb.walker.walksLong 560635 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20884 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178593 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 560635 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 560635 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 560635 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 199477 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 26985.070961 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 22842.355807 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20873.513445 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 197251 98.88% 98.88% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1888 0.95% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 57 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 109 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 46 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 97 0.05% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 199340 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 199477 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 178521 89.56% 89.56% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 20820 10.44% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 199341 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560555 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 178594 89.53% 89.53% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 20884 10.47% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 199478 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560635 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560555 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199341 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560635 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199478 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199341 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 759896 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199478 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 760113 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 178230117 # DTB read hits -system.cpu.dtb.read_misses 462749 # DTB read misses -system.cpu.dtb.write_hits 157902959 # DTB write hits -system.cpu.dtb.write_misses 97806 # DTB write misses +system.cpu.dtb.read_hits 178339564 # DTB read hits +system.cpu.dtb.read_misses 462901 # DTB read misses +system.cpu.dtb.write_hits 158016400 # DTB write hits +system.cpu.dtb.write_misses 97734 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 78363 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1414 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14783 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 78401 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1394 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14946 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23068 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 178692866 # DTB read accesses -system.cpu.dtb.write_accesses 158000765 # DTB write accesses +system.cpu.dtb.perms_faults 23063 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 178802465 # DTB read accesses +system.cpu.dtb.write_accesses 158114134 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 336133076 # DTB hits -system.cpu.dtb.misses 560555 # DTB misses -system.cpu.dtb.accesses 336693631 # DTB accesses +system.cpu.dtb.hits 336355964 # DTB hits +system.cpu.dtb.misses 560635 # DTB misses +system.cpu.dtb.accesses 336916599 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -461,42 +468,47 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 134868 # Table walker walks requested -system.cpu.itb.walker.walksLong 134868 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1077 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 117569 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 134868 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 134868 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 134868 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 118646 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 30429.546719 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 26050.717125 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 23099.528150 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 116148 97.89% 97.89% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 8 0.01% 97.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 2266 1.91% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 70 0.06% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 116 0.10% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 118646 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 134932 # Table walker walks requested +system.cpu.itb.walker.walksLong 134932 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1079 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 117658 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 134932 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 134932 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 134932 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 118737 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 30245.892182 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 25862.614601 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 23195.505917 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-32767 58684 49.42% 49.42% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-65535 57510 48.43% 97.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-98303 2 0.00% 97.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-131071 7 0.01% 97.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-163839 1905 1.60% 99.47% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::163840-196607 424 0.36% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-229375 23 0.02% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::229376-262143 17 0.01% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-294911 94 0.08% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::294912-327679 21 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-360447 17 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-425983 17 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::425984-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 118737 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 117569 99.09% 99.09% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1077 0.91% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 118646 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 117658 99.09% 99.09% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1079 0.91% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 118737 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134868 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 134868 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134932 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 134932 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118646 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 118646 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 253514 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 438855637 # ITB inst hits -system.cpu.itb.inst_misses 134868 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118737 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 118737 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 253669 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 439091546 # ITB inst hits +system.cpu.itb.inst_misses 134932 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -505,140 +517,140 @@ system.cpu.itb.flush_tlb 11 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 56516 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 56478 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 359281 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 354973 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 438990505 # ITB inst accesses -system.cpu.itb.hits 438855637 # DTB hits -system.cpu.itb.misses 134868 # DTB misses -system.cpu.itb.accesses 438990505 # DTB accesses -system.cpu.numCycles 2563496972 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 439226478 # ITB inst accesses +system.cpu.itb.hits 439091546 # DTB hits +system.cpu.itb.misses 134932 # DTB misses +system.cpu.itb.accesses 439226478 # DTB accesses +system.cpu.numCycles 2564620605 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 921877826 # Number of instructions committed -system.cpu.committedOps 1083223459 # Number of ops (including micro ops) committed -system.cpu.discardedOps 92885181 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7623 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100772604966 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.780734 # CPI: cycles per instruction -system.cpu.ipc 0.359617 # IPC: instructions per cycle +system.cpu.committedInsts 922453344 # Number of instructions committed +system.cpu.committedOps 1083887959 # Number of ops (including micro ops) committed +system.cpu.discardedOps 92875630 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7622 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100771468164 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.780217 # CPI: cycles per instruction +system.cpu.ipc 0.359684 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16483 # number of quiesce instructions executed -system.cpu.tickCycles 1740911334 # Number of cycles that the object actually ticked -system.cpu.idleCycles 822585638 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 10734176 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.930080 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320289523 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10734688 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.836873 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 16482 # number of quiesce instructions executed +system.cpu.tickCycles 1741581813 # Number of cycles that the object actually ticked +system.cpu.idleCycles 823038792 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 10731841 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.930081 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 320513038 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10732353 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.864191 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.930080 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.930081 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1345515853 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1345515853 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 163941297 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 163941297 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 147439641 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 147439641 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 511618 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 511618 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 335027 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 335027 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3852667 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3852667 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4161339 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4161339 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 311380938 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 311380938 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 311892556 # number of overall hits -system.cpu.dcache.overall_hits::total 311892556 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6369353 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6369353 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4134165 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4134165 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1400138 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1400138 # 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miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037398 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027275 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027275 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.732383 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.732383 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787241 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.787241 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074556 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074556 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 317353768000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 317353768000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 317353768000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 317353768000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 170415872 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 170415872 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 151684622 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 151684622 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1911159 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1911159 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1574679 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1574679 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4164860 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4164860 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4163152 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4163152 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 322100494 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 322100494 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 324011653 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 324011653 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037383 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037383 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027232 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027232 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.731920 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.731920 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786712 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786712 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074480 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074480 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032631 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032631 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036763 # 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miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036728 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036728 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18428.434171 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18428.434171 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48406.116003 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48406.116003 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 68255.980898 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 68255.980898 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.045777 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.045777 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # 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number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -647,155 +659,155 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8245378 # number of writebacks -system.cpu.dcache.writebacks::total 8245378 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 770684 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 770684 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1822945 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1822945 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 152 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 152 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106000226500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 106000226500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26589323500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26589323500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 83310681500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 83310681500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3491728500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3491728500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 201982521500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 201982521500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228568624500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 228568624500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197557500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197557500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207394000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207394000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12404951500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 12404951500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032873 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032873 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015248 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015248 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.728433 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.728433 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787145 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787145 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057800 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057800 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202068202000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 202068202000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228657525500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 228657525500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197287500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197287500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207449000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207449000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12404736500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12404736500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032861 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032861 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.727967 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.727967 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786615 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786615 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057917 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057917 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024574 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024574 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028729 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028729 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17166.828669 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17166.828669 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45807.465321 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45807.465321 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19091.161270 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19091.161270 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67240.800338 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67240.800338 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14467.237266 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14467.237266 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024555 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024555 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028704 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028704 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17154.701544 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17154.701544 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45906.423204 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45906.423204 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19111.685451 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19111.685451 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67258.390478 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67258.390478 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14475.406064 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14475.406064 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25535.443228 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25535.443228 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24570.729825 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24570.729825 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183920.156097 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183920.156097 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184162.879013 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184162.879013 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184041.533760 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184041.533760 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25548.675167 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25548.675167 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24585.757385 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24585.757385 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183912.143514 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183912.143514 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184164.510770 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184164.510770 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184038.343991 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184038.343991 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24166189 # number of replacements +system.cpu.icache.tags.replacements 24176986 # number of replacements system.cpu.icache.tags.tagsinuse 511.872408 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 414317362 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24166701 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.144142 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 414546703 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24177498 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.145972 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 39504620500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.872408 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 462650783 # Number of tag accesses -system.cpu.icache.tags.data_accesses 462650783 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 414317362 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 414317362 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 414317362 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 414317362 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 414317362 # number of overall hits -system.cpu.icache.overall_hits::total 414317362 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24166711 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24166711 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24166711 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24166711 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24166711 # number of overall misses -system.cpu.icache.overall_misses::total 24166711 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 327482385000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 327482385000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 327482385000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 327482385000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 327482385000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 327482385000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 438484073 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 438484073 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 438484073 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 438484073 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 438484073 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 438484073 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055114 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.055114 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.055114 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.055114 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.055114 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.055114 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13550.970382 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13550.970382 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13550.970382 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13550.970382 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13550.970382 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13550.970382 # average overall miss latency +system.cpu.icache.tags.tag_accesses 462901718 # Number of tag accesses +system.cpu.icache.tags.data_accesses 462901718 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 414546703 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 414546703 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 414546703 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 414546703 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 414546703 # number of overall hits +system.cpu.icache.overall_hits::total 414546703 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24177508 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24177508 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24177508 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24177508 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24177508 # number of overall misses +system.cpu.icache.overall_misses::total 24177508 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 327600086000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 327600086000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 327600086000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 327600086000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 327600086000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 327600086000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 438724211 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 438724211 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 438724211 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 438724211 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 438724211 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 438724211 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055109 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.055109 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.055109 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.055109 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.055109 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.055109 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13549.787100 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13549.787100 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13549.787100 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13549.787100 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13549.787100 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13549.787100 # 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average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128850.667834 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128850.667834 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122367.838615 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123369.027344 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123302.213926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122367.838615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123369.027344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123302.213926 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171418.360685 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136180.714136 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172644.974189 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172644.974189 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171410.437131 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136177.609702 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172646.576277 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172646.576277 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172031.749329 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146447.557471 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172028.589232 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146445.778201 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 70542716 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 35641283 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4403 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2298 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2298 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 70561172 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 35651281 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4392 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2272 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2272 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1728705 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33127830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1729330 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33139930 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 9610686 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24162502 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2728698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 47872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 9609467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24176986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2728127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 47900 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 47873 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2263598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2263598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24166711 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7240510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1346166 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1239502 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72600538 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32434260 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 690132 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2164681 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 107889611 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3096417152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1135639442 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2297512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7399400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4241753506 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2152838 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 38433190 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018207 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.133699 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 47901 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2261407 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2261407 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24177508 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7241194 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1345330 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1238666 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72636616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32428005 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 687897 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2160128 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 107912646 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3098035136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1135439954 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2278088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7359520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4243112698 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2160696 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 38442129 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018241 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.133822 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 37733441 98.18% 98.18% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 699749 1.82% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 37740909 98.18% 98.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 701220 1.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 38433190 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 68234466996 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 38442129 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 68252447493 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1477892 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1464392 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36335720582 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36351871671 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14937837927 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14935181922 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 402991902 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 403175920 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1239794423 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1240232910 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40325 # Transaction distribution -system.iobus.trans_dist::ReadResp 40325 # Transaction distribution +system.iobus.trans_dist::ReadReq 40322 # Transaction distribution +system.iobus.trans_dist::ReadResp 40322 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1252,11 +1264,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353786 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1271,12 +1283,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42167500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492360 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42165000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1298,73 +1310,73 @@ system.iobus.reqLayer16.occupancy 16000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25751500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25683500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34145500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34144500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 565709151 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567247076 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147762000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115486 # number of replacements -system.iocache.tags.tagsinuse 10.440009 # Cycle average of tags in use +system.iocache.tags.replacements 115483 # number of replacements +system.iocache.tags.tagsinuse 10.440004 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13160148730000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.520855 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.919154 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13160148727000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.520843 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.919161 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.220053 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432447 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652501 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432448 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652500 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039893 # Number of tag accesses -system.iocache.tags.data_accesses 1039893 # Number of data accesses +system.iocache.tags.tag_accesses 1039866 # Number of tag accesses +system.iocache.tags.data_accesses 1039866 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8840 # number of demand (read+write) misses -system.iocache.demand_misses::total 8880 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses +system.iocache.demand_misses::total 8877 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8840 # number of overall misses -system.iocache.overall_misses::total 8880 # number of overall misses +system.iocache.overall_misses::realview.ide 8837 # number of overall misses +system.iocache.overall_misses::total 8877 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1638496114 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1643565614 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1647976559 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1653046059 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13864020537 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13864020537 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13408898017 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13408898017 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1638496114 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1643916614 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1647976559 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1653397059 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1638496114 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1643916614 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1647976559 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1653397059 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8840 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8880 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8840 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8880 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1379,54 +1391,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 185350.239140 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185148.768052 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186485.974765 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186279.700135 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129978.441995 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129978.441995 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125711.561698 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125711.561698 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 185350.239140 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 185125.744820 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 186485.974765 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 186256.286921 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 185350.239140 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 185125.744820 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33657 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 186485.974765 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 186256.286921 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33362 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3502 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3432 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.610794 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.720862 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8840 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8880 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8840 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8880 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1196496114 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1199715614 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1206126559 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1209346059 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8530820537 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8530820537 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8070540171 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8070540171 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1196496114 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1199916614 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1206126559 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1209547059 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1196496114 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1199916614 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1206126559 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1209547059 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1441,72 +1453,71 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135350.239140 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 135148.768052 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136485.974765 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136279.700135 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79978.441995 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.441995 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75663.205683 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75663.205683 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 135350.239140 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 135125.744820 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136485.974765 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 136256.286921 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 135350.239140 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 135125.744820 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136485.974765 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 136256.286921 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 86006 # Transaction distribution -system.membus.trans_dist::ReadResp 527021 # Transaction distribution +system.membus.trans_dist::ReadResp 526304 # Transaction distribution system.membus.trans_dist::WriteReq 33706 # Transaction distribution system.membus.trans_dist::WriteResp 33706 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1365292 # Transaction distribution -system.membus.trans_dist::CleanEvict 236782 # Transaction distribution -system.membus.trans_dist::UpgradeReq 38218 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1365657 # Transaction distribution +system.membus.trans_dist::CleanEvict 238956 # Transaction distribution +system.membus.trans_dist::UpgradeReq 38308 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 38219 # Transaction distribution -system.membus.trans_dist::ReadExReq 1148769 # Transaction distribution -system.membus.trans_dist::ReadExResp 1148769 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 441015 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 1150364 # Transaction distribution +system.membus.trans_dist::ReadExResp 1150364 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 440298 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4836672 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4966324 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5307628 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4800126 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4929778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237399 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237399 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5167177 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185058092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 185228498 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7229952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7229952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192458450 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3204 # Total snoops (count) -system.membus.snoop_fanout::samples 3459197 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185137772 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 185308178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7232384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7232384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192540562 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3164 # Total snoops (count) +system.membus.snoop_fanout::samples 3459998 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3459197 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3459998 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3459197 # Request fanout histogram -system.membus.reqLayer0.occupancy 102492500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3459998 # Request fanout histogram +system.membus.reqLayer0.occupancy 102421000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5497000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5498500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9250665962 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9252697708 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8763516637 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8691723530 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 227782427 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44915426 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks |