diff options
| author | Steve Reinhardt <stever@gmail.com> | 2015-03-19 08:41:32 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2015-03-19 08:41:32 -0400 |
| commit | 1483496803f8a8618f62adc5439ce435359b36fe (patch) | |
| tree | a6134ff85d7e6e07e6d34293513f91b16ff94515 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor | |
| parent | f1c3fda965dd4b28ab6b2e99f5f3210fa2089a17 (diff) | |
| download | gem5-1483496803f8a8618f62adc5439ce435359b36fe.tar.xz | |
stats: update Minor stats due to PF bug fix
A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5)
inadvertently fixed a bug in the Minor CPU model which caused it to treat
software prefetches as regular loads. Prior to this changeset, Minor
did an ad-hoc generation of memory commands that left out the PF check;
because it now uses the common code that the other CPU models use,
it generates prefetches properly. These stat changes reflect the fact
that the Minor model now issues SoftPFReqs.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini | 43 | ||||
| -rwxr-xr-x[-rw-r--r--] | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr | 0 | ||||
| -rwxr-xr-x[-rw-r--r--] | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout | 16 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt | 1955 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal | 248 |
5 files changed, 1147 insertions, 1115 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini index f34f6e208..ef40366e9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_loader=/dist/m5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/dist/m5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,21 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel=/dist/m5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.realview.vram system.physmem system.realview.nvmem +memories=system.physmem system.realview.nvmem system.realview.vram +mmap_using_noreserve=false multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/z/stever/hg/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +87,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +image_file=/dist/m5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -186,6 +187,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -220,6 +222,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -237,7 +240,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -645,6 +647,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -713,6 +716,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -730,7 +734,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -755,6 +758,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -788,13 +792,16 @@ size=4194304 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -825,9 +832,11 @@ sys=system type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=1 +frontend_latency=2 +response_latency=2 use_default_range=true -width=8 +width=16 default=system.realview.pciconfig.pio master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma @@ -838,6 +847,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -872,11 +882,14 @@ type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side @@ -926,7 +939,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr index 744db2c76..744db2c76 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout index 9642d869b..e83ff881b 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout @@ -1,16 +1,16 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:22 -gem5 started Oct 29 2014 10:29:11 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 - 0: system.cpu.isa: ISA system set to: 0x5c61b00 0x5c61b00 +info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch64.20140821 + 0: system.cpu.isa: ISA system set to: 0x404afc0 0x404afc0 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51727209160500 because m5_exit instruction encountered +Exiting @ tick 51609998980000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 72f54d4c6..f1c6e64c5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.690388 # Number of seconds simulated -sim_ticks 51690388482000 # Number of ticks simulated -final_tick 51690388482000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.609999 # Number of seconds simulated +sim_ticks 51609998980000 # Number of ticks simulated +final_tick 51609998980000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185969 # Simulator instruction rate (inst/s) -host_op_rate 218525 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10104822635 # Simulator tick rate (ticks/s) -host_mem_usage 719212 # Number of bytes of host memory used -host_seconds 5115.42 # Real time elapsed on the host -sim_insts 951311494 # Number of instructions simulated -sim_ops 1117847862 # Number of ops (including micro ops) simulated +host_inst_rate 125549 # Simulator instruction rate (inst/s) +host_op_rate 147521 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6837484784 # Simulator tick rate (ticks/s) +host_mem_usage 653616 # Number of bytes of host memory used +host_seconds 7548.10 # Real time elapsed on the host +sim_insts 947659008 # Number of instructions simulated +sim_ops 1113505098 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 413184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 346752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10436032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 67415176 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 415104 # Number of bytes read from this memory -system.physmem.bytes_read::total 79026248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10436032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10436032 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 95778368 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 398592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 332160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10228032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 65553800 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 419072 # Number of bytes read from this memory +system.physmem.bytes_read::total 76931656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10228032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10228032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 93992704 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 95798948 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5418 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 163063 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1053375 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6486 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1234798 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1496537 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 94013284 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6228 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5190 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 159813 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1024291 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6548 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1202070 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1468636 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1499110 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6708 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 201895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1304211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1528838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1852924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1853322 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1852924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1304609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3382161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1234798 # Number of read requests accepted -system.physmem.writeReqs 2155868 # Number of write requests accepted -system.physmem.readBursts 1234798 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2155868 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 78985984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 41088 # Total number of bytes read from write queue -system.physmem.bytesWritten 134775168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 79026248 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 137831460 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 642 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 49988 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 39660 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 74085 # Per bank write bursts -system.physmem.perBankRdBursts::1 76722 # Per bank write bursts -system.physmem.perBankRdBursts::2 75273 # Per bank write bursts -system.physmem.perBankRdBursts::3 67779 # Per bank write bursts -system.physmem.perBankRdBursts::4 73670 # Per bank write bursts -system.physmem.perBankRdBursts::5 87218 # Per bank write bursts -system.physmem.perBankRdBursts::6 75623 # Per bank write bursts -system.physmem.perBankRdBursts::7 75034 # Per bank write bursts -system.physmem.perBankRdBursts::8 70647 # Per bank write bursts -system.physmem.perBankRdBursts::9 127770 # Per bank write bursts -system.physmem.perBankRdBursts::10 77193 # Per bank write bursts -system.physmem.perBankRdBursts::11 73706 # Per bank write bursts -system.physmem.perBankRdBursts::12 69495 # Per bank write bursts -system.physmem.perBankRdBursts::13 70758 # Per bank write bursts -system.physmem.perBankRdBursts::14 68705 # Per bank write bursts -system.physmem.perBankRdBursts::15 70478 # Per bank write bursts -system.physmem.perBankWrBursts::0 131375 # Per bank write bursts -system.physmem.perBankWrBursts::1 133100 # Per bank write bursts -system.physmem.perBankWrBursts::2 134570 # Per bank write bursts -system.physmem.perBankWrBursts::3 130352 # Per bank write bursts -system.physmem.perBankWrBursts::4 132576 # Per bank write bursts -system.physmem.perBankWrBursts::5 140660 # Per bank write bursts -system.physmem.perBankWrBursts::6 130709 # Per bank write bursts -system.physmem.perBankWrBursts::7 134220 # Per bank write bursts -system.physmem.perBankWrBursts::8 130946 # Per bank write bursts -system.physmem.perBankWrBursts::9 136651 # Per bank write bursts -system.physmem.perBankWrBursts::10 131424 # Per bank write bursts -system.physmem.perBankWrBursts::11 131217 # Per bank write bursts -system.physmem.perBankWrBursts::12 125851 # Per bank write bursts -system.physmem.perBankWrBursts::13 128099 # Per bank write bursts -system.physmem.perBankWrBursts::14 126227 # Per bank write bursts -system.physmem.perBankWrBursts::15 127885 # Per bank write bursts +system.physmem.num_writes::total 1471209 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7723 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 198179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1270176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1490635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 198179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 198179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1821211 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1821610 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1821211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 198179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1270575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3312245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1202070 # Number of read requests accepted +system.physmem.writeReqs 2120779 # Number of write requests accepted +system.physmem.readBursts 1202070 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2120779 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 76896960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35520 # Total number of bytes read from write queue +system.physmem.bytesWritten 132496640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 76931656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 135585764 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 50494 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 39336 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 72977 # Per bank write bursts +system.physmem.perBankRdBursts::1 77412 # Per bank write bursts +system.physmem.perBankRdBursts::2 73227 # Per bank write bursts +system.physmem.perBankRdBursts::3 70716 # Per bank write bursts +system.physmem.perBankRdBursts::4 69716 # Per bank write bursts +system.physmem.perBankRdBursts::5 78531 # Per bank write bursts +system.physmem.perBankRdBursts::6 70002 # Per bank write bursts +system.physmem.perBankRdBursts::7 72888 # Per bank write bursts +system.physmem.perBankRdBursts::8 66687 # Per bank write bursts +system.physmem.perBankRdBursts::9 126636 # Per bank write bursts +system.physmem.perBankRdBursts::10 72169 # Per bank write bursts +system.physmem.perBankRdBursts::11 76842 # Per bank write bursts +system.physmem.perBankRdBursts::12 69750 # Per bank write bursts +system.physmem.perBankRdBursts::13 69617 # Per bank write bursts +system.physmem.perBankRdBursts::14 66498 # Per bank write bursts +system.physmem.perBankRdBursts::15 67847 # Per bank write bursts +system.physmem.perBankWrBursts::0 128572 # Per bank write bursts +system.physmem.perBankWrBursts::1 129591 # Per bank write bursts +system.physmem.perBankWrBursts::2 133621 # Per bank write bursts +system.physmem.perBankWrBursts::3 133794 # Per bank write bursts +system.physmem.perBankWrBursts::4 127990 # Per bank write bursts +system.physmem.perBankWrBursts::5 135547 # Per bank write bursts +system.physmem.perBankWrBursts::6 129190 # Per bank write bursts +system.physmem.perBankWrBursts::7 132517 # Per bank write bursts +system.physmem.perBankWrBursts::8 125103 # Per bank write bursts +system.physmem.perBankWrBursts::9 133352 # Per bank write bursts +system.physmem.perBankWrBursts::10 128272 # Per bank write bursts +system.physmem.perBankWrBursts::11 129497 # Per bank write bursts +system.physmem.perBankWrBursts::12 125797 # Per bank write bursts +system.physmem.perBankWrBursts::13 127747 # Per bank write bursts +system.physmem.perBankWrBursts::14 124476 # Per bank write bursts +system.physmem.perBankWrBursts::15 125194 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 155 # Number of times write queue was full causing retry -system.physmem.totGap 51690386784000 # Total gap between requests +system.physmem.numWrRetry 166 # Number of times write queue was full causing retry +system.physmem.totGap 51609997338500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1234783 # Read request sizes (log2) +system.physmem.readPktSize::6 1202055 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2153295 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1198377 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 29223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 778 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2118206 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1132428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 547 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 234 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,158 +159,169 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 52281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 61850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 106555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 108316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 116449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 154618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 128128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 118111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 116108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 109682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 109242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 142032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 116099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 110906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 124147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 111898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 106882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 105751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 8381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 7481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 272 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 737863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 289.702517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.794717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.456499 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 301335 40.84% 40.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 180643 24.48% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 66243 8.98% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 37149 5.03% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25772 3.49% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 17225 2.33% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13400 1.82% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 11666 1.58% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 84430 11.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 737863 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 101448 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.165149 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 123.730461 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 101445 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 51481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 61019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 101890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 106045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 113976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 152332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 126167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 115190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 114656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 107766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 140408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 114567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 109101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 121792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 109844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 105744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 103641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 6549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 4213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 344 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 720627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 290.570872 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.798815 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.942314 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 295355 40.99% 40.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 175877 24.41% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 63976 8.88% 74.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35683 4.95% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24604 3.41% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16955 2.35% 84.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13020 1.81% 86.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 11401 1.58% 88.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 83756 11.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 720627 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 99482 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.077512 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 124.901364 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 99480 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 101448 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 101448 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.758044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.253158 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.739377 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 97720 96.33% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 2404 2.37% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 434 0.43% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 505 0.50% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 168 0.17% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 63 0.06% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 44 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-255 12 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 10 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 11 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 20 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-383 26 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-415 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-447 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-479 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-511 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-543 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-575 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-607 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-639 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-703 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-735 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-767 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::832-863 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::896-927 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::928-959 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1152-1183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 101448 # Writes before turning the bus around for reads -system.physmem.totQLat 16140892467 # Total ticks spent queuing -system.physmem.totMemAccLat 39281317467 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6170780000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13078.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 99482 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 99482 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.810398 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.292150 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.172998 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 95801 96.30% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 1933 1.94% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 403 0.41% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 315 0.32% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 148 0.15% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 160 0.16% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 333 0.33% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 129 0.13% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 31 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 15 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 63 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 32 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 14 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 6 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 4 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 7 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 7 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 9 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 20 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 4 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 8 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 99482 # Writes before turning the bus around for reads +system.physmem.totQLat 16741886044 # Total ticks spent queuing +system.physmem.totMemAccLat 39270292294 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6007575000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13933.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31828.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.53 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.61 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32683.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing -system.physmem.readRowHits 952465 # Number of row buffer hits during reads -system.physmem.writeRowHits 1649689 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.34 # Row buffer hit rate for writes -system.physmem.avgGap 15244906.69 # Average gap between requests -system.physmem.pageHitRate 77.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2866207680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1563903000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4722104400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6917801760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3376164558000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1320834277260 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29855603520000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34568672372100 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.764092 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49666580122402 # Time in different power states -system.physmem_0.memoryStateTime::REF 1726055500000 # Time in different power states +system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing +system.physmem.readRowHits 927538 # Number of row buffer hits during reads +system.physmem.writeRowHits 1623609 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.42 # Row buffer hit rate for writes +system.physmem.avgGap 15531851.53 # Average gap between requests +system.physmem.pageHitRate 77.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2802990960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1529409750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4566611400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6809326560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3370914184560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1308588544890 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29818114243500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34513325311620 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.733317 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49604286854347 # Time in different power states +system.physmem_0.memoryStateTime::REF 1723371260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 297752382598 # Time in different power states +system.physmem_0.memoryStateTime::ACT 282340388153 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2712036600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1479781875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4904265600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6728184000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3376164558000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1311236111385 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29864022963750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34567247901210 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.736534 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49680605946994 # Time in different power states -system.physmem_1.memoryStateTime::REF 1726055500000 # Time in different power states +system.physmem_1.actEnergy 2644949160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1443176625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4805158800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6605958240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3370914184560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1300507873200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29825202552000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34512123852585 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.710038 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49616091454429 # Time in different power states +system.physmem_1.memoryStateTime::REF 1723371260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 283722031756 # Time in different power states +system.physmem_1.memoryStateTime::ACT 270535519321 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -334,15 +345,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 261231631 # Number of BP lookups -system.cpu.branchPred.condPredicted 183305796 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12196019 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 193363774 # Number of BTB lookups -system.cpu.branchPred.BTBHits 136711559 # Number of BTB hits +system.cpu.branchPred.lookups 260066829 # Number of BP lookups +system.cpu.branchPred.condPredicted 182351604 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12179122 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 192997810 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135975989 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.701743 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31664930 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2143732 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.454680 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31593975 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2147293 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -373,68 +384,61 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 585994 # Table walker walks requested -system.cpu.dtb.walker.walksLong 585994 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21793 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191747 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 585994 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 585994 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 585994 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 213540 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24710.005137 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20824.581984 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15872.776829 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 123160 57.68% 57.68% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 87731 41.08% 98.76% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 1449 0.68% 99.44% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 786 0.37% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 33 0.02% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 127 0.06% 99.88% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-229375 51 0.02% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::229376-262143 62 0.03% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 77 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 22 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 20 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::360448-393215 10 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-491519 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 213540 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 583127 # Table walker walks requested +system.cpu.dtb.walker.walksLong 583127 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22581 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191165 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 583127 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 583127 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 583127 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 213746 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24576.454072 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20707.683114 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15710.461946 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 211230 98.82% 98.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 2148 1.00% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 131 0.06% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 118 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 73 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 213746 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples -15748296 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 -15748296 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total -15748296 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 191748 89.79% 89.79% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 21793 10.21% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 213541 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 585994 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 191166 89.44% 89.44% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 22581 10.56% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 213747 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 583127 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 585994 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213541 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 583127 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213747 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213541 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 799535 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213747 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 796874 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183604569 # DTB read hits -system.cpu.dtb.read_misses 484391 # DTB read misses -system.cpu.dtb.write_hits 162970808 # DTB write hits -system.cpu.dtb.write_misses 101603 # DTB write misses +system.cpu.dtb.read_hits 182952995 # DTB read hits +system.cpu.dtb.read_misses 481784 # DTB read misses +system.cpu.dtb.write_hits 162354187 # DTB write hits +system.cpu.dtb.write_misses 101343 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47405 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 80226 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 794 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 47075 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 80213 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 854 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14789 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23565 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 184088960 # DTB read accesses -system.cpu.dtb.write_accesses 163072411 # DTB write accesses +system.cpu.dtb.perms_faults 23472 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 183434779 # DTB read accesses +system.cpu.dtb.write_accesses 162455530 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 346575377 # DTB hits -system.cpu.dtb.misses 585994 # DTB misses -system.cpu.dtb.accesses 347161371 # DTB accesses +system.cpu.dtb.hits 345307182 # DTB hits +system.cpu.dtb.misses 583127 # DTB misses +system.cpu.dtb.accesses 345890309 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -464,175 +468,183 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 136676 # Table walker walks requested -system.cpu.itb.walker.walksLong 136676 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1079 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 118957 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 136676 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 136676 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 136676 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 120036 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 27117.842072 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23228.726671 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 17468.785563 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 117053 97.51% 97.51% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2702 2.25% 99.77% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 172 0.14% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 64 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 25 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 17 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 120036 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 136411 # Table walker walks requested +system.cpu.itb.walker.walksLong 136411 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1074 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 118764 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 136411 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 136411 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 136411 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 119838 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 26864.678099 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23079.638443 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17315.603436 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 117018 97.65% 97.65% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2553 2.13% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 159 0.13% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 57 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 28 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 119838 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples -16365796 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 -16365796 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total -16365796 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 118957 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1079 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 120036 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 118764 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1074 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 119838 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136676 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 136676 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136411 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 136411 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120036 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 120036 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 256712 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 454948976 # ITB inst hits -system.cpu.itb.inst_misses 136676 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119838 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 119838 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 256249 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 452746266 # ITB inst hits +system.cpu.itb.inst_misses 136411 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47405 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57709 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 47075 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 57592 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 370702 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 369764 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 455085652 # ITB inst accesses -system.cpu.itb.hits 454948976 # DTB hits -system.cpu.itb.misses 136676 # DTB misses -system.cpu.itb.accesses 455085652 # DTB accesses -system.cpu.numCycles 2543244455 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 452882677 # ITB inst accesses +system.cpu.itb.hits 452746266 # DTB hits +system.cpu.itb.misses 136411 # DTB misses +system.cpu.itb.accesses 452882677 # DTB accesses +system.cpu.numCycles 2486475408 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 951311494 # Number of instructions committed -system.cpu.committedOps 1117847862 # Number of ops (including micro ops) committed -system.cpu.discardedOps 97312681 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7756 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100838701590 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.673409 # CPI: cycles per instruction -system.cpu.ipc 0.374054 # IPC: instructions per cycle +system.cpu.committedInsts 947659008 # Number of instructions committed +system.cpu.committedOps 1113505098 # Number of ops (including micro ops) committed +system.cpu.discardedOps 96546934 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7735 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100734690731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.623808 # CPI: cycles per instruction +system.cpu.ipc 0.381125 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16616 # number of quiesce instructions executed -system.cpu.tickCycles 1803568308 # Number of cycles that the object actually ticked -system.cpu.idleCycles 739676147 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 11160252 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.957398 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 330283218 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11160764 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.593245 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 16595 # number of quiesce instructions executed +system.cpu.tickCycles 1791502894 # Number of cycles that the object actually ticked +system.cpu.idleCycles 694972514 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 11092406 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.957332 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 328965151 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11092918 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.655421 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4320792250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.957398 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.957332 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1387540349 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1387540349 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 169325544 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 169325544 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 152117254 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 152117254 # number of WriteReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336638 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 336638 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4103260 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4103260 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4350721 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4350721 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 321442798 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 321442798 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 321442798 # number of overall hits -system.cpu.dcache.overall_hits::total 321442798 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 8046914 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 8046914 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4320227 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4320227 # number of WriteReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245138 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1245138 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 249194 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 249194 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1382417296 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1382417296 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 168207875 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 168207875 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 151549113 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 151549113 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 490930 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 490930 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 335942 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 335942 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4008865 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4008865 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4323127 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4323127 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 319756988 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 319756988 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 320247918 # number of overall hits +system.cpu.dcache.overall_hits::total 320247918 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6578537 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6578537 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4302299 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4302299 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1473808 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1473808 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1244599 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1244599 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 315993 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 315993 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 12367141 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12367141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12367141 # number of overall misses -system.cpu.dcache.overall_misses::total 12367141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 131461867675 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 131461867675 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 154903534956 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 154903534956 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35707428702 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35707428702 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3656528250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 3656528250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 10880836 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10880836 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12354644 # number of overall misses +system.cpu.dcache.overall_misses::total 12354644 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 106697920457 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 106697920457 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 153242376598 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 153242376598 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35461255171 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35461255171 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4805977234 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4805977234 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 286365402631 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 286365402631 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 286365402631 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 286365402631 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 177372458 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177372458 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 156437481 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 156437481 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1581776 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1581776 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4352454 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4352454 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4350722 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4350722 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 333809939 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 333809939 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 333809939 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 333809939 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.045367 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.045367 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027616 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027616 # miss rate for WriteReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787177 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787177 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057254 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057254 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 259940297055 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 259940297055 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 259940297055 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 259940297055 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 174786412 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 174786412 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 155851412 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 155851412 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1964738 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1964738 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1580541 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1580541 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4324858 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4324858 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4323128 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4323128 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 330637824 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 330637824 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 332602562 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 332602562 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037638 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037638 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027605 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027605 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.750130 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.750130 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787451 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787451 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073064 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073064 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037048 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037048 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037048 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037048 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16336.929620 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16336.929620 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.415689 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.415689 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28677.486915 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28677.486915 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14673.420106 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14673.420106 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.032909 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032909 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037145 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037145 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.095592 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.095592 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35618.718410 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35618.718410 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28492.112858 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28492.112858 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15209.125626 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15209.125626 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23155.343877 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23155.343877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23155.343877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23155.343877 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23889.735775 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23889.735775 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21039.885654 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21039.885654 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,82 +653,90 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8571803 # number of writebacks -system.cpu.dcache.writebacks::total 8571803 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 759012 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 759012 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1891728 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1891728 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 152 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 152 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2650740 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2650740 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2650740 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2650740 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7287902 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7287902 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2428499 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2428499 # number of WriteReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244986 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244986 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 249191 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 249191 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 8509656 # number of writebacks +system.cpu.dcache.writebacks::total 8509656 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 799615 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 799615 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1895946 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1895946 # number of WriteReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 144 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 144 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69791 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 69791 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2695561 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2695561 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2695561 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2695561 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5778922 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5778922 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2406353 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2406353 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1466300 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1466300 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244455 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244455 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 246202 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 246202 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9716401 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9716401 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9716401 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9716401 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108232242328 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 108232242328 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80044946410 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 80044946410 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33835516298 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33835516298 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3281036750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3281036750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 8185275 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8185275 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9651575 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9651575 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84566997800 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 84566997800 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78901247228 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 78901247228 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22730570766 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22730570766 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33591268829 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33591268829 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3240983258 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3240983258 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 80500 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 80500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 188277188738 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 188277188738 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 188277188738 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 188277188738 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5752052750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5752052750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5611431750 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5611431750 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363484500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363484500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041088 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041088 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015524 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015524 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787081 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787081 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057253 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057253 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163468245028 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 163468245028 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186198815794 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 186198815794 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751743992 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751743992 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5611366250 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5611366250 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363110242 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363110242 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033063 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033063 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015440 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015440 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746308 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746308 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787360 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787360 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056927 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056927 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029108 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029108 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029108 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029108 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14850.946449 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14850.946449 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32960.666819 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32960.666819 # average WriteReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27177.427134 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27177.427134 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.754618 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.754618 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024756 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024756 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029018 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029018 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14633.697738 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14633.697738 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32788.725190 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32788.725190 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15501.991929 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15501.991929 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 26992.754924 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26992.754924 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13163.919294 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13163.919294 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19377.255914 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19377.255914 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19377.255914 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19377.255914 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19971.014416 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19971.014416 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19292.065367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19292.065367 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -724,58 +744,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24658319 # number of replacements -system.cpu.icache.tags.tagsinuse 511.926866 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 429907589 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24658831 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.434224 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 23112715250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.926866 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 24538707 # number of replacements +system.cpu.icache.tags.tagsinuse 511.926996 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 427825373 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24539219 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.434352 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 22330853250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.926996 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999857 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 479225270 # Number of tag accesses -system.cpu.icache.tags.data_accesses 479225270 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 429907589 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 429907589 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 429907589 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13331.208004 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13324.567403 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13324.567403 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13324.567403 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13324.567403 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13324.567403 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13324.567403 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -784,18 +804,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24658841 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24658841 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24658841 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 24658841 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 24658841 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 24658841 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 291693903909 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 291693903909 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 291693903909 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 291693903909 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 291693903909 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 291693903909 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24539229 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 24539229 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 24539229 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 24539229 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 24539229 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 24539229 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290116862082 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 290116862082 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290116862082 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 290116862082 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 290116862082 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 290116862082 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4024065500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4024065500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4024065500 # number of overall MSHR uncacheable cycles @@ -806,187 +826,186 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054247 system.cpu.icache.demand_mshr_miss_rate::total 0.054247 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054247 # 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Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1697658 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.714400 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1594461 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65370.145273 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 40075906 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1658209 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.168187 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 6394381000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36150.495855 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 348.587735 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 419.061629 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8126.200133 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20284.052712 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.551613 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005319 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006394 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123996 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.309510 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996832 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 298 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62661 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5172564500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5172564500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5279396750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8388316750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5172507000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5172507000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3108920000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10452120750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13561040750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006626 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018732 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004493 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.044596 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013712 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.442009 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.442009 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.780049 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.780049 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10451903750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13560823750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006438 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018129 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004383 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.043178 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013292 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.436398 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.436398 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.781892 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.781892 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.302032 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.302032 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006626 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018732 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004493 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.106358 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.032850 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006626 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018732 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004493 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.106358 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.032850 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73885.455390 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73993.586194 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69252.307740 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71119.001842 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70741.075007 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 33684.334226 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33684.334226 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17742.304086 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17742.304086 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.297836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.297836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006438 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018129 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004383 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104132 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.032112 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006438 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018129 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004383 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.104132 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.032112 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69526.454526 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72580.357467 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71879.898685 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 33699.036547 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33699.036547 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17744.117563 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17744.117563 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69377.787528 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69377.787528 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73885.455390 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.835215 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1115,56 +1134,56 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 33999690 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33991608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8571803 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 49796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 33827953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33819864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8509656 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351233 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 49295 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 49797 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2378926 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2378926 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49422267 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31128556 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 697608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2275060 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 83523491 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581512448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1263125858 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2313872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7794488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2854746666 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 562001 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 46265986 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.002499 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.049932 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 49296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2357319 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2357319 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49183042 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30929702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 693856 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2262449 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 83069049 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1573857216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1254806154 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2290296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7738512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2838692178 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 565529 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 46009467 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.002514 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.050072 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 46150346 99.75% 99.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 115640 0.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 45893822 99.75% 99.75% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115645 0.25% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 46265986 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 32968786985 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 46009467 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32777837483 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1168500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1164000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 37104005805 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36924053878 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15790852218 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15679140875 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 409077948 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 408249695 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1301562725 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1295905979 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40307 # Transaction distribution -system.iobus.trans_dist::ReadResp 40307 # Transaction distribution +system.iobus.trans_dist::ReadReq 40311 # Transaction distribution +system.iobus.trans_dist::ReadResp 40311 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1184,11 +1203,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230972 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230972 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230980 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1205,11 +1224,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334352 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334352 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492272 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1238,71 +1257,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 606946752 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607011706 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148389141 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148422470 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115468 # number of replacements -system.iocache.tags.tagsinuse 10.447877 # Cycle average of tags in use +system.iocache.tags.replacements 115472 # number of replacements +system.iocache.tags.tagsinuse 10.439528 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115484 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115488 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13143236480000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.519281 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.928596 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219955 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433037 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652992 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13142428728000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.524738 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.914790 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220296 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432174 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652471 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039731 # Number of tag accesses -system.iocache.tags.data_accesses 1039731 # Number of data accesses +system.iocache.tags.tag_accesses 1039767 # Number of tag accesses +system.iocache.tags.data_accesses 1039767 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8822 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8859 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8826 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8863 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8822 # number of demand (read+write) misses -system.iocache.demand_misses::total 8862 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8826 # number of demand (read+write) misses +system.iocache.demand_misses::total 8866 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8822 # number of overall misses -system.iocache.overall_misses::total 8862 # number of overall misses +system.iocache.overall_misses::realview.ide 8826 # number of overall misses +system.iocache.overall_misses::total 8866 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1598742761 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1603814761 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1599431674 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1604503674 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19786721850 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19786721850 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19839532562 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19839532562 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1598742761 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1604167261 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1599431674 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1604856174 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1598742761 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1604167261 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1599431674 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1604856174 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8822 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8859 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8826 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8863 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8822 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8862 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8826 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8866 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8822 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8862 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8826 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8866 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1317,54 +1336,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 181222.258105 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 181037.900553 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 181218.181962 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 181033.924630 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185505.154973 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 185505.154973 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186000.267775 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186000.267775 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 181222.258105 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 181016.391447 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 181218.181962 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 181012.426573 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 181222.258105 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 181016.391447 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 108614 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 181218.181962 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 181012.426573 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 109629 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16000 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16167 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.788375 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.781035 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8822 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8859 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8826 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8863 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8822 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8862 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8826 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8866 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8822 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8862 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8826 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8866 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1138893007 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1142035007 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1139388578 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1142530578 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14240157886 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14240157886 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14292968598 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14292968598 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1138893007 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1142228507 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1139388578 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1142724078 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1138893007 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1142228507 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1139388578 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1142724078 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1379,70 +1398,70 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129096.917592 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 128912.406254 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129094.559030 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 128910.140810 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133504.817802 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133504.817802 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133999.930605 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133999.930605 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 129096.917592 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 128890.601106 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 129094.559030 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 128888.346267 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 129096.917592 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 128890.601106 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 129094.559030 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 128888.346267 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 553634 # Transaction distribution -system.membus.trans_dist::ReadResp 553634 # Transaction distribution -system.membus.trans_dist::WriteReq 33707 # Transaction distribution -system.membus.trans_dist::WriteResp 33707 # Transaction distribution -system.membus.trans_dist::Writeback 1496537 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 656758 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 656758 # Transaction distribution -system.membus.trans_dist::UpgradeReq 39666 # Transaction distribution +system.membus.trans_dist::ReadReq 537267 # Transaction distribution +system.membus.trans_dist::ReadResp 537267 # Transaction distribution +system.membus.trans_dist::WriteReq 33705 # Transaction distribution +system.membus.trans_dist::WriteResp 33705 # Transaction distribution +system.membus.trans_dist::Writeback 1468636 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 649570 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 649570 # Transaction distribution +system.membus.trans_dist::UpgradeReq 39342 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 39667 # Transaction distribution -system.membus.trans_dist::ReadExReq 717891 # Transaction distribution -system.membus.trans_dist::ReadExResp 717891 # Transaction distribution +system.membus.trans_dist::UpgradeResp 39343 # Transaction distribution +system.membus.trans_dist::ReadExReq 701468 # Transaction distribution +system.membus.trans_dist::ReadExResp 701468 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5031846 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5161506 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335307 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335307 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5496813 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4923341 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5052989 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335373 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335373 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5388362 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 202791724 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 202962146 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14065984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14065984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 217028130 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3038 # Total snoops (count) -system.membus.snoop_fanout::samples 3378648 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198447468 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 198617866 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14069952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14069952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 212687818 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2980 # Total snoops (count) +system.membus.snoop_fanout::samples 3310460 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3378648 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3310460 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3378648 # Request fanout histogram -system.membus.reqLayer0.occupancy 100002500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3310460 # Request fanout histogram +system.membus.reqLayer0.occupancy 99903000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5714500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5637000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 12721299869 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 12263986868 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7256295209 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7071367467 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151537359 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151550030 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal index 5c853e457..2bb89eb2c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal @@ -34,133 +34,133 @@ [ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[ 0.000026] Console: colour dummy device 80x25
[ 0.000029] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000030] pid_max: default: 32768 minimum: 301
-[ 0.000044] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000046] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000174] hw perfevents: no hardware support available
-[ 1.060092] CPU1: failed to come online
-[ 2.080180] CPU2: failed to come online
-[ 3.100268] CPU3: failed to come online
-[ 3.100271] Brought up 1 CPUs
-[ 3.100273] SMP: Total of 1 processors activated.
-[ 3.100341] devtmpfs: initialized
-[ 3.101042] atomic64_test: passed
-[ 3.101098] regulator-dummy: no parameters
-[ 3.101606] NET: Registered protocol family 16
-[ 3.101773] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.101783] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.102080] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.102082] Serial: AMBA PL011 UART driver
-[ 3.102304] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.102346] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.102874] console [ttyAMA0] enabled
-[ 3.102953] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.102989] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.103025] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.103058] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130671] 3V3: 3300 mV
-[ 3.130723] vgaarb: loaded
-[ 3.130779] SCSI subsystem initialized
-[ 3.130831] libata version 3.00 loaded.
-[ 3.130889] usbcore: registered new interface driver usbfs
-[ 3.130910] usbcore: registered new interface driver hub
-[ 3.130951] usbcore: registered new device driver usb
-[ 3.130982] pps_core: LinuxPPS API ver. 1 registered
-[ 3.130991] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.131010] PTP clock support registered
-[ 3.131159] Switched to clocksource arch_sys_counter
-[ 3.132645] NET: Registered protocol family 2
-[ 3.132738] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.132758] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.132782] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.132801] TCP: reno registered
-[ 3.132808] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132822] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132867] NET: Registered protocol family 1
-[ 3.132915] RPC: Registered named UNIX socket transport module.
-[ 3.132925] RPC: Registered udp transport module.
-[ 3.132933] RPC: Registered tcp transport module.
-[ 3.132941] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.132953] PCI: CLS 0 bytes, default 64
-[ 3.133150] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.133293] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.135708] fuse init (API version 7.23)
-[ 3.135822] msgmni has been set to 469
-[ 3.138911] io scheduler noop registered
-[ 3.138984] io scheduler cfq registered (default)
-[ 3.139445] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.139457] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.139469] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.139481] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.139491] pci_bus 0000:00: scanning bus
-[ 3.139501] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.139514] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.139528] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.139574] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.139586] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.139597] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.139607] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.139618] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.139629] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.139640] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.139683] pci_bus 0000:00: fixups for bus
-[ 3.139691] pci_bus 0000:00: bus scan returning with max=00
-[ 3.139703] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.139723] pci 0000:00:00.0: fixup irq: got 33
-[ 3.139731] pci 0000:00:00.0: assigning IRQ 33
-[ 3.139742] pci 0000:00:01.0: fixup irq: got 34
-[ 3.139750] pci 0000:00:01.0: assigning IRQ 34
-[ 3.139762] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.139775] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.139788] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.139801] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.139812] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.139823] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.139835] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.139846] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.140504] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.140842] ata_piix 0000:00:01.0: version 2.13
-[ 3.140853] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.140875] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.141475] scsi0 : ata_piix
-[ 3.141603] scsi1 : ata_piix
-[ 3.141641] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.141654] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.141783] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.141795] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.141811] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.141823] e1000 0000:00:00.0: enabling bus mastering
-[ 3.301188] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.301198] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.301227] ata1.00: configured for UDMA/33
-[ 3.301281] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.301428] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.301457] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.301505] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.301514] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.301538] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.301694] sda: sda1
-[ 3.301852] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.421479] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.421492] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.421515] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.421525] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.421549] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.421561] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.421651] usbcore: registered new interface driver usb-storage
-[ 3.421719] mousedev: PS/2 mouse device common for all mice
-[ 3.421922] usbcore: registered new interface driver usbhid
-[ 3.421931] usbhid: USB HID core driver
-[ 3.421965] TCP: cubic registered
-[ 3.421972] NET: Registered protocol family 17
- -[ 3.422426] devtmpfs: mounted
+[ 0.000031] pid_max: default: 32768 minimum: 301
+[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000047] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000180] hw perfevents: no hardware support available
+[ 1.060095] CPU1: failed to come online
+[ 2.080185] CPU2: failed to come online
+[ 3.100275] CPU3: failed to come online
+[ 3.100278] Brought up 1 CPUs
+[ 3.100280] SMP: Total of 1 processors activated.
+[ 3.100349] devtmpfs: initialized
+[ 3.100980] atomic64_test: passed
+[ 3.101035] regulator-dummy: no parameters
+[ 3.101538] NET: Registered protocol family 16
+[ 3.101703] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.101713] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.102141] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.102147] Serial: AMBA PL011 UART driver
+[ 3.102394] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.102440] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.102971] console [ttyAMA0] enabled
+[ 3.103068] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.103104] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.103141] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.103175] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130690] 3V3: 3300 mV
+[ 3.130742] vgaarb: loaded
+[ 3.130800] SCSI subsystem initialized
+[ 3.130851] libata version 3.00 loaded.
+[ 3.130907] usbcore: registered new interface driver usbfs
+[ 3.130928] usbcore: registered new interface driver hub
+[ 3.130968] usbcore: registered new device driver usb
+[ 3.130999] pps_core: LinuxPPS API ver. 1 registered
+[ 3.131008] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.131027] PTP clock support registered
+[ 3.131174] Switched to clocksource arch_sys_counter
+[ 3.132602] NET: Registered protocol family 2
+[ 3.132697] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.132719] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.132744] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.132760] TCP: reno registered
+[ 3.132768] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.132782] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.132828] NET: Registered protocol family 1
+[ 3.132876] RPC: Registered named UNIX socket transport module.
+[ 3.132886] RPC: Registered udp transport module.
+[ 3.132894] RPC: Registered tcp transport module.
+[ 3.132902] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.132914] PCI: CLS 0 bytes, default 64
+[ 3.133108] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.133253] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.135428] fuse init (API version 7.23)
+[ 3.135535] msgmni has been set to 469
+[ 3.138600] io scheduler noop registered
+[ 3.138667] io scheduler cfq registered (default)
+[ 3.139158] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.139171] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.139182] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.139194] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.139204] pci_bus 0000:00: scanning bus
+[ 3.139215] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.139228] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.139243] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.139286] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.139299] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.139310] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.139320] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.139331] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.139342] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.139353] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.139394] pci_bus 0000:00: fixups for bus
+[ 3.139403] pci_bus 0000:00: bus scan returning with max=00
+[ 3.139414] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.139435] pci 0000:00:00.0: fixup irq: got 33
+[ 3.139444] pci 0000:00:00.0: assigning IRQ 33
+[ 3.139455] pci 0000:00:01.0: fixup irq: got 34
+[ 3.139463] pci 0000:00:01.0: assigning IRQ 34
+[ 3.139475] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.139488] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.139501] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.139514] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.139525] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.139537] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.139548] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.139559] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.140184] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.140520] ata_piix 0000:00:01.0: version 2.13
+[ 3.140531] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.140555] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.140911] scsi0 : ata_piix
+[ 3.141038] scsi1 : ata_piix
+[ 3.141075] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.141087] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.141242] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.141254] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.141271] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.141283] e1000 0000:00:00.0: enabling bus mastering
+[ 3.301203] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.301213] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.301243] ata1.00: configured for UDMA/33
+[ 3.301299] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.301438] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.301467] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.301514] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.301523] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.301547] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.301695] sda: sda1
+[ 3.301842] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.421490] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.421503] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.421526] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.421536] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.421559] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.421571] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.421656] usbcore: registered new interface driver usb-storage
+[ 3.421723] mousedev: PS/2 mouse device common for all mice
+[ 3.421911] usbcore: registered new interface driver usbhid
+[ 3.421921] usbhid: USB HID core driver
+[ 3.421955] TCP: cubic registered
+[ 3.421963] NET: Registered protocol family 17
+ +[ 3.422420] devtmpfs: mounted
[ 3.422455] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.464515] udevd[607]: starting version 182
+[ 3.464312] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.614679] random: dd urandom read with 21 bits of entropy available
+[ 3.594630] random: dd urandom read with 20 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.781391] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 3.751405] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
|