diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
| commit | 0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (patch) | |
| tree | 45d559d0511bdca749a08a2f42eeafdcf25739cf /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker | |
| parent | 3de9def6c1ad38d6a5068b07512cbefffafcb758 (diff) | |
| download | gem5-0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e.tar.xz | |
stats: updates due to recent changesets including d0934b57735a
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker')
4 files changed, 1530 insertions, 1526 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini index ef60c64b3..7fb6c1d15 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -352,7 +352,7 @@ type=ExeTracer eventq_index=0 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -693,7 +693,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -803,7 +803,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -891,7 +891,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1306,9 +1306,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr index 18ae58d7b..95cf6c86b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr @@ -11,84 +11,89 @@ warn: 12461855003000: Instruction results do not match! (Values may not actually warn: 12461858210000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist -warn: 13850221736500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13887901759500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13889201357500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13891026528000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13912972124000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13922135264000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13972304377500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 14214756028000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14214756243500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14222804811500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14230560980500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14230561210500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14230561417000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14238296234000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14238296464000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14238296670500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14243468378000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14243468608000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14249670454500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14249670684500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14259219992000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14259220222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14259220428500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14270200247500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14270200481500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14270200711500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14270200918000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14279912002500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14279912512000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14279912746000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14279912976000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14279913182500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14295232623000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14295232862500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14300292322000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14300292552000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14307240927500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14307241161500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14307241391500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14307241598000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14317300126000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14317300896500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14317301130500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14317301360500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14317301567000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14379824982500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14379825231000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14379825446500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14437325800500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14437326869000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14437327084500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14565495184000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565581739000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14565581956000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565582249000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 -warn: 14565582808000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565583286500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565583575500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565584084500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565585151500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14565585961500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566302033500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566302294500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42 -warn: 14566302499000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566373295000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 -warn: 14566373505000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566373776000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 -warn: 14566374346500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566374602000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 -warn: 14566374825500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566375114500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566375623500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566376687000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566377185000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14566377487000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14614511931000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 -warn: 14614512222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14614512481000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14614512725500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14614512987500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14614513217000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 +warn: 13846883856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13889111424500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13890567287500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13890857543500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14120809755000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14122306502500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14122718805500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14129885647500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14130112878000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14130333669000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14130937323000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14131157192000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14131378652000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14143275616000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14210692350500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14453290384000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14453290599500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14461368009500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14469164155500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14469164395000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14469164601500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14477036010500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14477036254000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14477036493500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14477036700000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14482248599500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14482248839000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14488506207500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14488506438000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14498157332500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14498158077500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14498158308000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14498158514500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14509187190500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14509187421000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14509187627500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14518942903500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14518943414000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14518943648500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14518943879000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14518944085500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14534430251500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14534430481500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14539499143500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14539499377500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14539499607500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14546501559500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14546502303000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14546502533000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14546502739500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14556606981000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14556607490500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14556607724500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14556607954500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14556608161000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14619728573500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14619728789000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14678031922000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14678032489500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14678032742000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14678032990500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14678033206000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14803922617500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804021218000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804021536500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804745192000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804745453000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42 +warn: 14804745657500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804816537000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 +warn: 14804816747000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804817018000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 +warn: 14804817588500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804817844000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 +warn: 14804818067500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804818356500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804818865500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804819928000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804820419500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14804820721500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14853183049500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14853362963500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 +warn: 14853363240000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14853363492000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14853363736500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14853363998500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14853364228000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout index 703b25032..ddf9e75e0 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 11:01:08 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 01:50:46 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51323721423000 because m5_exit instruction encountered +Exiting @ tick 51562169701000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index 597734940..e2a586128 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.323721 # Number of seconds simulated -sim_ticks 51323721423000 # Number of ticks simulated -final_tick 51323721423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.562170 # Number of seconds simulated +sim_ticks 51562169701000 # Number of ticks simulated +final_tick 51562169701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88242 # Simulator instruction rate (inst/s) -host_op_rate 103686 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5307363437 # Simulator tick rate (ticks/s) -host_mem_usage 679356 # Number of bytes of host memory used -host_seconds 9670.29 # Real time elapsed on the host -sim_insts 853325819 # Number of instructions simulated -sim_ops 1002674190 # Number of ops (including micro ops) simulated +host_inst_rate 60233 # Simulator instruction rate (inst/s) +host_op_rate 70799 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2812244888 # Simulator tick rate (ticks/s) +host_mem_usage 727556 # Number of bytes of host memory used +host_seconds 18334.88 # Real time elapsed on the host +sim_insts 1104366834 # Number of instructions simulated +sim_ops 1298086167 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 203200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 189632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5727200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 73778504 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 419776 # Number of bytes read from this memory -system.physmem.bytes_read::total 80318312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5727200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5727200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68723904 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 657984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 557504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6634080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 148649160 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 417792 # Number of bytes read from this memory +system.physmem.bytes_read::total 156916520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6634080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6634080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 139624832 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 68744484 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3175 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 105440 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1152802 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6559 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1270939 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1073811 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 139645412 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 10281 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8711 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 119610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2322656 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6528 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2467786 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2181638 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1076384 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 3959 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 3695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 111590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1437513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1564935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 111590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 111590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1339028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1339429 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1339028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 3959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 3695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 111590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1437914 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2904365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1270939 # Number of read requests accepted -system.physmem.writeReqs 1076384 # Number of write requests accepted -system.physmem.readBursts 1270939 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1076384 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 81299584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 40512 # Total number of bytes read from write queue -system.physmem.bytesWritten 68742976 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 80318312 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 68744484 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 633 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 142017 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 76590 # Per bank write bursts -system.physmem.perBankRdBursts::1 80112 # Per bank write bursts -system.physmem.perBankRdBursts::2 82312 # Per bank write bursts -system.physmem.perBankRdBursts::3 76894 # Per bank write bursts -system.physmem.perBankRdBursts::4 75148 # Per bank write bursts -system.physmem.perBankRdBursts::5 84486 # Per bank write bursts -system.physmem.perBankRdBursts::6 75307 # Per bank write bursts -system.physmem.perBankRdBursts::7 76047 # Per bank write bursts -system.physmem.perBankRdBursts::8 76921 # Per bank write bursts -system.physmem.perBankRdBursts::9 104197 # Per bank write bursts -system.physmem.perBankRdBursts::10 75653 # Per bank write bursts -system.physmem.perBankRdBursts::11 81028 # Per bank write bursts -system.physmem.perBankRdBursts::12 74845 # Per bank write bursts -system.physmem.perBankRdBursts::13 77383 # Per bank write bursts -system.physmem.perBankRdBursts::14 76622 # Per bank write bursts -system.physmem.perBankRdBursts::15 76761 # Per bank write bursts -system.physmem.perBankWrBursts::0 64108 # Per bank write bursts -system.physmem.perBankWrBursts::1 67910 # Per bank write bursts -system.physmem.perBankWrBursts::2 69982 # Per bank write bursts -system.physmem.perBankWrBursts::3 67432 # Per bank write bursts -system.physmem.perBankWrBursts::4 65959 # Per bank write bursts -system.physmem.perBankWrBursts::5 70786 # Per bank write bursts -system.physmem.perBankWrBursts::6 64733 # Per bank write bursts -system.physmem.perBankWrBursts::7 66187 # Per bank write bursts -system.physmem.perBankWrBursts::8 67287 # Per bank write bursts -system.physmem.perBankWrBursts::9 71812 # Per bank write bursts -system.physmem.perBankWrBursts::10 65064 # Per bank write bursts -system.physmem.perBankWrBursts::11 69201 # Per bank write bursts -system.physmem.perBankWrBursts::12 65082 # Per bank write bursts -system.physmem.perBankWrBursts::13 66370 # Per bank write bursts -system.physmem.perBankWrBursts::14 66024 # Per bank write bursts -system.physmem.perBankWrBursts::15 66172 # Per bank write bursts +system.physmem.num_writes::total 2184211 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 12761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 10812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 128662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2882911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3043249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 128662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 128662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2707893 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2708292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2707893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 10812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 128662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2883310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5751541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2467786 # Number of read requests accepted +system.physmem.writeReqs 2184211 # Number of write requests accepted +system.physmem.readBursts 2467786 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2184211 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 157889856 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 48448 # Total number of bytes read from write queue +system.physmem.bytesWritten 139644224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 156916520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 139645412 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 757 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 155211 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 149005 # Per bank write bursts +system.physmem.perBankRdBursts::1 156339 # Per bank write bursts +system.physmem.perBankRdBursts::2 155955 # Per bank write bursts +system.physmem.perBankRdBursts::3 150628 # Per bank write bursts +system.physmem.perBankRdBursts::4 148084 # Per bank write bursts +system.physmem.perBankRdBursts::5 159303 # Per bank write bursts +system.physmem.perBankRdBursts::6 149188 # Per bank write bursts +system.physmem.perBankRdBursts::7 152515 # Per bank write bursts +system.physmem.perBankRdBursts::8 150862 # Per bank write bursts +system.physmem.perBankRdBursts::9 179370 # Per bank write bursts +system.physmem.perBankRdBursts::10 150320 # Per bank write bursts +system.physmem.perBankRdBursts::11 155893 # Per bank write bursts +system.physmem.perBankRdBursts::12 152080 # Per bank write bursts +system.physmem.perBankRdBursts::13 155961 # Per bank write bursts +system.physmem.perBankRdBursts::14 150556 # Per bank write bursts +system.physmem.perBankRdBursts::15 150970 # Per bank write bursts +system.physmem.perBankWrBursts::0 132106 # Per bank write bursts +system.physmem.perBankWrBursts::1 138501 # Per bank write bursts +system.physmem.perBankWrBursts::2 137398 # Per bank write bursts +system.physmem.perBankWrBursts::3 135602 # Per bank write bursts +system.physmem.perBankWrBursts::4 133392 # Per bank write bursts +system.physmem.perBankWrBursts::5 140433 # Per bank write bursts +system.physmem.perBankWrBursts::6 132940 # Per bank write bursts +system.physmem.perBankWrBursts::7 137025 # Per bank write bursts +system.physmem.perBankWrBursts::8 135656 # Per bank write bursts +system.physmem.perBankWrBursts::9 141181 # Per bank write bursts +system.physmem.perBankWrBursts::10 134433 # Per bank write bursts +system.physmem.perBankWrBursts::11 138339 # Per bank write bursts +system.physmem.perBankWrBursts::12 136301 # Per bank write bursts +system.physmem.perBankWrBursts::13 138853 # Per bank write bursts +system.physmem.perBankWrBursts::14 135122 # Per bank write bursts +system.physmem.perBankWrBursts::15 134659 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 51323720227500 # Total gap between requests +system.physmem.numWrRetry 21 # Number of times write queue was full causing retry +system.physmem.totGap 51562168447500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1249654 # Read request sizes (log2) +system.physmem.readPktSize::6 2446501 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1073811 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 646219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 339232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 151287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 128129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 812 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2181638 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1276105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 831313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 193469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 160610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 761 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 413 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 120 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,164 +159,161 @@ system.physmem.wrQLenPdf::11 1 # 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What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 938073 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.175418 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.850858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.830774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 348981 37.20% 37.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 217922 23.23% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 89990 9.59% 70.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51985 5.54% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 41514 4.43% 79.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 28050 2.99% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24686 2.63% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20558 2.19% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 114387 12.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 938073 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 129462 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 19.055908 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 183.344638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 129459 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61522 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61522 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.458942 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.948779 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.823778 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 58490 95.07% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 664 1.08% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 448 0.73% 96.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 190 0.31% 97.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 308 0.50% 97.69% # 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Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 35 0.06% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 31 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 129462 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 129462 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.853911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.595936 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 4.789289 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 125866 97.22% 97.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1229 0.95% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 433 0.33% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 197 0.15% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 330 0.25% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 524 0.40% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 121 0.09% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 23 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 39 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 16 0.01% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 43 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 23 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 425 0.33% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 36 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 42 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 37 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 19 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 35 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 6 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61522 # Writes before turning the bus around for reads -system.physmem.totQLat 31530968444 # Total ticks spent queuing -system.physmem.totMemAccLat 55349205944 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6351530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24821.55 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 129462 # Writes before turning the bus around for reads +system.physmem.totQLat 61876185756 # Total ticks spent queuing +system.physmem.totMemAccLat 108132979506 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 12335145000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25081.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43571.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.56 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43831.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.71 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.31 # Average write queue length when enqueuing -system.physmem.readRowHits 1047361 # Number of row buffer hits during reads -system.physmem.writeRowHits 815697 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.94 # Row buffer hit rate for writes -system.physmem.avgGap 21864788.20 # Average gap between requests -system.physmem.pageHitRate 79.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1828287720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 997577625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4889757600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3480388560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1226219398425 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29718601656750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34308233025720 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.467372 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49439480717043 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713811840000 # Time in different power states +system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing +system.physmem.readRowHits 2056722 # Number of row buffer hits during reads +system.physmem.writeRowHits 1654173 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.81 # Row buffer hit rate for writes +system.physmem.avgGap 11083878.27 # Average gap between requests +system.physmem.pageHitRate 79.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3550765680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1937421750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 9523885800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 7046332560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1313489115900 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29785116936750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34488454558920 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.871313 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49548907375208 # Time in different power states +system.physmem_0.memoryStateTime::REF 1721774080000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 170428636707 # Time in different power states +system.physmem_0.memoryStateTime::ACT 291487862292 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1810756080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 988011750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5018598000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3479837760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1228704019020 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29716422156750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34308639338400 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.475289 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49435820968594 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713811840000 # Time in different power states +system.physmem_1.actEnergy 3541066200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1932129375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 9718893600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 7092645120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1316895447015 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29782128927000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34489099208790 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.883816 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49543906734220 # Time in different power states +system.physmem_1.memoryStateTime::REF 1721774080000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 174088371406 # Time in different power states +system.physmem_1.memoryStateTime::ACT 296486485780 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -340,15 +337,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 225557622 # Number of BP lookups -system.cpu.branchPred.condPredicted 150824960 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12221670 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 159273353 # Number of BTB lookups -system.cpu.branchPred.BTBHits 104130221 # Number of BTB hits +system.cpu.branchPred.lookups 288825634 # Number of BP lookups +system.cpu.branchPred.condPredicted 198097109 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13566789 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 207338959 # Number of BTB lookups +system.cpu.branchPred.BTBHits 136913226 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.378307 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30957399 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 344598 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 66.033526 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37451224 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 402112 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -379,45 +376,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 199616 # Table walker walks requested -system.cpu.checker.dtb.walker.walksLong 199616 # Table walker walks initiated with long descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 199616 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 199616 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 199616 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walks 346524 # Table walker walks requested +system.cpu.checker.dtb.walker.walksLong 346524 # Table walker walks initiated with long descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 346524 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 346524 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 346524 # Table walker wait (enqueue to first request) latency system.cpu.checker.dtb.walker.walksPending::samples 1622408500 # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::0 1622408500 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::total 1622408500 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 155025 91.25% 91.25% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::2M 14865 8.75% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 169890 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 199616 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkPageSizes::4K 271954 90.33% 90.33% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::2M 29125 9.67% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 301079 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 346524 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 199616 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 169890 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 346524 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 301079 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 169890 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 369506 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 301079 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 647603 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 160527490 # DTB read hits -system.cpu.checker.dtb.read_misses 148526 # DTB read misses -system.cpu.checker.dtb.write_hits 145616651 # DTB write hits -system.cpu.checker.dtb.write_misses 51090 # DTB write misses -system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed +system.cpu.checker.dtb.read_hits 204557812 # DTB read hits +system.cpu.checker.dtb.read_misses 253438 # DTB read misses +system.cpu.checker.dtb.write_hits 188384851 # DTB write hits +system.cpu.checker.dtb.write_misses 93086 # DTB write misses +system.cpu.checker.dtb.flush_tlb 22 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 72318 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_tlb_mva_asid 126406 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 87812 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 7517 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 10297 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 19125 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 160676016 # DTB read accesses -system.cpu.checker.dtb.write_accesses 145667741 # DTB write accesses +system.cpu.checker.dtb.perms_faults 24573 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 204811250 # DTB read accesses +system.cpu.checker.dtb.write_accesses 188477937 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 306144141 # DTB hits -system.cpu.checker.dtb.misses 199616 # DTB misses -system.cpu.checker.dtb.accesses 306343757 # DTB accesses +system.cpu.checker.dtb.hits 392942663 # DTB hits +system.cpu.checker.dtb.misses 346524 # DTB misses +system.cpu.checker.dtb.accesses 393289187 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -447,46 +444,46 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.walks 120521 # Table walker walks requested -system.cpu.checker.itb.walker.walksLong 120521 # Table walker walks initiated with long descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 120521 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 120521 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 120521 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walks 130770 # Table walker walks requested +system.cpu.checker.itb.walker.walksLong 130770 # Table walker walks initiated with long descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 130770 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 130770 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 130770 # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walksPending::samples 1621807000 # Table walker pending requests distribution system.cpu.checker.itb.walker.walksPending::0 1621807000 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.itb.walker.walksPending::total 1621807000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 108578 98.83% 98.83% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::2M 1286 1.17% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 109864 # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::4K 116506 98.90% 98.90% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::2M 1293 1.10% 100.00% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 117799 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 120521 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 120521 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 130770 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 130770 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109864 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109864 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 230385 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 853734937 # ITB inst hits -system.cpu.checker.itb.inst_misses 120521 # ITB inst misses +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 117799 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 117799 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 248569 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 1104906556 # ITB inst hits +system.cpu.checker.itb.inst_misses 130770 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed +system.cpu.checker.itb.flush_tlb 22 # Number of times complete TLB was flushed system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 52057 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_tlb_mva_asid 126406 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 60682 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 853855458 # ITB inst accesses -system.cpu.checker.itb.hits 853734937 # DTB hits -system.cpu.checker.itb.misses 120521 # DTB misses -system.cpu.checker.itb.accesses 853855458 # DTB accesses -system.cpu.checker.numCycles 1003246954 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 1105037326 # ITB inst accesses +system.cpu.checker.itb.hits 1104906556 # DTB hits +system.cpu.checker.itb.misses 130770 # DTB misses +system.cpu.checker.itb.accesses 1105037326 # DTB accesses +system.cpu.checker.numCycles 1298799784 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -518,87 +515,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 951838 # Table walker walks requested -system.cpu.dtb.walker.walksLong 951838 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16475 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156308 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 435006 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 516832 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 1986.510123 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 12487.736879 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-32767 508349 98.36% 98.36% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-65535 5443 1.05% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-98303 1244 0.24% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::98304-131071 1085 0.21% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-163839 165 0.03% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::163840-196607 178 0.03% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-229375 121 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::229376-262143 54 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-294911 95 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::294912-327679 7 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-360447 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::360448-393215 38 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-425983 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::425984-458751 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 516832 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 485267 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 21943.293074 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 17562.054008 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15786.896980 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 475094 97.90% 97.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 9290 1.91% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 546 0.11% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 199 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 82 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 20 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 485267 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 776250627376 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.722476 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.519579 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 774163165376 99.73% 99.73% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1120728500 0.14% 99.88% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 435636500 0.06% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 187638500 0.02% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 148036000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 113935000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 26323500 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 52542500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2621500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 776250627376 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 156309 90.46% 90.46% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 16475 9.54% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 172784 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 951838 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 1430156 # Table walker walks requested +system.cpu.dtb.walker.walksLong 1430156 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30793 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273791 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 677378 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 752778 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2375.228819 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 15567.513073 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 746726 99.20% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 4359 0.58% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 685 0.09% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 394 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 311 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 120 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 171 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 752778 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 802636 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 25959.455469 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21570.790504 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 17698.477360 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 783977 97.68% 97.68% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 16023 2.00% 99.67% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1555 0.19% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 316 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 129 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 37 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 22 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 802636 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1044763922448 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.739319 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.520240 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 1040800473448 99.62% 99.62% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 2579873000 0.25% 99.87% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 637994000 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 271834500 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 201274500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 132884500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 46819000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 89469000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 3255500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 45000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1044763922448 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 273792 89.89% 89.89% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 30793 10.11% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 304585 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1430156 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 951838 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 172784 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1430156 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304585 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 172784 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1124622 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304585 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1734741 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 170417440 # DTB read hits -system.cpu.dtb.read_misses 677013 # DTB read misses -system.cpu.dtb.write_hits 148384109 # DTB write hits -system.cpu.dtb.write_misses 274825 # DTB write misses -system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed +system.cpu.dtb.read_hits 217117628 # DTB read hits +system.cpu.dtb.read_misses 1002788 # DTB read misses +system.cpu.dtb.write_hits 192115888 # DTB write hits +system.cpu.dtb.write_misses 427368 # DTB write misses +system.cpu.dtb.flush_tlb 22 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72556 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 126406 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 87986 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10696 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 15675 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 70061 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 171094453 # DTB read accesses -system.cpu.dtb.write_accesses 148658934 # DTB write accesses +system.cpu.dtb.perms_faults 85972 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 218120416 # DTB read accesses +system.cpu.dtb.write_accesses 192543256 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 318801549 # DTB hits -system.cpu.dtb.misses 951838 # DTB misses -system.cpu.dtb.accesses 319753387 # DTB accesses +system.cpu.dtb.hits 409233516 # DTB hits +system.cpu.dtb.misses 1430156 # DTB misses +system.cpu.dtb.accesses 410663672 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -628,877 +622,877 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 162167 # Table walker walks requested -system.cpu.itb.walker.walksLong 162167 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 122178 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17760 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144407 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1087.128740 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 7079.961036 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 143546 99.40% 99.40% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 491 0.34% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 245 0.17% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 86 0.06% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 14 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 177415 # Table walker walks requested +system.cpu.itb.walker.walksLong 177415 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1441 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 130680 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 19804 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 157611 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1499.045117 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 10189.386950 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 155888 98.91% 98.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 579 0.37% 99.27% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 739 0.47% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 292 0.19% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 35 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 38 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 19 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144407 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 141371 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 27408.566821 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23535.121999 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 16611.953111 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 138940 98.28% 98.28% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2106 1.49% 99.77% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 209 0.15% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 62 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 27 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 157611 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 151925 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29463.087050 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24547.770920 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 22228.579404 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 146250 96.26% 96.26% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 4800 3.16% 99.42% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 534 0.35% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 196 0.13% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 80 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 44 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 15 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 141371 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 655988501088 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.936740 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.243710 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 41542191152 6.33% 6.33% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 614402729936 93.66% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 43110500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 467500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walkCompletionTime::total 151925 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 920206753364 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.948994 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.220270 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 46987798652 5.11% 5.11% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 873167595712 94.89% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 50573500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 783500 0.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 655988501088 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 122178 98.84% 98.84% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 123611 # Table walker page sizes translated +system.cpu.itb.walker.walksPending::total 920206753364 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 130680 98.91% 98.91% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1441 1.09% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 132121 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162167 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 162167 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177415 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 177415 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123611 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 123611 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 285778 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 358625455 # ITB inst hits -system.cpu.itb.inst_misses 162167 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 132121 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 132121 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 309536 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 461294711 # ITB inst hits +system.cpu.itb.inst_misses 177415 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb 22 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53363 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 126406 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 62159 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 372145 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 458083 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 358787622 # ITB inst accesses -system.cpu.itb.hits 358625455 # DTB hits -system.cpu.itb.misses 162167 # DTB misses -system.cpu.itb.accesses 358787622 # DTB accesses -system.cpu.numCycles 1590418745 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 461472126 # ITB inst accesses +system.cpu.itb.hits 461294711 # DTB hits +system.cpu.itb.misses 177415 # DTB misses +system.cpu.itb.accesses 461472126 # DTB accesses +system.cpu.numCycles 2141240199 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 646410999 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1006402404 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225557622 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135087620 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 866562323 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26107474 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3678311 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 25439 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9275413 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1023850 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 676 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 358236204 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6112300 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 49056 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1540030748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.765724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.157325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 785638694 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1289733601 # Number of instructions fetch has processed +system.cpu.fetch.Branches 288825634 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174364450 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1267374465 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29210356 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4418623 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 28241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 12152128 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1217886 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 633 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 460817774 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6728045 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 53516 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2085435848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.725171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.139838 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 979927440 63.63% 63.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 215057699 13.96% 77.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70955696 4.61% 82.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 274089913 17.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1366680941 65.53% 65.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 278589155 13.36% 78.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 86788366 4.16% 83.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 353377386 16.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1540030748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.141823 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632791 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 525466953 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 519947088 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 434864784 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 50506307 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9245616 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33796734 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3867997 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1090931528 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29050280 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9245616 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 570424085 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50840114 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 363017689 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 440398811 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 106104433 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1071115355 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6801917 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5040663 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 343395 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 645255 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 54344412 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20434 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1018974666 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1651092433 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1266893179 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1473696 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 953236782 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65737881 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27206823 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23528426 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 103688094 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 174464093 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 151959443 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9931077 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9032567 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1035787653 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27506074 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1051526043 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3293799 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60619533 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33780075 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 314140 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1540030748 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.682795 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.925415 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 2085435848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.134887 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.602330 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 612239538 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 852574124 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 529946172 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80118083 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10557931 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41219534 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4107385 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1403247413 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32566835 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10557931 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 674962554 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 85247440 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 550746700 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 547461697 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 216459526 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1379612307 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 7971383 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7360618 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 963827 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1074082 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 133209723 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 22971 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1329803577 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2195861380 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1637517470 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1437183 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1251935276 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 77868298 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 43546894 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39087703 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 166786807 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 221659276 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 196613901 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12565776 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11015266 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1326936815 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 43849103 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1356961205 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4098709 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 72699747 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41430931 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 372473 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2085435848 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.650685 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.914510 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 888949202 57.72% 57.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 336251490 21.83% 79.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 235798342 15.31% 94.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72468185 4.71% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6544331 0.42% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19198 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1239320860 59.43% 59.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 449936886 21.58% 81.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 291017288 13.95% 94.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 95682212 4.59% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9449903 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 28699 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1540030748 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2085435848 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 58035888 35.01% 35.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 99674 0.06% 35.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26738 0.02% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 574 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44566242 26.88% 61.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63041416 38.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 73477453 34.17% 34.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90486 0.04% 34.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26768 0.01% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 385 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 57876005 26.91% 61.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 83594438 38.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 724142674 68.87% 68.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2543730 0.24% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122779 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 376 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 121012 0.01% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 174312709 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 150282706 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 937288786 69.07% 69.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2936989 0.22% 69.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 129444 0.01% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 114407 0.01% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 221949724 16.36% 85.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194541406 14.34% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1051526043 # Type of FU issued -system.cpu.iq.rate 0.661163 # Inst issue rate -system.cpu.iq.fu_busy_cnt 165770532 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157648 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3809671307 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1123107931 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1033541701 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2475857 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 947397 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 910004 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1215741366 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1555198 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4333965 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1356961205 # Type of FU issued +system.cpu.iq.rate 0.633727 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215065535 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.158491 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5016097714 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1442740685 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1335189379 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2424787 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 927446 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 888349 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1570502436 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1524273 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5709357 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13839303 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14833 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143349 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6338712 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 16902439 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24350 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 184211 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8196884 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2540349 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1552925 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3577769 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1870440 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9245616 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6389360 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5797347 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1063516239 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 10557931 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12374030 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7706525 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1371058602 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 174464093 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 151959443 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23100216 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 59008 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5663632 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143349 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3667729 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5111764 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8779493 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1040328227 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 170406440 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10257681 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 221659276 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 196613901 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 38550114 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 178028 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7343410 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 184211 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4239042 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5703306 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 9942348 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1343677933 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 217120223 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11882036 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222512 # number of nop insts executed -system.cpu.iew.exec_refs 318786335 # number of memory reference insts executed -system.cpu.iew.exec_branches 197400349 # Number of branches executed -system.cpu.iew.exec_stores 148379895 # Number of stores executed -system.cpu.iew.exec_rate 0.654122 # Inst execution rate -system.cpu.iew.wb_sent 1035262700 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1034451705 # cumulative count of insts written-back -system.cpu.iew.wb_producers 440415620 # num instructions producing a value -system.cpu.iew.wb_consumers 712619707 # num instructions consuming a value +system.cpu.iew.exec_nop 272684 # number of nop insts executed +system.cpu.iew.exec_refs 409245203 # number of memory reference insts executed +system.cpu.iew.exec_branches 255119365 # Number of branches executed +system.cpu.iew.exec_stores 192124980 # Number of stores executed +system.cpu.iew.exec_rate 0.627523 # Inst execution rate +system.cpu.iew.wb_sent 1337102879 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1336077728 # cumulative count of insts written-back +system.cpu.iew.wb_producers 573421420 # num instructions producing a value +system.cpu.iew.wb_consumers 940568778 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.650427 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618023 # average fanout of values written-back +system.cpu.iew.wb_rate 0.623974 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.609654 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 51498978 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 27191934 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8413549 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1528028900 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.656188 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.286676 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 62140410 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 43476630 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9519542 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2071346493 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.626687 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.267080 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1013092181 66.30% 66.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 289858237 18.97% 85.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 121052617 7.92% 93.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36682667 2.40% 95.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28563883 1.87% 97.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14105791 0.92% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8655946 0.57% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4198069 0.27% 99.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11819509 0.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1395640231 67.38% 67.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 393909449 19.02% 86.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 150461425 7.26% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44316735 2.14% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35977476 1.74% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18232281 0.88% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10892931 0.53% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5452952 0.26% 99.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16463013 0.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1528028900 # Number of insts commited each cycle -system.cpu.commit.committedInsts 853325819 # Number of instructions committed -system.cpu.commit.committedOps 1002674190 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 2071346493 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1104366834 # Number of instructions committed +system.cpu.commit.committedOps 1298086167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 306245520 # Number of memory references committed -system.cpu.commit.loads 160624789 # Number of loads committed -system.cpu.commit.membars 6977905 # Number of memory barriers committed -system.cpu.commit.branches 190474151 # Number of branches committed -system.cpu.commit.fp_insts 896785 # Number of committed floating point instructions. -system.cpu.commit.int_insts 921116747 # Number of committed integer instructions. -system.cpu.commit.function_calls 25400785 # Number of function calls committed. +system.cpu.commit.refs 393173853 # Number of memory references committed +system.cpu.commit.loads 204756836 # Number of loads committed +system.cpu.commit.membars 9104821 # Number of memory barriers committed +system.cpu.commit.branches 246834909 # Number of branches committed +system.cpu.commit.fp_insts 874964 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1186447841 # Number of committed integer instructions. +system.cpu.commit.function_calls 30876862 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 694059947 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2158876 0.22% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98131 0.01% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111674 0.01% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 160624789 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 145620731 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 902159630 69.50% 69.50% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2542825 0.20% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 103949 0.01% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 105868 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 204756836 15.77% 85.49% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 188417017 14.51% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1002674190 # Class of committed instruction -system.cpu.commit.bw_lim_events 11819509 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2562796067 # The number of ROB reads -system.cpu.rob.rob_writes 2120254358 # The number of ROB writes -system.cpu.timesIdled 8129447 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50387997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101057024238 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 853325819 # Number of Instructions Simulated -system.cpu.committedOps 1002674190 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.863788 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.863788 # CPI: Total CPI of All Threads -system.cpu.ipc 0.536542 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.536542 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1231590969 # number of integer regfile reads -system.cpu.int_regfile_writes 735370650 # number of integer regfile writes -system.cpu.fp_regfile_reads 1462122 # number of floating regfile reads -system.cpu.fp_regfile_writes 782688 # number of floating regfile writes -system.cpu.cc_regfile_reads 226859046 # number of cc regfile reads -system.cpu.cc_regfile_writes 227515194 # number of cc regfile writes -system.cpu.misc_regfile_reads 2534481060 # number of misc regfile reads -system.cpu.misc_regfile_writes 27245755 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9758519 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.983709 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 284707567 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9759031 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.173754 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 1298086167 # Class of committed instruction +system.cpu.commit.bw_lim_events 16463013 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3405665880 # The number of ROB reads +system.cpu.rob.rob_writes 2734432791 # The number of ROB writes +system.cpu.timesIdled 9009507 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 55804351 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100983102115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1104366834 # Number of Instructions Simulated +system.cpu.committedOps 1298086167 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.938885 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.938885 # CPI: Total CPI of All Threads +system.cpu.ipc 0.515760 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.515760 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1596434625 # number of integer regfile reads +system.cpu.int_regfile_writes 940526506 # number of integer regfile writes +system.cpu.fp_regfile_reads 1424965 # number of floating regfile reads +system.cpu.fp_regfile_writes 765828 # number of floating regfile writes +system.cpu.cc_regfile_reads 311708448 # number of cc regfile reads +system.cpu.cc_regfile_writes 312593649 # number of cc regfile writes +system.cpu.misc_regfile_reads 3410532874 # number of misc regfile reads +system.cpu.misc_regfile_writes 44362921 # number of misc regfile writes +system.cpu.dcache.tags.replacements 13614186 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.983787 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 360288791 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 13614698 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.463223 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1642601500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.983709 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.983787 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1243872376 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1243872376 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 147964440 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147964440 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128940955 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128940955 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 380183 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 380183 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 324678 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 324678 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3327415 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3327415 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3725844 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3725844 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 276905395 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 276905395 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 277285578 # number of overall hits -system.cpu.dcache.overall_hits::total 277285578 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9612542 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9612542 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11385353 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11385353 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1184834 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1184834 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1232047 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1232047 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 450033 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 450033 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1595334423 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1595334423 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 186468319 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 186468319 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 162903680 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 162903680 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 463393 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 463393 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 334025 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 334025 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4787397 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4787397 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5271269 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5271269 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 349371999 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 349371999 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 349835392 # number of overall hits +system.cpu.dcache.overall_hits::total 349835392 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12723000 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12723000 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 18625078 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 18625078 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 2035956 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2035956 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1270469 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1270469 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 547335 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 547335 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 20997895 # 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number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 31348078 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 31348078 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 33384034 # number of overall misses +system.cpu.dcache.overall_misses::total 33384034 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 203343916000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 203343916000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 979374659621 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 979374659621 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 74427778402 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 74427778402 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8800618500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 8800618500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 251000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 475536754944 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 475536754944 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 475536754944 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 475536754944 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 157576982 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 157576982 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 140326308 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 140326308 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1565017 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1565017 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1556725 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1556725 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3777448 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3777448 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3725851 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3725851 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 297903290 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 297903290 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 299468307 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 299468307 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061002 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061002 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081135 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081135 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.757074 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.757074 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791435 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.791435 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119137 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119137 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.070486 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.070486 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074074 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074074 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15050.025633 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15050.025633 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29060.825031 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29060.825031 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 51683.009794 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 51683.009794 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14295.584990 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14295.584990 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_latency::cpu.data 1182718575621 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1182718575621 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1182718575621 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1182718575621 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 199191319 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 199191319 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 181528758 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 181528758 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2499349 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2499349 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1604494 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1604494 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5334732 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5334732 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5271276 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5271276 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 380720077 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 380720077 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 383219426 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 383219426 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063873 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.063873 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102601 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.102601 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.814595 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.814595 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791819 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.791819 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102598 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102598 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.082339 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082339 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087115 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087115 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15982.387487 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15982.387487 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52583.654126 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52583.654126 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 58582.915759 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 58582.915759 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16079.034778 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16079.034778 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35857.142857 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35857.142857 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22646.877458 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22646.877458 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21437.252150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21437.252150 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 35158879 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37728.583412 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37728.583412 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35427.671072 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35427.671072 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 46020939 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1606955 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2096301 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.879193 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.953402 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7549082 # number of writebacks -system.cpu.dcache.writebacks::total 7549082 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4467834 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4467834 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9360902 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9360902 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7079 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 7079 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219205 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 219205 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13828736 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13828736 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13828736 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13828736 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5144708 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5144708 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2024451 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2024451 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1178103 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1178103 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1224968 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1224968 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230828 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 230828 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 10299062 # number of writebacks +system.cpu.dcache.writebacks::total 10299062 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5706012 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5706012 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15543150 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15543150 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7171 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 7171 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 263403 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 263403 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 21249162 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21249162 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21249162 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21249162 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7016988 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7016988 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3081928 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3081928 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2029224 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2029224 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263298 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1263298 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283932 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 283932 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7169159 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7169159 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8347262 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8347262 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75818409500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75818409500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57062160713 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57062160713 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20148080000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20148080000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 62191648168 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 62191648168 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3063087000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3063087000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 10098916 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 10098916 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 12128140 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 12128140 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109410315500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109410315500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 144646896672 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 144646896672 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32373018500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32373018500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72874671402 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72874671402 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4076865500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4076865500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 244000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 244000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 132880570213 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 132880570213 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 153028650213 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 153028650213 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5828327500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5828327500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5707957967 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5707957967 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11536285467 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11536285467 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032649 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032649 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014427 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014427 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.752773 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.752773 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786888 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786888 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061107 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061107 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024065 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024065 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027874 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027874 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14737.164772 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14737.164772 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.486466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.486466 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17102.137929 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17102.137929 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 50770.018619 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 50770.018619 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13269.997574 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13269.997574 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 254057212172 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 254057212172 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286430230672 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 286430230672 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829096500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829096500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5708243467 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5708243467 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11537339967 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11537339967 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035227 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035227 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016978 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016978 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.811901 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.811901 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787350 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787350 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053223 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053223 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026526 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026526 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031648 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031648 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15592.205017 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15592.205017 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46933.898739 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46933.898739 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15953.398196 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.398196 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 57686.049849 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 57686.049849 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14358.598185 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14358.598185 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18535.029034 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18535.029034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18332.795857 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18332.795857 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173060.380664 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173060.380664 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169395.713646 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169395.713646 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171227.557619 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171227.557619 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25156.879429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25156.879429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23616.995737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23616.995737 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173011.293482 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.293482 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169369.001780 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169369.001780 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171189.850389 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171189.850389 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 15042093 # number of replacements -system.cpu.icache.tags.tagsinuse 511.944879 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 342405629 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15042605 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.762389 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 16756542 # number of replacements +system.cpu.icache.tags.tagsinuse 511.945135 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 443237235 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16757054 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26.450785 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 17214303500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.944879 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999892 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 511.945135 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999893 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 373257734 # Number of tag accesses -system.cpu.icache.tags.data_accesses 373257734 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 342405629 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 342405629 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 342405629 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 342405629 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 342405629 # number of overall hits -system.cpu.icache.overall_hits::total 342405629 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15809279 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15809279 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15809279 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15809279 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15809279 # number of overall misses -system.cpu.icache.overall_misses::total 15809279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 208403044384 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 208403044384 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 208403044384 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 208403044384 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 208403044384 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 208403044384 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 358214908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 358214908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 358214908 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 358214908 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 358214908 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 358214908 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 460796476 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 460796476 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 460796476 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 460796476 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038106 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.038106 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.038106 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.038106 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.038106 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.038106 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13220.446937 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13220.446937 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13220.446937 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13220.446937 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 15959 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1210 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1225 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 12.421488 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.027755 # 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number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15042826 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15042826 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15042826 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 801966 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 801966 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 801966 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 801966 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 801966 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 801966 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16757275 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16757275 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16757275 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16757275 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16757275 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16757275 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186915451392 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 186915451392 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186915451392 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 186915451392 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186915451392 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 186915451392 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208567956898 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 208567956898 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208567956898 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 208567956898 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208567956898 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 208567956898 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1594412000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1594412000 # 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average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12425.554307 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12425.554307 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12425.554307 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12425.554307 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036366 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.036366 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.036366 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12446.412492 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12446.412492 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12446.412492 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12446.412492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74872.599202 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74872.599202 # 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Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37192.962627 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 301.460755 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 460.210435 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7626.713626 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19697.469572 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.567520 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004600 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007022 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.116374 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.300560 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996076 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 380 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61851 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 379 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 530 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2690 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5173 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53395 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005798 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.943771 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 410382726 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 410382726 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 788948 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299798 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1088746 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 7549082 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 7549082 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 9455 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 9455 # number of UpgradeReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 35816.547430 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 265.508156 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 348.644093 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6890.433367 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 21997.104889 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.546517 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004051 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005320 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.105140 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.335649 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996677 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63093 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 240 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 558 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2664 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5217 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54586 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962723 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 506469360 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 506469360 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1313351 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 329734 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1643085 # 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mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785148 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787568 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787568 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005596 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038736 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038736 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.402131 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.402131 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030479 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030479 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78357.038123 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20762.170063 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.170063 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.432327 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.432327 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005869 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045172 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045172 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.467465 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.467465 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060150 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060150 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78619.287068 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20785.158130 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20785.158130 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78334.828345 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78334.828345 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74132.050033 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74132.050033 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78817.042073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78817.042073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 93946.664420 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 93946.664420 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81517.659355 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81517.659355 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74372.135348 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74372.135348 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79230.161201 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79230.161201 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 95693.484177 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 95693.484177 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160560.143120 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122525.039565 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157762.078585 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157762.078585 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160511.085718 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122504.664739 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157735.424146 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157735.424146 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159160.737080 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135915.821764 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159123.028415 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135892.671102 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1633565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23227278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8622904 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 17438576 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 44010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2244083 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28317103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 12480720 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 20347986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 60667 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 44017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1983984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1983984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15042826 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6558947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1331632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1224968 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45167572 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29499463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 732865 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1940611 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 77340511 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 963068272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1029563294 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2422088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6336984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2001390638 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1864369 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 52693428 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.056141 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.230194 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 60674 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3036433 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3036433 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 16757275 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 9323830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1369962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1263298 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50310988 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41099763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 807461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3043712 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 95261924 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1072793136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1449869810 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2707560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10589056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2535959562 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 3104722 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 65657900 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.072586 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.259455 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 49735173 94.39% 94.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2958255 5.61% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 60892075 92.74% 92.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 4765825 7.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 52693428 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 33222815494 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 65657900 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 41856500497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1182000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22592032956 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25164199957 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13487423434 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 19241199390 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 430634727 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 469526277 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1148958035 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1720822991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40295 # Transaction distribution -system.iobus.trans_dist::ReadResp 40295 # Transaction distribution +system.iobus.trans_dist::ReadReq 40298 # Transaction distribution +system.iobus.trans_dist::ReadResp 40298 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1713,11 +1707,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230948 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353738 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1734,11 +1728,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492144 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492168 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1767,71 +1761,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 568813596 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 568892559 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147708000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147714000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115455 # number of replacements -system.iocache.tags.tagsinuse 10.423947 # Cycle average of tags in use +system.iocache.tags.replacements 115458 # number of replacements +system.iocache.tags.tagsinuse 10.449705 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13095311635000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544418 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.879529 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221526 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429971 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651497 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13095311633000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.528028 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.921676 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220502 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432605 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653107 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039623 # Number of tag accesses -system.iocache.tags.data_accesses 1039623 # Number of data accesses +system.iocache.tags.tag_accesses 1039650 # Number of tag accesses +system.iocache.tags.data_accesses 1039650 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8810 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8847 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8810 # number of demand (read+write) misses -system.iocache.demand_misses::total 8850 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses +system.iocache.demand_misses::total 8853 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8810 # number of overall misses -system.iocache.overall_misses::total 8850 # number of overall misses +system.iocache.overall_misses::realview.ide 8813 # number of overall misses +system.iocache.overall_misses::total 8853 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1621911166 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1626980166 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1615020135 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1620089135 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12610487430 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12610487430 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12610143424 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12610143424 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1621911166 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1627331166 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1615020135 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1620440135 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1621911166 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1627331166 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1615020135 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1620440135 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8810 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8847 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8810 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8850 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8810 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8850 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1846,54 +1840,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184098.883768 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183901.906409 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183254.298763 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183060.919209 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.275313 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118226.275313 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118223.050176 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118223.050176 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183879.227797 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183038.533266 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183879.227797 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31681 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183038.533266 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31319 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3345 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.471151 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.276955 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8810 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8847 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8810 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8850 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8810 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8850 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1181411166 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1184630166 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1174370135 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1177589135 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7277287430 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7277287430 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7276943424 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7276943424 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1181411166 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1184831166 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1174370135 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1177790135 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1181411166 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1184831166 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1174370135 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1177790135 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1908,72 +1902,72 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134098.883768 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133901.906409 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133254.298763 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133060.919209 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.275313 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.275313 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68223.050176 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68223.050176 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54973 # Transaction distribution -system.membus.trans_dist::ReadResp 407867 # Transaction distribution -system.membus.trans_dist::WriteReq 33696 # Transaction distribution -system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::Writeback 1073811 # Transaction distribution -system.membus.trans_dist::CleanEvict 187846 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35358 # Transaction distribution +system.membus.trans_dist::ReadReq 54987 # Transaction distribution +system.membus.trans_dist::ReadResp 601962 # Transaction distribution +system.membus.trans_dist::WriteReq 33703 # Transaction distribution +system.membus.trans_dist::WriteResp 33703 # Transaction distribution +system.membus.trans_dist::Writeback 2181638 # Transaction distribution +system.membus.trans_dist::CleanEvict 277040 # Transaction distribution +system.membus.trans_dist::UpgradeReq 48552 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35361 # Transaction distribution -system.membus.trans_dist::ReadExReq 899707 # Transaction distribution -system.membus.trans_dist::ReadExResp 899707 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 352894 # Transaction distribution +system.membus.trans_dist::UpgradeResp 48555 # Transaction distribution +system.membus.trans_dist::ReadExReq 1902507 # Transaction distribution +system.membus.trans_dist::ReadExResp 1902507 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 546975 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3753956 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3883578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4225292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7371150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7500814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341657 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341657 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7842471 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 141818700 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 141988686 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7244096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7244096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 149232782 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2955 # Total snoops (count) -system.membus.snoop_fanout::samples 2747442 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 289319820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 289489890 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7242112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7242112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 296732002 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2989 # Total snoops (count) +system.membus.snoop_fanout::samples 5154600 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2747442 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5154600 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2747442 # Request fanout histogram -system.membus.reqLayer0.occupancy 104159500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5154600 # Request fanout histogram +system.membus.reqLayer0.occupancy 104456000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5443500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5495500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7279924206 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 14230820482 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6776038462 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 13100845399 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228860056 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228852771 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1984,11 +1978,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -2017,17 +2011,17 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16150 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 20008 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |