diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
| commit | c6cede244b431c167ac0213d89ad2bd7a0abbd96 (patch) | |
| tree | fb0e63d4172746d5b1a8edeb859f7ee68cfe13a6 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt | |
| parent | 83a5977481d55916b200740cf03748a20777bdf1 (diff) | |
| download | gem5-c6cede244b431c167ac0213d89ad2bd7a0abbd96.tar.xz | |
stats: Update stats to reflect changes to cache and crossbar
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt | 6513 |
1 files changed, 3257 insertions, 3256 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 5e9f9ee14..6b53e6579 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.393981 # Number of seconds simulated -sim_ticks 47393980707000 # Number of ticks simulated -final_tick 47393980707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.354243 # Number of seconds simulated +sim_ticks 47354242877000 # Number of ticks simulated +final_tick 47354242877000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118826 # Simulator instruction rate (inst/s) -host_op_rate 139727 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6107626980 # Simulator tick rate (ticks/s) -host_mem_usage 769604 # Number of bytes of host memory used -host_seconds 7759.80 # Real time elapsed on the host -sim_insts 922064003 # Number of instructions simulated -sim_ops 1084251192 # Number of ops (including micro ops) simulated +host_inst_rate 195342 # Simulator instruction rate (inst/s) +host_op_rate 229691 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10034841905 # Simulator tick rate (ticks/s) +host_mem_usage 778832 # Number of bytes of host memory used +host_seconds 4718.98 # Real time elapsed on the host +sim_insts 921815819 # Number of instructions simulated +sim_ops 1083910027 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 150400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 142336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4326432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 44486728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 20365824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 171008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 152256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3129632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 15575440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 14887232 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428800 # Number of bytes read from this memory -system.physmem.bytes_read::total 103816088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4326432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3129632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7456064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 86117376 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 202368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 196224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4450144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 45350984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 22283904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 113792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 85504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2862048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 13865872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12452160 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 439808 # Number of bytes read from this memory +system.physmem.bytes_read::total 102302808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4450144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2862048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7312192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 85371072 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 86137960 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2350 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2224 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 83553 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 695118 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 318216 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2672 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2379 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 48944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 243379 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 232613 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6700 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1638148 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1345584 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 85391656 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3162 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3066 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 85486 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 708622 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 348186 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1778 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1336 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44763 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 216667 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 194565 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6872 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1614503 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1333923 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1348158 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 91287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 938658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 429713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3608 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 66034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 328638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 314117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9048 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2190491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 91287 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 66034 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 157321 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1817053 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1336497 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 93976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 957696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 470579 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1806 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 60439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 292812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 262958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2160373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 93976 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 60439 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 154415 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1802818 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1817487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1817053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 91287 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 939092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 429713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3608 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 66034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 328638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 314117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4007978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1638148 # Number of read requests accepted -system.physmem.writeReqs 1348158 # Number of write requests accepted -system.physmem.readBursts 1638148 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1348158 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 104808896 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 32576 # Total number of bytes read from write queue -system.physmem.bytesWritten 86137280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 103816088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 86137960 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 509 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1803252 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1802818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 93976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 958131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 470579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 60439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 292812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 262958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3963625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1614503 # Number of read requests accepted +system.physmem.writeReqs 1336497 # Number of write requests accepted +system.physmem.readBursts 1614503 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1336497 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 103293760 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 34432 # Total number of bytes read from write queue +system.physmem.bytesWritten 85390720 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 102302808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 85391656 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 538 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 529318 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 98506 # Per bank write bursts -system.physmem.perBankRdBursts::1 102125 # Per bank write bursts -system.physmem.perBankRdBursts::2 96514 # Per bank write bursts -system.physmem.perBankRdBursts::3 101212 # Per bank write bursts -system.physmem.perBankRdBursts::4 98283 # Per bank write bursts -system.physmem.perBankRdBursts::5 109978 # Per bank write bursts -system.physmem.perBankRdBursts::6 106703 # Per bank write bursts -system.physmem.perBankRdBursts::7 105175 # Per bank write bursts -system.physmem.perBankRdBursts::8 93813 # Per bank write bursts -system.physmem.perBankRdBursts::9 120186 # Per bank write bursts -system.physmem.perBankRdBursts::10 99379 # Per bank write bursts -system.physmem.perBankRdBursts::11 109206 # Per bank write bursts -system.physmem.perBankRdBursts::12 97639 # Per bank write bursts -system.physmem.perBankRdBursts::13 103304 # Per bank write bursts -system.physmem.perBankRdBursts::14 94884 # Per bank write bursts -system.physmem.perBankRdBursts::15 100732 # Per bank write bursts -system.physmem.perBankWrBursts::0 82092 # Per bank write bursts -system.physmem.perBankWrBursts::1 86582 # Per bank write bursts -system.physmem.perBankWrBursts::2 80748 # Per bank write bursts -system.physmem.perBankWrBursts::3 83407 # Per bank write bursts -system.physmem.perBankWrBursts::4 81928 # Per bank write bursts -system.physmem.perBankWrBursts::5 88947 # Per bank write bursts -system.physmem.perBankWrBursts::6 86848 # Per bank write bursts -system.physmem.perBankWrBursts::7 87370 # Per bank write bursts -system.physmem.perBankWrBursts::8 79257 # Per bank write bursts -system.physmem.perBankWrBursts::9 83439 # Per bank write bursts -system.physmem.perBankWrBursts::10 82066 # Per bank write bursts -system.physmem.perBankWrBursts::11 89206 # Per bank write bursts -system.physmem.perBankWrBursts::12 82040 # Per bank write bursts -system.physmem.perBankWrBursts::13 87648 # Per bank write bursts -system.physmem.perBankWrBursts::14 80198 # Per bank write bursts -system.physmem.perBankWrBursts::15 84119 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 97103 # Per bank write bursts +system.physmem.perBankRdBursts::1 99552 # Per bank write bursts +system.physmem.perBankRdBursts::2 98906 # Per bank write bursts +system.physmem.perBankRdBursts::3 103577 # Per bank write bursts +system.physmem.perBankRdBursts::4 99773 # Per bank write bursts +system.physmem.perBankRdBursts::5 105983 # Per bank write bursts +system.physmem.perBankRdBursts::6 104785 # Per bank write bursts +system.physmem.perBankRdBursts::7 101396 # Per bank write bursts +system.physmem.perBankRdBursts::8 95400 # Per bank write bursts +system.physmem.perBankRdBursts::9 122614 # Per bank write bursts +system.physmem.perBankRdBursts::10 95999 # Per bank write bursts +system.physmem.perBankRdBursts::11 101585 # Per bank write bursts +system.physmem.perBankRdBursts::12 99838 # Per bank write bursts +system.physmem.perBankRdBursts::13 98462 # Per bank write bursts +system.physmem.perBankRdBursts::14 93633 # Per bank write bursts +system.physmem.perBankRdBursts::15 95359 # Per bank write bursts +system.physmem.perBankWrBursts::0 80772 # Per bank write bursts +system.physmem.perBankWrBursts::1 85062 # Per bank write bursts +system.physmem.perBankWrBursts::2 82679 # Per bank write bursts +system.physmem.perBankWrBursts::3 85393 # Per bank write bursts +system.physmem.perBankWrBursts::4 84018 # Per bank write bursts +system.physmem.perBankWrBursts::5 87943 # Per bank write bursts +system.physmem.perBankWrBursts::6 87092 # Per bank write bursts +system.physmem.perBankWrBursts::7 86427 # Per bank write bursts +system.physmem.perBankWrBursts::8 80096 # Per bank write bursts +system.physmem.perBankWrBursts::9 84617 # Per bank write bursts +system.physmem.perBankWrBursts::10 79653 # Per bank write bursts +system.physmem.perBankWrBursts::11 85236 # Per bank write bursts +system.physmem.perBankWrBursts::12 82895 # Per bank write bursts +system.physmem.perBankWrBursts::13 82853 # Per bank write bursts +system.physmem.perBankWrBursts::14 78695 # Per bank write bursts +system.physmem.perBankWrBursts::15 80799 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 13 # Number of times write queue was full causing retry -system.physmem.totGap 47393979099500 # Total gap between requests +system.physmem.numWrRetry 46 # Number of times write queue was full causing retry +system.physmem.totGap 47354241269500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1616790 # Read request sizes (log2) +system.physmem.readPktSize::6 1593145 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1345584 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 619728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 417888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 167778 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 159876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 99605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 61553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 7798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1333923 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 609512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 408742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 165543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 158385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 99064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 61330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30716 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 869 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -188,163 +188,166 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 36742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 54132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 72218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 78252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 84742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 88110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 91290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 97437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 95426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 99220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 110773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 98211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 87853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 81636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 35 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1054994 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 180.992301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 111.466356 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 240.522304 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 655278 62.11% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 195680 18.55% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 62552 5.93% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34743 3.29% 89.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24726 2.34% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13789 1.31% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13873 1.31% 94.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7523 0.71% 95.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 46830 4.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1054994 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 76193 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.493169 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 249.861284 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 76190 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 21385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 25204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 37704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 53566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 68935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 76299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 82207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 85573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 89148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 94653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 94373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 98828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 112387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 98640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 87955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 82141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 109 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1039142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 181.576816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 111.689088 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.244363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 644376 62.01% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 193180 18.59% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 61698 5.94% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 33929 3.27% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24382 2.35% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13748 1.32% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13846 1.33% 94.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7628 0.73% 95.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 46355 4.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1039142 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 75311 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.430349 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 250.668355 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 75308 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 76193 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 76193 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.664287 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.191501 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.434084 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 70631 92.70% 92.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 3142 4.12% 96.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 485 0.64% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 323 0.42% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 79 0.10% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 306 0.40% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 178 0.23% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 116 0.15% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 95 0.12% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 99 0.13% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 41 0.05% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 55 0.07% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 407 0.53% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 35 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 33 0.04% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 86 0.11% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 20 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 6 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 76193 # Writes before turning the bus around for reads -system.physmem.totQLat 70239099561 # Total ticks spent queuing -system.physmem.totMemAccLat 100944830811 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8188195000 # Total ticks spent in databus transfers -system.physmem.avgQLat 42890.47 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 75311 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 75311 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.716270 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.189166 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.091364 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 70052 93.02% 93.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 3029 4.02% 97.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 423 0.56% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 178 0.24% 97.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 138 0.18% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 118 0.16% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 205 0.27% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 81 0.11% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 292 0.39% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 59 0.08% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 23 0.03% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 57 0.08% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 240 0.32% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 44 0.06% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 27 0.04% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 108 0.14% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 169 0.22% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 75311 # Writes before turning the bus around for reads +system.physmem.totQLat 70116127057 # Total ticks spent queuing +system.physmem.totMemAccLat 100377970807 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8069825000 # Total ticks spent in databus transfers +system.physmem.avgQLat 43443.40 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 61640.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.21 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.82 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 62193.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing -system.physmem.readRowHits 1316973 # Number of row buffer hits during reads -system.physmem.writeRowHits 611565 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 45.44 # Row buffer hit rate for writes -system.physmem.avgGap 15870436.28 # Average gap between requests -system.physmem.pageHitRate 64.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4035157560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2201722875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6384222000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4392934560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3095544201360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1182732038730 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27398902223250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31694192500335 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.738819 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45580299815708 # Time in different power states -system.physmem_0.memoryStateTime::REF 1582589060000 # Time in different power states +system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.55 # Average write queue length when enqueuing +system.physmem.readRowHits 1298803 # Number of row buffer hits during reads +system.physmem.writeRowHits 610248 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 45.74 # Row buffer hit rate for writes +system.physmem.avgGap 16046845.57 # Average gap between requests +system.physmem.pageHitRate 64.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4027930200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2197779375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6326346000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4402421280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3092948511120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1180978829595 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27376595514000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31667477331570 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.735888 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45543196260914 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581262020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 231091139792 # Time in different power states +system.physmem_0.memoryStateTime::ACT 229783905086 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3940597080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2150127375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6389315400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4328465040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3095544201360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1183329754695 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27398377902750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31694060363700 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.736031 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45579400276584 # Time in different power states -system.physmem_1.memoryStateTime::REF 1582589060000 # Time in different power states +system.physmem_1.actEnergy 3827983320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2088681375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6262534200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4243389120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3092948511120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1177720349355 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27379453830000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31666545278490 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.716205 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45547950580913 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581262020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 231988109666 # Time in different power states +system.physmem_1.memoryStateTime::ACT 225030017087 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -378,15 +381,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 135522453 # Number of BP lookups -system.cpu0.branchPred.condPredicted 89756354 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6696164 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 95487916 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 63232655 # Number of BTB hits +system.cpu0.branchPred.lookups 149665852 # Number of BP lookups +system.cpu0.branchPred.condPredicted 99294558 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7394871 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 104737280 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 69525721 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.220583 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 18624977 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 201233 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.381064 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20507496 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 218312 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -417,85 +420,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 590400 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 590400 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12973 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94460 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 278631 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 311769 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2427.181663 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 14785.327659 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 309280 99.20% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1331 0.43% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 885 0.28% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 124 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 48 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 73 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 311769 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 310891 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 20766.069137 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17798.694444 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 20375.668326 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 307651 98.96% 98.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 747 0.24% 99.20% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1834 0.59% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 107 0.03% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 307 0.10% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 102 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 75 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 634428 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 634428 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 14162 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 100318 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 297022 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 337406 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2383.727616 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14932.270093 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 334700 99.20% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1380 0.41% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 1061 0.31% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 114 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 46 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 68 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 337406 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 331422 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 21257.229454 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17843.462773 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 23121.353715 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 326855 98.62% 98.62% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1016 0.31% 98.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2453 0.74% 99.67% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 165 0.05% 99.72% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 627 0.19% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 136 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 104 0.03% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 36 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 21 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 310891 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 523001837252 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.567345 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.551290 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 521647732752 99.74% 99.74% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 761373500 0.15% 99.89% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 275460500 0.05% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 125915000 0.02% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 99351000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 52861000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 16652500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 21714500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 741500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 35000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 523001837252 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 94460 87.92% 87.92% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 12973 12.08% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 107433 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 590400 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 24 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 331422 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 582048251060 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.606269 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.543146 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 580572178560 99.75% 99.75% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 833055500 0.14% 99.89% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 305294500 0.05% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 135391000 0.02% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 101845000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 57765000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 18306500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 23753000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 653000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 582048251060 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 100318 87.63% 87.63% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 14162 12.37% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 114480 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 634428 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 590400 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107433 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 634428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 114480 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107433 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 697833 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 114480 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 748908 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 98363253 # DTB read hits -system.cpu0.dtb.read_misses 426453 # DTB read misses -system.cpu0.dtb.write_hits 80524387 # DTB write hits -system.cpu0.dtb.write_misses 163947 # DTB write misses +system.cpu0.dtb.read_hits 109416332 # DTB read hits +system.cpu0.dtb.read_misses 460008 # DTB read misses +system.cpu0.dtb.write_hits 89314742 # DTB write hits +system.cpu0.dtb.write_misses 174420 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 40807 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 204 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7493 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 43796 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 708 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7923 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 42725 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 98789706 # DTB read accesses -system.cpu0.dtb.write_accesses 80688334 # DTB write accesses +system.cpu0.dtb.perms_faults 42753 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 109876340 # DTB read accesses +system.cpu0.dtb.write_accesses 89489162 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 178887640 # DTB hits -system.cpu0.dtb.misses 590400 # DTB misses -system.cpu0.dtb.accesses 179478040 # DTB accesses +system.cpu0.dtb.hits 198731074 # DTB hits +system.cpu0.dtb.misses 634428 # DTB misses +system.cpu0.dtb.accesses 199365502 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -525,1170 +529,1175 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 85262 # Table walker walks requested -system.cpu0.itb.walker.walksLong 85262 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1098 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61891 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 9791 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 75471 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1466.000186 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 11351.229924 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-65535 75137 99.56% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-131071 79 0.10% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-196607 235 0.31% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-262143 9 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 91298 # Table walker walks requested +system.cpu0.itb.walker.walksLong 91298 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1125 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 66671 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10542 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 80756 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1599.144336 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 12482.430449 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-65535 80336 99.48% 99.48% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-131071 92 0.11% 99.59% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-196607 294 0.36% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-262143 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-327679 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 75471 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 72780 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26660.353119 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23025.074927 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 26139.582838 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 71045 97.62% 97.62% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 123 0.17% 97.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1365 1.88% 99.66% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.13% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 88 0.12% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 30 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 31 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 80756 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 78338 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 27568.581021 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23319.178868 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 29698.501423 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 76052 97.08% 97.08% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 130 0.17% 97.25% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 1833 2.34% 99.59% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 110 0.14% 99.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 108 0.14% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 41 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 39 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 15 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 72780 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 389854695076 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.839132 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.367626 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 62743884640 16.09% 16.09% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 327084697936 83.90% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 23698000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 2390500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 24000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 389854695076 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 61891 98.26% 98.26% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1098 1.74% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 62989 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::917504-983039 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 78338 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 423131286608 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.845297 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.361834 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 65489609660 15.48% 15.48% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 357613926448 84.52% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 25558000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 2033000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 159500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 423131286608 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 66671 98.34% 98.34% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1125 1.66% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 67796 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85262 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85262 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 91298 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 91298 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 62989 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 62989 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 148251 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 213975614 # ITB inst hits -system.cpu0.itb.inst_misses 85262 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 67796 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 67796 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 159094 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 236080263 # ITB inst hits +system.cpu0.itb.inst_misses 91298 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 29309 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 31862 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 214464 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 229508 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 214060876 # ITB inst accesses -system.cpu0.itb.hits 213975614 # DTB hits -system.cpu0.itb.misses 85262 # DTB misses -system.cpu0.itb.accesses 214060876 # DTB accesses -system.cpu0.numCycles 807659312 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 236171561 # ITB inst accesses +system.cpu0.itb.hits 236080263 # DTB hits +system.cpu0.itb.misses 91298 # DTB misses +system.cpu0.itb.accesses 236171561 # DTB accesses +system.cpu0.numCycles 875332831 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 88233839 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 599476727 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 135522453 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81857632 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 670713114 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14447630 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2036483 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 334818 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6261942 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 813783 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 863786 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 213760838 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1698349 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 28412 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 776481580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.903685 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.199979 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 98502478 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 662547160 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 149665852 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 90033217 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 725278481 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15926346 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2210942 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 343253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6644206 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 843353 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 921483 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 235849038 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1874950 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 30072 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 842707369 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.920891 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.205357 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 440207018 56.69% 56.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 130689201 16.83% 73.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 45750499 5.89% 79.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 159834862 20.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 471086256 55.90% 55.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 144263495 17.12% 73.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 50294842 5.97% 78.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 177062776 21.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 776481580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.167797 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.742240 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 105533428 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 405339788 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 223093644 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 37388098 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5126622 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19615970 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2136984 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 619581339 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23102207 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5126622 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 140592491 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 65041706 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 253704898 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 224831888 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 87183975 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 602582059 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 5894427 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 10859505 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 384608 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 879717 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 52095352 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 10977 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 576174683 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 933371731 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 711261087 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 684793 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 519247735 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 56926942 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15518812 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13493208 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 75428854 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 98376014 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 83834868 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 8883598 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 7640207 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 580665271 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15522553 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 585221400 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2674583 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 53398017 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 34936380 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 261009 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 776481580 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.753684 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.045500 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 842707369 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.170982 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.756909 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 117017992 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 431286061 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 248304840 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 40439583 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5658893 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 21552813 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2348874 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 685973615 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 25548756 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5658893 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 155339909 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 68898576 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 270709645 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 249775497 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 92324849 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 667175567 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6553348 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 11928405 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 414386 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 932685 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 54388046 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11955 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 637281036 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1029527825 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 787757309 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 900744 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 574091859 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 63189171 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16646916 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14438257 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 81666616 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 109512073 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 93001551 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9792967 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8489048 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 643441375 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16650008 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 647817648 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2959555 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 59258512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 38730764 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 299230 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 842707369 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.768734 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.052616 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 456332573 58.77% 58.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 134692381 17.35% 76.12% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 113447710 14.61% 90.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 64406978 8.29% 99.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7597025 0.98% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 4913 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 489695832 58.11% 58.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 146908165 17.43% 75.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 125837037 14.93% 90.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 71836004 8.52% 99.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8424258 1.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 6073 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 776481580 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 842707369 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 60244006 45.44% 45.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 62130 0.05% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 15273 0.01% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 15 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 34917494 26.34% 71.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 37330795 28.16% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 67261039 45.56% 45.56% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 66196 0.04% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 15732 0.01% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 29 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 38768633 26.26% 71.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 41521295 28.12% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 400469737 68.43% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1445270 0.25% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 74848 0.01% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 41036 0.01% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 101401840 17.33% 86.02% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 81788668 13.98% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 442579425 68.32% 68.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1577066 0.24% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 84316 0.01% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 83107 0.01% 68.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.59% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 112773884 17.41% 86.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 90719836 14.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 585221400 # Type of FU issued -system.cpu0.iq.rate 0.724589 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 132569713 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.226529 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2081071755 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 649281804 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 568296572 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1096919 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 437057 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 404655 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 717109128 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 681984 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2687978 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 647817648 # Type of FU issued +system.cpu0.iq.rate 0.740082 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 147632924 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.227893 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2287461115 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 718905040 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 629078745 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1474027 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 598009 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 548346 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 794539840 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 910718 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2963176 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12198109 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 15815 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 133954 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5685458 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13511879 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17808 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 154801 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6318307 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2533664 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4860713 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2892844 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5122180 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5126622 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8215667 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 7173428 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 596307716 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5658893 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8725604 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 7188731 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 660220960 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 98376014 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 83834868 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13216543 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 57072 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 7044703 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 133954 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2031236 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2866413 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4897649 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 577519741 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 98358575 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7118543 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 109512073 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 93001551 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 14147683 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 61387 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 7052032 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 154801 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2237378 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3184169 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5421547 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 639276531 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 109409199 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7914356 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119892 # number of nop insts executed -system.cpu0.iew.exec_refs 178881734 # number of memory reference insts executed -system.cpu0.iew.exec_branches 109041178 # Number of branches executed -system.cpu0.iew.exec_stores 80523159 # Number of stores executed -system.cpu0.iew.exec_rate 0.715054 # Inst execution rate -system.cpu0.iew.wb_sent 569480217 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 568701227 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 276442254 # num instructions producing a value -system.cpu0.iew.wb_consumers 453748356 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.704135 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609241 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 46598328 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15261544 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4598971 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 767596191 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.707129 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.516118 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 129577 # number of nop insts executed +system.cpu0.iew.exec_refs 198721456 # number of memory reference insts executed +system.cpu0.iew.exec_branches 120519027 # Number of branches executed +system.cpu0.iew.exec_stores 89312257 # Number of stores executed +system.cpu0.iew.exec_rate 0.730324 # Inst execution rate +system.cpu0.iew.wb_sent 630467148 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 629627091 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 306648182 # num instructions producing a value +system.cpu0.iew.wb_consumers 503078288 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.719300 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609544 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 51710398 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 16350778 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 5090591 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 832883786 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.721389 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.530255 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 529386438 68.97% 68.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 123369518 16.07% 85.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 53181556 6.93% 91.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 17664925 2.30% 94.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 12675398 1.65% 95.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8710511 1.13% 97.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5748655 0.75% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3557202 0.46% 98.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 13301988 1.73% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 570514920 68.50% 68.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 134700149 16.17% 84.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 59058098 7.09% 91.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 19776256 2.37% 94.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 14036208 1.69% 95.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9662272 1.16% 96.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6431324 0.77% 97.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3992857 0.48% 98.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14711702 1.77% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 767596191 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 462839739 # Number of instructions committed -system.cpu0.commit.committedOps 542789800 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 832883786 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 511876907 # Number of instructions committed +system.cpu0.commit.committedOps 600832864 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 164327314 # Number of memory references committed -system.cpu0.commit.loads 86177904 # Number of loads committed -system.cpu0.commit.membars 3634236 # Number of memory barriers committed -system.cpu0.commit.branches 103555612 # Number of branches committed -system.cpu0.commit.fp_insts 396011 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 497579695 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13818381 # Number of function calls committed. +system.cpu0.commit.refs 182683437 # Number of memory references committed +system.cpu0.commit.loads 96000193 # Number of loads committed +system.cpu0.commit.membars 3986424 # Number of memory barriers committed +system.cpu0.commit.branches 114418082 # Number of branches committed +system.cpu0.commit.fp_insts 535391 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 551244640 # Number of committed integer instructions. +system.cpu0.commit.function_calls 15252520 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 377157891 69.49% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1210852 0.22% 69.71% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 58620 0.01% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 35123 0.01% 69.73% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.73% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.73% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.73% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 86177904 15.88% 85.60% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 78149410 14.40% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 416691372 69.35% 69.35% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1318004 0.22% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 66523 0.01% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 73528 0.01% 69.59% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.59% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.59% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.59% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 96000193 15.98% 85.57% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 86683244 14.43% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 542789800 # Class of committed instruction -system.cpu0.commit.bw_lim_events 13301988 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1339296609 # The number of ROB reads -system.cpu0.rob.rob_writes 1187626415 # The number of ROB writes -system.cpu0.timesIdled 1008617 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 31177732 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93980302134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 462839739 # Number of Instructions Simulated -system.cpu0.committedOps 542789800 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.745009 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.745009 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.573063 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.573063 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 681400785 # number of integer regfile reads -system.cpu0.int_regfile_writes 404691660 # number of integer regfile writes -system.cpu0.fp_regfile_reads 669454 # number of floating regfile reads -system.cpu0.fp_regfile_writes 305508 # number of floating regfile writes -system.cpu0.cc_regfile_reads 127155216 # number of cc regfile reads -system.cpu0.cc_regfile_writes 127713312 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1347757085 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15341922 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6037671 # number of replacements -system.cpu0.dcache.tags.tagsinuse 477.387062 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 152039806 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6038183 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 25.179728 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 600832864 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14711702 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1466105636 # The number of ROB reads +system.cpu0.rob.rob_writes 1314872451 # The number of ROB writes +system.cpu0.timesIdled 1097159 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 32625462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93833152963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 511876907 # Number of Instructions Simulated +system.cpu0.committedOps 600832864 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.710046 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.710046 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.584780 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.584780 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 754446272 # number of integer regfile reads +system.cpu0.int_regfile_writes 448604038 # number of integer regfile writes +system.cpu0.fp_regfile_reads 881646 # number of floating regfile reads +system.cpu0.fp_regfile_writes 476304 # number of floating regfile writes +system.cpu0.cc_regfile_reads 139793568 # number of cc regfile reads +system.cpu0.cc_regfile_writes 140496633 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1470350924 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16456285 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6559473 # number of replacements +system.cpu0.dcache.tags.tagsinuse 490.326221 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 169584910 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6559985 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.851417 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 477.387062 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.932397 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.932397 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.326221 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957668 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.957668 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 341097294 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 341097294 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79771007 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 79771007 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67422867 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 67422867 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213459 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 213459 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 258123 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 258123 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1760749 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1760749 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1785447 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1785447 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 147193874 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 147193874 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147407333 # number of overall hits -system.cpu0.dcache.overall_hits::total 147407333 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6628879 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6628879 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7648651 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7648651 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 727328 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 727328 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823977 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 823977 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 249122 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 249122 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189214 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 189214 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 14277530 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 14277530 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15004858 # number of overall misses -system.cpu0.dcache.overall_misses::total 15004858 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 114348877500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 114348877500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 176760598457 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 176760598457 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 91829921579 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 91829921579 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3934102000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3934102000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5393439500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5393439500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4601000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4601000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 291109475957 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 291109475957 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 291109475957 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 291109475957 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 86399886 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 86399886 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 75071518 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 75071518 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 940787 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 940787 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082100 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1082100 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2009871 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2009871 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1974661 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1974661 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 161471404 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 161471404 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 162412191 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 162412191 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076723 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.076723 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101885 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.101885 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.773106 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.773106 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.761461 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.761461 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.123949 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.123949 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095821 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095821 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.088421 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.088421 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092388 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092388 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17250.107824 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17250.107824 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23110.035803 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23110.035803 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 111447.190369 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 111447.190369 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15791.869044 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15791.869044 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28504.442060 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28504.442060 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 379087602 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 379087602 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 89088742 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 89088742 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75269986 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75269986 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228422 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 228422 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263534 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 263534 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1920078 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1920078 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1972778 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1972778 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 164358728 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 164358728 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 164587150 # number of overall hits +system.cpu0.dcache.overall_hits::total 164587150 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7258058 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7258058 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 8107301 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 8107301 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 768102 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 768102 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 855425 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 855425 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 287297 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 287297 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 193519 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 193519 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 15365359 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 15365359 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 16133461 # number of overall misses +system.cpu0.dcache.overall_misses::total 16133461 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 123043131500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 123043131500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 187154125822 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 187154125822 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 92776135134 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 92776135134 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4545100500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4545100500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5540857500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5540857500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7820000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7820000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 310197257322 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 310197257322 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 310197257322 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 310197257322 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 96346800 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 96346800 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 83377287 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 83377287 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 996524 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 996524 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1118959 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1118959 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2207375 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2207375 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2166297 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2166297 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 179724087 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 179724087 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 180720611 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 180720611 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075333 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.075333 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.097236 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.097236 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770781 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770781 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.764483 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.764483 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130153 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130153 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089332 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089332 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085494 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.085494 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089273 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.089273 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16952.624449 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16952.624449 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23084.640107 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23084.640107 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 108456.188601 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 108456.188601 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15820.215665 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15820.215665 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28632.111059 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28632.111059 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20389.344372 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20389.344372 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19401.015055 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19401.015055 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 28956080 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 26869955 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 763930 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 756063 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.904101 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 35.539307 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20188.090452 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20188.090452 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19226.950579 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19226.950579 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 29213495 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 28830141 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 790800 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 799061 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.941698 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 36.080025 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6037757 # number of writebacks -system.cpu0.dcache.writebacks::total 6037757 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3397304 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3397304 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6149640 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6149640 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4348 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4348 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 126499 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 126499 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9546944 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9546944 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9546944 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9546944 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3231575 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3231575 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1499011 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1499011 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 720499 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 720499 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 819629 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 819629 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122623 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 122623 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189214 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 189214 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4730586 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4730586 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5451085 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5451085 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32157 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32157 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31964 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31964 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64121 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64121 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 51760022500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 51760022500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40775562681 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 40775562681 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18675421500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18675421500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 90765682079 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 90765682079 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1771728000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1771728000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5204285500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5204285500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4541000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4541000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 92535585181 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 92535585181 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 111211006681 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 111211006681 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6175664000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6175664000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6047364000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6047364000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12223028000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12223028000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037403 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037403 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019968 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019968 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765847 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765847 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.757443 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.757443 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061010 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061010 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095821 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095821 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029297 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029297 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033563 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033563 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16016.964638 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16016.964638 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27201.643404 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27201.643404 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25920.121333 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25920.121333 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 110739.959273 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 110739.959273 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14448.578162 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14448.578162 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27504.759162 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27504.759162 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 6559531 # number of writebacks +system.cpu0.dcache.writebacks::total 6559531 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3685333 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3685333 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6510101 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6510101 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4620 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4620 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 146516 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 146516 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 10195434 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 10195434 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 10195434 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 10195434 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3572725 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3572725 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1597200 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1597200 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 761247 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 761247 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 850805 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 850805 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140781 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140781 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 193511 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 193511 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5169925 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5169925 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5931172 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5931172 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32878 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32941 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65819 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65819 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56556979500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56556979500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 42701336905 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 42701336905 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18998780500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18998780500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 91672230134 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 91672230134 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2014552000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2014552000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5347454500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5347454500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 7712000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 7712000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99258316405 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 99258316405 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 118257096905 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 118257096905 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6293183000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6293183000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6230446500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6230446500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12523629500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12523629500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037082 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037082 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019156 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019156 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.763902 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.763902 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760354 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760354 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063778 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063778 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089328 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089328 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028766 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028766 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032820 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032820 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15830.207895 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15830.207895 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26735.122029 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26735.122029 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24957.445481 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24957.445481 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 107747.639158 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 107747.639158 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14309.828741 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14309.828741 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27633.852856 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27633.852856 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19561.125235 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19561.125235 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20401.627691 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20401.627691 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 192047.268091 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192047.268091 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189192.967088 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189192.967088 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190624.413219 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190624.413219 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19199.179177 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19199.179177 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19938.234282 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19938.234282 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191410.152686 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191410.152686 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189139.567712 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189139.567712 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190273.773530 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190273.773530 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5991449 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.937020 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 207384617 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5991961 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.610475 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 21603135000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937020 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 6707377 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.936942 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 228724396 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6707889 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.097821 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 21622819000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.936942 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999877 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 433456796 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 433456796 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 207384617 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 207384617 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 207384617 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 207384617 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 207384617 # number of overall hits -system.cpu0.icache.overall_hits::total 207384617 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6347783 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6347783 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6347783 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6347783 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6347783 # number of overall misses -system.cpu0.icache.overall_misses::total 6347783 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 72771579605 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 72771579605 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 72771579605 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 72771579605 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 72771579605 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 72771579605 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 213732400 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 213732400 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 213732400 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 213732400 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 213732400 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 213732400 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029700 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029700 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029700 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029700 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029700 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029700 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11464.093780 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 11464.093780 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11464.093780 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11464.093780 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11464.093780 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11464.093780 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 11432767 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1960 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 763504 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.974076 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 122.500000 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 478348155 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 478348155 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 228724396 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 228724396 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 228724396 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 228724396 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 228724396 # number of overall hits +system.cpu0.icache.overall_hits::total 228724396 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 7095721 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 7095721 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 7095721 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 7095721 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 7095721 # number of overall misses +system.cpu0.icache.overall_misses::total 7095721 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 79714633751 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 79714633751 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 79714633751 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 79714633751 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 79714633751 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 79714633751 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 235820117 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 235820117 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 235820117 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 235820117 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 235820117 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 235820117 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030090 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.030090 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030090 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.030090 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030090 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.030090 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11234.183778 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11234.183778 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11234.183778 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11234.183778 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11234.183778 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11234.183778 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 12261513 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1787 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 839174 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.611407 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 127.642857 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 5991449 # number of writebacks -system.cpu0.icache.writebacks::total 5991449 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355787 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 355787 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 355787 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 355787 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 355787 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 355787 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5991996 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 5991996 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 5991996 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 5991996 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5991996 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 5991996 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 6707377 # number of writebacks +system.cpu0.icache.writebacks::total 6707377 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 387800 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 387800 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 387800 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 387800 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 387800 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 387800 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6707921 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6707921 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6707921 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6707921 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6707921 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6707921 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 65359568752 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 65359568752 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 65359568752 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 65359568752 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 65359568752 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 65359568752 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 71756007072 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 71756007072 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 71756007072 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 71756007072 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 71756007072 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 71756007072 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028035 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028035 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028035 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028035 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028035 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10907.812481 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10907.812481 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10907.812481 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10907.812481 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10907.812481 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10907.812481 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028445 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028445 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028445 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10697.205151 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10697.205151 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10697.205151 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8312308 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8321741 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 8453 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8921966 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8932201 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 9178 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1049931 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2736768 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15876.012159 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 17362528 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2752871 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.307062 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1125087 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2909208 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16158.656650 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 19404404 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2925253 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.633411 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 3536776000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14917.842100 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 70.317341 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 59.112590 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 828.740128 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.910513 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004292 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003608 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.050582 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.968995 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1213 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14811 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 670 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 342 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 47 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 15221.688116 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.041534 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 63.344722 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000040 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 812.582238 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.929058 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003726 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003866 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.049596 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.986246 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1170 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14800 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 38 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 606 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 338 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1270 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5895 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4592 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2939 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.074036 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.903992 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 412851946 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 412851946 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 601484 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 195644 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 797128 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3986432 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3986432 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 8040621 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 8040621 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 576 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 576 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 912887 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 912887 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5408697 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5408697 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3048347 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 3048347 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 196930 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 196930 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 601484 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 195644 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5408697 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3961234 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10167059 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 601484 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 195644 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5408697 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3961234 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10167059 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12249 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9259 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 21508 # number of ReadReq misses -system.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses -system.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses -system.cpu0.l2cache.WritebackClean_misses::writebacks 3 # number of WritebackClean misses -system.cpu0.l2cache.WritebackClean_misses::total 3 # number of WritebackClean misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 258491 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 258491 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 189208 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 189208 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 336496 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 336496 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 583279 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 583279 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1024126 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1024126 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 620872 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 620872 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12249 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9259 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 583279 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1360622 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1965409 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12249 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9259 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 583279 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1360622 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1965409 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 599464000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 508507000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1107971000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3541175500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 3541175500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2016705000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2016705000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4451000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4451000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 22474975499 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 22474975499 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 23599019498 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 23599019498 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 45762236974 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 45762236974 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 87223622986 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 87223622986 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 599464000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 508507000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23599019498 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 68237212473 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 92944202971 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 599464000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 508507000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23599019498 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 68237212473 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 92944202971 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 613733 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 204903 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 818636 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3986433 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 3986433 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 8040624 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 8040624 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 259067 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 259067 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 189210 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 189210 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1249383 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1249383 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5991976 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 5991976 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4072473 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 4072473 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 817802 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 817802 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 613733 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 204903 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5991976 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5321856 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 12132468 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 613733 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 204903 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5991976 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5321856 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 12132468 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.019958 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.045187 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.026273 # miss rate for ReadReq accesses -system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses -system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1308 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5860 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4512 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3004 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.071411 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.903320 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 454144773 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 454144773 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 651189 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 209837 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 861026 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 4295929 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 4295929 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 8968573 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 8968573 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 805 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 805 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 980855 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 980855 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 6087853 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 6087853 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3397389 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 3397389 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 211269 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 211269 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 651189 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 209837 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 6087853 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 4378244 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 11327123 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 651189 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 209837 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 6087853 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 4378244 # number of overall hits +system.cpu0.l2cache.overall_hits::total 11327123 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13609 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10441 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 24050 # number of ReadReq misses +system.cpu0.l2cache.WritebackDirty_misses::writebacks 4 # number of WritebackDirty misses +system.cpu0.l2cache.WritebackDirty_misses::total 4 # number of WritebackDirty misses +system.cpu0.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses +system.cpu0.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 266523 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 266523 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 193497 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 193497 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 13 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 13 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 359046 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 359046 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 620051 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 620051 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1074980 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1074980 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 637513 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 637513 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13609 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10441 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 620051 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1434026 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2078127 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13609 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10441 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 620051 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1434026 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2078127 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 731180000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 642927000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 1374107000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3539737000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 3539737000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2018375000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2018375000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 7547996 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 7547996 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 23661492999 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 23661492999 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 24792926998 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 24792926998 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 48196505484 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 48196505484 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 87950874488 # number of InvalidateReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::total 87950874488 # number of InvalidateReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 731180000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 642927000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 24792926998 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 71857998483 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 98025032481 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 731180000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 642927000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 24792926998 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 71857998483 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 98025032481 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 664798 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 220278 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 885076 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4295933 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 4295933 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 8968575 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 8968575 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 267328 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 267328 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 193498 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 193498 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 13 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 13 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1339901 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1339901 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6707904 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 6707904 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4472369 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4472369 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 848782 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 848782 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 664798 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 220278 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 6707904 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5812270 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 13405250 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 664798 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 220278 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 6707904 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5812270 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 13405250 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020471 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.047399 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.027173 # miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses +system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997777 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997777 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999989 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999989 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.996989 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.996989 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999995 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.269330 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.269330 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.097343 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.097343 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.251475 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.251475 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.759196 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.759196 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019958 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.045187 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.097343 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.255667 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.161996 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019958 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.045187 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.097343 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.255667 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.161996 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 48939.831823 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 54920.293768 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 51514.366747 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13699.415067 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13699.415067 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10658.666653 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10658.666653 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1112750 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1112750 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66791.211482 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66791.211482 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 40459.230485 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40459.230485 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44684.186295 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44684.186295 # average ReadSharedReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 140485.676574 # average InvalidateReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 140485.676574 # average InvalidateReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 48939.831823 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 54920.293768 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40459.230485 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50151.484007 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 47290.005780 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 48939.831823 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 54920.293768 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40459.230485 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50151.484007 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 47290.005780 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 2951 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.267965 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.267965 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092436 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092436 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.240360 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.240360 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.751092 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.751092 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020471 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.047399 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092436 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.246724 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.155023 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020471 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.047399 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092436 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.246724 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.155023 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 53727.680212 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 61577.147783 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 57135.426195 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13281.168980 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13281.168980 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10431.040275 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10431.040275 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 580615.076923 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 580615.076923 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65901.007111 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65901.007111 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39985.302819 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39985.302819 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44834.792725 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44834.792725 # average ReadSharedReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 137959.342771 # average InvalidateReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 137959.342771 # average InvalidateReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 53727.680212 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 61577.147783 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39985.302819 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50109.271717 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 47169.895045 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 53727.680212 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 61577.147783 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39985.302819 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50109.271717 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 47169.895045 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 3672 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 31 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 25 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 95.193548 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 146.880000 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1713705 # number of writebacks -system.cpu0.l2cache.writebacks::total 1713705 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 4 # number of ReadReq MSHR hits +system.cpu0.l2cache.writebacks::writebacks 1813424 # number of writebacks +system.cpu0.l2cache.writebacks::total 1813424 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 5 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 178 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 63480 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 63480 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 6383 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 6383 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 183 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 69322 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 69322 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 4 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 7219 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 7219 # number of ReadSharedReq MSHR hits system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 5 # number of InvalidateReq MSHR hits system.cpu0.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 4 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 5 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 178 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 69863 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 70046 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 4 # number of overall MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 76541 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 76728 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 5 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 178 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 69863 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 70046 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12245 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9081 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 21326 # number of ReadReq MSHR misses -system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses -system.cpu0.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses -system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 3 # number of WritebackClean MSHR misses -system.cpu0.l2cache.WritebackClean_mshr_misses::total 3 # number of WritebackClean MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 867285 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 867285 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 258491 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 258491 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 189208 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 189208 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 273016 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 273016 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 583278 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 583278 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1017743 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1017743 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 620867 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::total 620867 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12245 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9081 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 583278 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1290759 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1895363 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12245 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9081 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 583278 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1290759 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 867285 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2762648 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 76541 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 76728 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13604 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10263 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 23867 # number of ReadReq MSHR misses +system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 4 # number of WritebackDirty MSHR misses +system.cpu0.l2cache.WritebackDirty_mshr_misses::total 4 # number of WritebackDirty MSHR misses +system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 2 # number of WritebackClean MSHR misses +system.cpu0.l2cache.WritebackClean_mshr_misses::total 2 # number of WritebackClean MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 927565 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 927565 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 266523 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 266523 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 193497 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 193497 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 13 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 13 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 289724 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 289724 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 620047 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 620047 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1067761 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1067761 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 637508 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 637508 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13604 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10263 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 620047 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1357485 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 2001399 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13604 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10263 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 620047 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1357485 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 927565 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2928964 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32157 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53450 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31964 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31964 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 54171 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32941 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 64121 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 85414 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 525913500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 445082000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 970995500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 62672299402 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 62672299402 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7863725997 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7863725997 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3782122004 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3782122004 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4091000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4091000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 17017630999 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17017630999 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20099332998 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20099332998 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 39175352474 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 39175352474 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 83498176486 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 83498176486 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 525913500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 445082000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20099332998 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 56192983473 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 77263311971 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 525913500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 445082000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20099332998 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 56192983473 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 62672299402 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 139935611373 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65819 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 87112 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 649200000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 572348000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1221548000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 68343452519 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 68343452519 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7943943496 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7943943496 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3893295994 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3893295994 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 6899996 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6899996 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 17756340999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17756340999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 21072592498 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 21072592498 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 41283242484 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 41283242484 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 84125646988 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 84125646988 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 649200000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 572348000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 21072592498 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 59039583483 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 81333723981 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 649200000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 572348000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 21072592498 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 59039583483 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 68343452519 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 149677176500 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5918259500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8698342000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5801825967 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5801825967 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6029953000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8810035500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5977560967 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5977560967 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11720085467 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14500167967 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.019952 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.044319 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026051 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses -system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 12007513967 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14787596467 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026966 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997777 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997777 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999989 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999989 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996989 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996989 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.218521 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.218521 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.097343 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097343 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.249908 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249908 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.759190 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.759190 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.019952 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.044319 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.097343 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242539 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156222 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.019952 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.044319 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.097343 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242539 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216228 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216228 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092435 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.238746 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.238746 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.751086 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.751086 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.233555 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.149300 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.233555 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227707 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 45531.065366 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72262.635007 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 72262.635007 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30421.662638 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30421.662638 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19989.228806 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19989.228806 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1022750 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1022750 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62331.991528 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62331.991528 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34459.268133 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34459.268133 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38492.382138 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38492.382138 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 134486.414137 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 134486.414137 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34459.268133 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43534.837621 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40764.387598 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34459.268133 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43534.837621 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72262.635007 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50652.711230 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.218494 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 51181.463946 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 73680.499500 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 73680.499500 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29805.846010 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29805.846010 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20120.704683 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20120.704683 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 530768.923077 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 530768.923077 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 61287.090469 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 61287.090469 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33985.476098 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38663.373624 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38663.373624 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 131960.143226 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 131960.143226 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43491.886454 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40638.435405 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43491.886454 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 73680.499500 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 51102.429562 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184042.650123 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162737.923293 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181511.261638 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181511.261638 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183403.887098 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162633.798527 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181462.644334 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181462.644334 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182780.765537 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169763.363933 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182432.336666 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169753.839505 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 24968942 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12837433 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2144 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2067889 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2067431 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 458 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 957998 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11124580 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31965 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31964 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5704814 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8040643 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2700571 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1106688 # Transaction distribution +system.cpu0.toL2Bus.snoop_filter.tot_requests 27467007 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14098216 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2397 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2174971 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2174417 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 554 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 1027741 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 12311555 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32941 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32941 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 6114023 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8970970 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2853143 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1178619 # Transaction distribution system.cpu0.toL2Bus.trans_dist::HardPFResp 8 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 482477 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 344108 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 518232 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1334424 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1260303 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5991996 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5072927 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 824948 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 817802 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18016682 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19524167 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 428300 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1294882 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 39264031 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 767195088 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 734396467 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1639224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4909864 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1508140643 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7265658 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 20566582 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.118168 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.322876 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeReq 489036 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 343853 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 531725 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 106 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1422561 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1350501 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6707921 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5424362 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 856015 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 848782 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20165788 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21120167 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 459340 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1399304 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 43144599 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 858918672 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 799305801 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1762224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5318384 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1665305081 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7537626 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 22154436 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.115021 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.319126 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 18136730 88.19% 88.19% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2429394 11.81% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 458 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 19606761 88.50% 88.50% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2547121 11.50% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 554 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 20566582 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 24844807916 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 22154436 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 27362140922 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 204855996 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 207113536 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9015512485 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 10089828109 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8672428624 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9431575123 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 223891503 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 239573965 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 681731807 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 735155181 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 134041815 # Number of BP lookups -system.cpu1.branchPred.condPredicted 89707660 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6609017 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 94187638 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 61197396 # Number of BTB hits +system.cpu1.branchPred.lookups 119891525 # Number of BP lookups +system.cpu1.branchPred.condPredicted 80198528 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5904198 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 84182887 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 54925615 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 64.973915 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17950728 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 175820 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.245583 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16054982 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 157154 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1718,90 +1727,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 567287 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 567287 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11327 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89325 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 259417 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 307870 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2446.318251 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 14947.483095 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 305492 99.23% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1236 0.40% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 840 0.27% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 161 0.05% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 48 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 59 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 20 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 307870 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 284687 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20644.869629 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17424.592515 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 21452.651975 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 281397 98.84% 98.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 951 0.33% 99.18% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1579 0.55% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 108 0.04% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 394 0.14% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 106 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 102 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 31 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 523591 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 523591 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9887 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 82113 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 242894 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 280697 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2503.193835 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 14937.525211 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 278494 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1255 0.45% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 659 0.23% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 166 0.06% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 38 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 57 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 13 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 280697 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 263545 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19785.484452 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17259.480271 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16001.974136 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 261738 99.31% 99.31% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 658 0.25% 99.56% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 820 0.31% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 79 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 151 0.06% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 47 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 31 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 284687 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 488633591384 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.617867 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.545160 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 487382306384 99.74% 99.74% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 662548500 0.14% 99.88% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 271218500 0.06% 99.94% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 131442000 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 92501000 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 52739500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 15718500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 24644000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 457500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 1000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-25 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::26-27 2500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 488633591384 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 89326 88.75% 88.75% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11327 11.25% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 100653 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 567287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 263545 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 427419381904 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.550644 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.560610 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 426298998404 99.74% 99.74% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 579725500 0.14% 99.87% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 235009500 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 123480000 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 88192000 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 51481500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 16753000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 25205500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 518000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 18500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 427419381904 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 82114 89.25% 89.25% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9887 10.75% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 92001 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 523591 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 567287 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 100653 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 523591 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92001 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 100653 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 667940 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92001 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 615592 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 99577859 # DTB read hits -system.cpu1.dtb.read_misses 392921 # DTB read misses -system.cpu1.dtb.write_hits 81911984 # DTB write hits -system.cpu1.dtb.write_misses 174366 # DTB write misses +system.cpu1.dtb.read_hits 88459625 # DTB read hits +system.cpu1.dtb.read_misses 355289 # DTB read misses +system.cpu1.dtb.write_hits 73058314 # DTB write hits +system.cpu1.dtb.write_misses 168302 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37295 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 442 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6095 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 34429 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 243 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 5558 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 38665 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 99970780 # DTB read accesses -system.cpu1.dtb.write_accesses 82086350 # DTB write accesses +system.cpu1.dtb.perms_faults 38457 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 88814914 # DTB read accesses +system.cpu1.dtb.write_accesses 73226616 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 181489843 # DTB hits -system.cpu1.dtb.misses 567287 # DTB misses -system.cpu1.dtb.accesses 182057130 # DTB accesses +system.cpu1.dtb.hits 161517939 # DTB hits +system.cpu1.dtb.misses 523591 # DTB misses +system.cpu1.dtb.accesses 162041530 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1831,1165 +1837,1156 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 85422 # Table walker walks requested -system.cpu1.itb.walker.walksLong 85422 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 706 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60440 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 10533 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 74889 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1637.737184 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 12543.180008 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 74488 99.46% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 92 0.12% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 279 0.37% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 10 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-327679 13 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 74889 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 71679 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26447.767128 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22834.132885 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 26054.956905 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 70042 97.72% 97.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 124 0.17% 97.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1290 1.80% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 62 0.09% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 94 0.13% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 27 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 71679 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 419883309648 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.857166 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.350104 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 59999474576 14.29% 14.29% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 359861735072 85.71% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 18604000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 3422000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 61500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 12500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 419883309648 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 60440 98.85% 98.85% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 706 1.15% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 61146 # Table walker page sizes translated +system.cpu1.itb.walker.walks 79238 # Table walker walks requested +system.cpu1.itb.walker.walksLong 79238 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 670 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55768 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9704 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 69534 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1362.196911 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 10189.827482 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 68875 99.05% 99.05% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 429 0.62% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 22 0.03% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 45 0.06% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 97 0.14% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 46 0.07% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69534 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 66142 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24972.294457 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22450.763423 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 20128.243900 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 65282 98.70% 98.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 106 0.16% 98.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 635 0.96% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 41 0.06% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 34 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 18 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 66142 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 405913969924 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.852777 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.354498 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 59781305300 14.73% 14.73% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 346114009624 85.27% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 16127000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 2369500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 82500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 76000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 405913969924 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 55768 98.81% 98.81% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 670 1.19% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 56438 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85422 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85422 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 79238 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 79238 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61146 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61146 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 146568 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 210903230 # ITB inst hits -system.cpu1.itb.inst_misses 85422 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56438 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56438 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 135676 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 188743149 # ITB inst hits +system.cpu1.itb.inst_misses 79238 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26936 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 24595 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 219212 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 203696 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 210988652 # ITB inst accesses -system.cpu1.itb.hits 210903230 # DTB hits -system.cpu1.itb.misses 85422 # DTB misses -system.cpu1.itb.accesses 210988652 # DTB accesses -system.cpu1.numCycles 739589068 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 188822387 # ITB inst accesses +system.cpu1.itb.hits 188743149 # DTB hits +system.cpu1.itb.misses 79238 # DTB misses +system.cpu1.itb.accesses 188822387 # DTB accesses +system.cpu1.numCycles 668763369 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 87179307 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 594353675 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 134041815 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 79148124 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 611930141 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 14224484 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1980961 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 327085 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6413771 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 794469 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 836341 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 210662459 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1674863 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 29397 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 716574317 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.975535 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.220237 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 76762482 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 531105996 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 119891525 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 70980597 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 555217707 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 12731518 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1797928 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 295013 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 5987179 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 752221 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 763722 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 188519405 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1489379 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 27517 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 647942011 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.963740 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.217002 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 382171132 53.33% 53.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 130053591 18.15% 71.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 44058900 6.15% 77.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 160290694 22.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 349005233 53.86% 53.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 116425876 17.97% 71.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 39511198 6.10% 77.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 142999704 22.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 716574317 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.181238 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.803627 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 104297157 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 348522347 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 221906314 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 36809016 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5039483 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 18926425 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2113724 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 618028101 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22771231 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5039483 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 138949493 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 52143991 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 230343934 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 223632177 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 66465239 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 601445820 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5788119 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 10817316 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 260401 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 332552 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 31997393 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 11898 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 571172784 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 925552885 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 711516112 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 817303 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 514566329 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 56606455 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15686724 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13790746 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 74346046 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 99668213 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 85253354 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 9496006 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 8106709 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 579162522 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15985308 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 584188542 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2667167 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 53686437 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 34500302 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 290258 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 716574317 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.815252 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.066417 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 647942011 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.179273 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.794161 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 92682171 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 320350015 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 196661442 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 33741382 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4507001 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 16971690 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1895430 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 551371568 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 20348682 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4507001 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 124070698 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 47114866 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 212074227 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 198637530 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 61537689 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 536563152 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5145214 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9840770 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 223861 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 282097 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 29934469 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 10810 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 509803663 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 829081125 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 634679636 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 600803 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 459431302 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 50372361 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14562905 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 12854163 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 68041373 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 88476596 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 76035338 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8565835 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7285035 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 516079501 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 14870100 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 521291240 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2377203 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 47872437 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 30743352 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 257935 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 647942011 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.804534 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.061029 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 397414827 55.46% 55.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 134713914 18.80% 74.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 111740906 15.59% 89.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 64830862 9.05% 98.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7868810 1.10% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4998 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 361872507 55.85% 55.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 122353667 18.88% 74.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 99252241 15.32% 90.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 57424869 8.86% 98.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7035151 1.09% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3576 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 716574317 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 647942011 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 59065524 44.03% 44.03% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 54166 0.04% 44.07% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 19277 0.01% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 22 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 36039894 26.87% 70.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 38965641 29.05% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 52040674 43.67% 43.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 50092 0.04% 43.71% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 18388 0.02% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 16 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 32200400 27.02% 70.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 34865580 29.26% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 40 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 396970173 67.95% 67.95% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1317793 0.23% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 74565 0.01% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 1 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 84907 0.01% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 102569706 17.56% 85.76% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 83171310 14.24% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 27 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 354670500 68.04% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1183955 0.23% 68.26% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 65513 0.01% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 42657 0.01% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 91135432 17.48% 85.77% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 74193108 14.23% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 584188542 # Type of FU issued -system.cpu1.iq.rate 0.789883 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 134144524 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.229625 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 2020390722 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 648436438 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 567390385 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1372370 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 557189 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 510457 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 717484509 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 848517 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2681981 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 521291240 # Type of FU issued +system.cpu1.iq.rate 0.779485 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 119175150 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.228615 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1811086365 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 578565811 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 506287229 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 990479 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 395514 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 364516 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 639849832 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 616531 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2398408 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 12380566 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16529 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 160745 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5876169 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11063470 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 14436 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 140383 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5257500 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2772484 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4108210 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2402216 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3864822 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5039483 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6511130 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2319208 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 595271017 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4507001 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5849706 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2188326 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 531063111 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 99668213 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 85253354 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13572161 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64444 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2193101 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 160745 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2023154 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2795718 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4818872 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 576621181 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 99570735 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 7012433 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 88476596 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 76035338 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12650539 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 60907 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2070757 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 140383 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1813068 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2483133 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4296201 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 514538937 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 88454625 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6240485 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 123187 # number of nop insts executed -system.cpu1.iew.exec_refs 181482515 # number of memory reference insts executed -system.cpu1.iew.exec_branches 107903719 # Number of branches executed -system.cpu1.iew.exec_stores 81911780 # Number of stores executed -system.cpu1.iew.exec_rate 0.779651 # Inst execution rate -system.cpu1.iew.wb_sent 568628901 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 567900842 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 274880956 # num instructions producing a value -system.cpu1.iew.wb_consumers 450165977 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.767860 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610621 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 47031076 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15695050 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4536258 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 707685383 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.765116 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.566861 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 113510 # number of nop insts executed +system.cpu1.iew.exec_refs 161513914 # number of memory reference insts executed +system.cpu1.iew.exec_branches 96416033 # Number of branches executed +system.cpu1.iew.exec_stores 73059289 # Number of stores executed +system.cpu1.iew.exec_rate 0.769389 # Inst execution rate +system.cpu1.iew.wb_sent 507314383 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 506651745 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 244576343 # num instructions producing a value +system.cpu1.iew.wb_consumers 400655745 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.757595 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610440 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 41944033 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14612165 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4045440 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 639995571 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.754813 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.555930 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 470367960 66.47% 66.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 123401303 17.44% 83.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 52359305 7.40% 91.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 17652538 2.49% 93.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 12497517 1.77% 95.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8502383 1.20% 96.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5935480 0.84% 97.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3482174 0.49% 98.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 13486723 1.91% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 426913272 66.71% 66.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 112061055 17.51% 84.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 46474767 7.26% 91.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15512784 2.42% 93.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11149430 1.74% 95.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7505688 1.17% 96.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5285555 0.83% 97.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3055428 0.48% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12037592 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 707685383 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 459224264 # Number of instructions committed -system.cpu1.commit.committedOps 541461392 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 639995571 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 409938912 # Number of instructions committed +system.cpu1.commit.committedOps 483077163 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 166664832 # Number of memory references committed -system.cpu1.commit.loads 87287647 # Number of loads committed -system.cpu1.commit.membars 3905531 # Number of memory barriers committed -system.cpu1.commit.branches 102374979 # Number of branches committed -system.cpu1.commit.fp_insts 497703 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 497469676 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13371734 # Number of function calls committed. +system.cpu1.commit.refs 148190964 # Number of memory references committed +system.cpu1.commit.loads 77413126 # Number of loads committed +system.cpu1.commit.membars 3553266 # Number of memory barriers committed +system.cpu1.commit.branches 91478423 # Number of branches committed +system.cpu1.commit.fp_insts 356192 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 443462583 # Number of committed integer instructions. +system.cpu1.commit.function_calls 11919697 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 373594883 69.00% 69.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1066183 0.20% 69.19% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 59540 0.01% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 75912 0.01% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 87287647 16.12% 85.34% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 79377185 14.66% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 333838399 69.11% 69.11% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 958189 0.20% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 52064 0.01% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 37505 0.01% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 77413126 16.03% 85.35% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 70777838 14.65% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 541461392 # Class of committed instruction -system.cpu1.commit.bw_lim_events 13486723 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1278856692 # The number of ROB reads -system.cpu1.rob.rob_writes 1185834230 # The number of ROB writes -system.cpu1.timesIdled 958439 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 23014751 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94048355585 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 459224264 # Number of Instructions Simulated -system.cpu1.committedOps 541461392 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.610518 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.610518 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.620918 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.620918 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 681935687 # number of integer regfile reads -system.cpu1.int_regfile_writes 403917801 # number of integer regfile writes -system.cpu1.fp_regfile_reads 803668 # number of floating regfile reads -system.cpu1.fp_regfile_writes 473340 # number of floating regfile writes -system.cpu1.cc_regfile_reads 122826591 # number of cc regfile reads -system.cpu1.cc_regfile_writes 123738784 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1267794356 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15807378 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5498905 # number of replacements -system.cpu1.dcache.tags.tagsinuse 458.394450 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 155608106 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5499414 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.295398 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8486277940000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.394450 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895302 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.895302 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 416 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 345701865 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 345701865 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 81166944 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 81166944 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 69652711 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 69652711 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 179570 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 179570 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 55554 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 55554 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1867218 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1867218 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1906025 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1906025 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 150819655 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 150819655 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 150999225 # number of overall hits -system.cpu1.dcache.overall_hits::total 150999225 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6513815 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6513815 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7138740 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7138740 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 666746 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 666746 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 433208 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 433208 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 280157 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 280157 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195063 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 195063 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13652555 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13652555 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14319301 # number of overall misses -system.cpu1.dcache.overall_misses::total 14319301 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 107790302500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 107790302500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 154935306923 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 154935306923 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17952138757 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 17952138757 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4403404000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 4403404000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5419622500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5419622500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3200000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3200000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 262725609423 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 262725609423 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 262725609423 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 262725609423 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 87680759 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 87680759 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 76791451 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 76791451 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 846316 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 846316 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 488762 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 488762 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2147375 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2147375 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2101088 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2101088 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 164472210 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 164472210 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 165318526 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 165318526 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074290 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.074290 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.092963 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.092963 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787822 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787822 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.886337 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.886337 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130465 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130465 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092839 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092839 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083008 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.083008 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.086616 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.086616 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16547.952697 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16547.952697 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21703.452839 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21703.452839 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41439.998239 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41439.998239 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15717.629758 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15717.629758 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27783.959541 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27783.959541 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 483077163 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12037592 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1149378464 # The number of ROB reads +system.cpu1.rob.rob_writes 1057951201 # The number of ROB writes +system.cpu1.timesIdled 862725 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 20821358 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94039702456 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 409938912 # Number of Instructions Simulated +system.cpu1.committedOps 483077163 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.631373 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.631373 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.612981 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.612981 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 608507800 # number of integer regfile reads +system.cpu1.int_regfile_writes 359700181 # number of integer regfile writes +system.cpu1.fp_regfile_reads 588843 # number of floating regfile reads +system.cpu1.fp_regfile_writes 298828 # number of floating regfile writes +system.cpu1.cc_regfile_reads 110183943 # number of cc regfile reads +system.cpu1.cc_regfile_writes 110950246 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1143200959 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14699928 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 4943818 # number of replacements +system.cpu1.dcache.tags.tagsinuse 455.490717 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 138046990 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4944322 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.920307 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8486298300000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.490717 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.889630 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.889630 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 504 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 434 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.984375 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 307427480 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 307427480 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 71852716 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 71852716 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 61790747 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 61790747 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 162379 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 162379 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50057 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 50057 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1706960 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1706960 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1722622 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1722622 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 133643463 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 133643463 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 133805842 # number of overall hits +system.cpu1.dcache.overall_hits::total 133805842 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 5820950 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 5820950 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6630483 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6630483 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 628859 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 628859 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 401328 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 401328 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243245 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 243245 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 186259 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 186259 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 12451433 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 12451433 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13080292 # number of overall misses +system.cpu1.dcache.overall_misses::total 13080292 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96708932500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 96708932500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 144491403356 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 144491403356 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16631824083 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 16631824083 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3760760000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3760760000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5141971500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5141971500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6754500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6754500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 241200335856 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 241200335856 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 241200335856 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 241200335856 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 77673666 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 77673666 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 68421230 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 68421230 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 791238 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 791238 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 451385 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 451385 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1950205 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1950205 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1908881 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1908881 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 146094896 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 146094896 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 146886134 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 146886134 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074941 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.074941 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.096907 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.096907 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794779 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794779 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.889104 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.889104 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124728 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124728 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097575 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097575 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085228 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.085228 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089051 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.089051 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16613.943171 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16613.943171 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21791.987606 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21791.987606 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41441.972858 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41441.972858 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15460.790561 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15460.790561 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27606.566663 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27606.566663 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19243.695369 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19243.695369 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18347.656036 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18347.656036 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 4719493 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 24576154 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 351674 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 713575 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.420079 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 34.440884 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19371.291309 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19371.291309 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18439.980992 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18439.980992 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4381553 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 22968096 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 326353 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 670571 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.425809 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 34.251550 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 5498938 # number of writebacks -system.cpu1.dcache.writebacks::total 5498938 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3304670 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3304670 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5753104 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5753104 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3561 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3561 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 144550 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 144550 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 9057774 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 9057774 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 9057774 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 9057774 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3209145 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3209145 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1385636 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1385636 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 666638 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 666638 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 429647 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 429647 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 135607 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 135607 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195058 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 195058 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4594781 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4594781 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5261419 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5261419 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6299 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6299 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6428 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6428 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 12727 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 12727 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 49159510500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 49159510500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 33253300624 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 33253300624 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15899737000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15899737000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 17350623757 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 17350623757 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1958308000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1958308000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5224605500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5224605500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3159000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3159000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82412811124 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 82412811124 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 98312548124 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 98312548124 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 727883500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 727883500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 859834500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 859834500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1587718000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1587718000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036600 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036600 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018044 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018044 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787694 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787694 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.879052 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.879052 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063150 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063150 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092837 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092837 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027937 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027937 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031826 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031826 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15318.569432 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15318.569432 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23998.583051 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23998.583051 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23850.631077 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23850.631077 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40383.439794 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40383.439794 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14441.053928 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14441.053928 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26784.881933 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26784.881933 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 4943833 # number of writebacks +system.cpu1.dcache.writebacks::total 4943833 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 2977175 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 2977175 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5355618 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5355618 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3078 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3078 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125917 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 125917 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8332793 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8332793 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8332793 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8332793 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2843775 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2843775 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1274865 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1274865 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 628773 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 628773 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 398250 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 398250 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117328 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117328 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 186249 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 186249 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4118640 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4118640 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4747413 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4747413 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5429 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5429 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5284 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5284 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10713 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10713 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43326231000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43326231000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30961849442 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30961849442 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15267610500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15267610500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16078596583 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16078596583 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1709363500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1709363500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4955815500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4955815500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6661500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6661500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74288080442 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 74288080442 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 89555690942 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 89555690942 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 604887500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 604887500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 670175500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 670175500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1275063000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1275063000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036612 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036612 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018633 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018633 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794670 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794670 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.882285 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.882285 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060162 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060162 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097570 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097570 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028192 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028192 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032320 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032320 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15235.463776 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15235.463776 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24286.374982 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24286.374982 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24281.593675 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24281.593675 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40373.123874 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40373.123874 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14569.101152 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14569.101152 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26608.548234 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26608.548234 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17936.178269 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17936.178269 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18685.557665 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18685.557665 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 115555.405620 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 115555.405620 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133763.923460 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 133763.923460 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124751.944685 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124751.944685 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.041461 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18037.041461 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18864.103659 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18864.103659 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111417.848591 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 111417.848591 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 126831.093868 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 126831.093868 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 119020.162419 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 119020.162419 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5972259 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.613786 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 204337040 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5972771 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 34.211431 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8525956583000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.613786 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979714 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.979714 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5253385 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.776230 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 182951519 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5253897 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 34.822060 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8525973531000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.776230 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980032 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980032 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 427283163 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 427283163 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 204337040 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 204337040 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 204337040 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 204337040 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 204337040 # number of overall hits -system.cpu1.icache.overall_hits::total 204337040 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6318152 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6318152 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6318152 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6318152 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6318152 # number of overall misses -system.cpu1.icache.overall_misses::total 6318152 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 69955140831 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 69955140831 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 69955140831 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 69955140831 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 69955140831 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 69955140831 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 210655192 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 210655192 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 210655192 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 210655192 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 210655192 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 210655192 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029993 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029993 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029993 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029993 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029993 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029993 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11072.088932 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 11072.088932 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11072.088932 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 11072.088932 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11072.088932 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 11072.088932 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 10670268 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 1157 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 748022 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.264645 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 144.625000 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 382279380 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 382279380 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 182951519 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 182951519 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 182951519 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 182951519 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 182951519 # number of overall hits +system.cpu1.icache.overall_hits::total 182951519 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5561220 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5561220 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5561220 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5561220 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5561220 # number of overall misses +system.cpu1.icache.overall_misses::total 5561220 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 62243274721 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 62243274721 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 62243274721 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 62243274721 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 62243274721 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 62243274721 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 188512739 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 188512739 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 188512739 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 188512739 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 188512739 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 188512739 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029500 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029500 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029500 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029500 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029500 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029500 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11192.377701 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 11192.377701 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11192.377701 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 11192.377701 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11192.377701 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 11192.377701 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 9679381 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 762 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 668024 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.489571 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 5972259 # number of writebacks -system.cpu1.icache.writebacks::total 5972259 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 345373 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 345373 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 345373 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 345373 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 345373 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 345373 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5972779 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5972779 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5972779 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5972779 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5972779 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5972779 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 5253385 # number of writebacks +system.cpu1.icache.writebacks::total 5253385 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 307318 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 307318 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 307318 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 307318 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 307318 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 307318 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5253902 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5253902 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5253902 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5253902 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5253902 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5253902 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 63045966777 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 63045966777 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 63045966777 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 63045966777 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 63045966777 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 63045966777 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8835998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8835998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8835998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8835998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028353 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028353 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028353 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.028353 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028353 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.028353 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10555.549900 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10555.549900 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10555.549900 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10555.549900 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10555.549900 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10555.549900 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 131880.567164 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 131880.567164 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 56076616223 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 56076616223 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 56076616223 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 56076616223 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 56076616223 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 56076616223 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9266998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9266998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9266998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9266998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027870 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027870 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027870 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10673.327409 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10673.327409 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10673.327409 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138313.402985 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138313.402985 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138313.402985 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138313.402985 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7501600 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7506319 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 4330 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6897065 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6901426 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 4002 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 900873 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2224556 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13365.286062 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 17240330 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2240308 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.695518 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10278781174500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12562.638726 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.088648 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 68.405438 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000005 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 667.153246 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.766763 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004095 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004175 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.040720 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.815752 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1289 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 98 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14365 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 78 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 616 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 417 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu1.l2cache.prefetcher.pfSpanPage 806814 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2026565 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13359.801047 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 15204091 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2042184 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 7.445015 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 10003867799500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 12523.198532 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 53.208861 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 55.513996 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 727.879658 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.764355 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003248 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003388 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.044426 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.815418 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1266 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 101 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14252 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 87 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 167 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 620 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 392 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 76 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 949 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4690 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4883 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3797 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078674 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005981 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.876770 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 393723429 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 393723429 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 587134 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 192926 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 780060 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3457963 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3457963 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 8011825 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 8011825 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 813 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 813 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 855353 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 855353 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5413940 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 5413940 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3003863 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 3003863 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191485 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 191485 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 587134 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 192926 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5413940 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3859216 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 10053216 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 587134 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 192926 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5413940 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3859216 # number of overall hits -system.cpu1.l2cache.overall_hits::total 10053216 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12541 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9429 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 21970 # number of ReadReq misses -system.cpu1.l2cache.WritebackDirty_misses::writebacks 4 # number of WritebackDirty misses -system.cpu1.l2cache.WritebackDirty_misses::total 4 # number of WritebackDirty misses -system.cpu1.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses -system.cpu1.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 239265 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 239265 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 195055 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 195055 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 299638 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 299638 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 558835 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 558835 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1003530 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 1003530 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 236473 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 236473 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12541 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9429 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 558835 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1303168 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1883973 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12541 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9429 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 558835 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1303168 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1883973 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 648758500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 531765000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1180523500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3573774499 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 3573774499 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1875778500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1875778500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3096999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3096999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 16089567500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 16089567500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 21287303500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 21287303500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 40947637491 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 40947637491 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 14994721499 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 14994721499 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 648758500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 531765000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 21287303500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 57037204991 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 79505031991 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 648758500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 531765000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 21287303500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 57037204991 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 79505031991 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 599675 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 202355 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 802030 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3457967 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3457967 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 8011827 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 8011827 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 240078 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 240078 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195057 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 195057 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1154991 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1154991 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5972775 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 5972775 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4007393 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 4007393 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 427958 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 427958 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 599675 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 202355 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5972775 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5162384 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 11937189 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 599675 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 202355 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5972775 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5162384 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 11937189 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020913 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046596 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.027393 # miss rate for ReadReq accesses -system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses -system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses -system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses -system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996614 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996614 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999990 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999990 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 933 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4753 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4784 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3782 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.077271 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006165 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.869873 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 351102850 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 351102850 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 535016 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 179387 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 714403 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 3106842 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 3106842 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 7089221 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 7089221 # number of WritebackClean hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 559 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 559 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 768937 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 768937 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4743157 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4743157 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2644934 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 2644934 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 173458 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 173458 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 535016 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 179387 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4743157 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3413871 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8871431 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 535016 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 179387 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4743157 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3413871 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8871431 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11427 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8460 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 19887 # number of ReadReq misses +system.cpu1.l2cache.WritebackDirty_misses::writebacks 5 # number of WritebackDirty misses +system.cpu1.l2cache.WritebackDirty_misses::total 5 # number of WritebackDirty misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 231672 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 231672 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 186238 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 186238 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 11 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 282579 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 282579 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 510739 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 510739 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 941159 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 941159 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 223115 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 223115 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11427 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8460 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 510739 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1223738 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1754364 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11427 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8460 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 510739 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1223738 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1754364 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 504816000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 376201500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 881017500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3395371000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 3395371000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1764127500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1764127500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 6519498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 6519498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 14960777499 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 14960777499 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 19472916000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 19472916000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 37255203986 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 37255203986 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 13917612499 # number of InvalidateReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::total 13917612499 # number of InvalidateReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 504816000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 376201500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 19472916000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 52215981485 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 72569914985 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 504816000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 376201500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 19472916000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 52215981485 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 72569914985 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 546443 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 187847 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 734290 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3106847 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 3106847 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 7089221 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 7089221 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 232231 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 232231 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 186238 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 186238 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 11 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1051516 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1051516 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5253896 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 5253896 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3586093 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 3586093 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 396573 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 396573 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 546443 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 187847 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5253896 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4637609 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10625795 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 546443 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 187847 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 5253896 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4637609 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10625795 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020912 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.045037 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.027083 # miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000002 # miss rate for WritebackDirty accesses +system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000002 # miss rate for WritebackDirty accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997593 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997593 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.259429 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.259429 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.093564 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.093564 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.250420 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.250420 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.552561 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.552561 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020913 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046596 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.093564 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.252435 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.157824 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020913 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046596 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.093564 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.252435 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.157824 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 51731.002312 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 56396.754693 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 53733.431953 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14936.470019 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14936.470019 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9616.664531 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9616.664531 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 3096999 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 3096999 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53696.685667 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53696.685667 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38092.287527 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38092.287527 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 40803.600780 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 40803.600780 # average ReadSharedReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 63409.867084 # average InvalidateReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 63409.867084 # average InvalidateReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 51731.002312 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 56396.754693 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38092.287527 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 43768.113544 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 42200.727925 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 51731.002312 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 56396.754693 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38092.287527 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 43768.113544 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 42200.727925 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 1276 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.268735 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.268735 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097211 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097211 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.262447 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.262447 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.562608 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.562608 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020912 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.045037 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097211 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.263873 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.165104 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020912 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.045037 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097211 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.263873 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.165104 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 44177.474403 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 44468.262411 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44301.176648 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14655.940295 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14655.940295 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9472.435808 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9472.435808 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 592681.636364 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 592681.636364 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52943.698927 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52943.698927 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38126.941549 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38126.941549 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39584.389020 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39584.389020 # average ReadSharedReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 62378.650019 # average InvalidateReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 62378.650019 # average InvalidateReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 44177.474403 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 44468.262411 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38126.941549 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42669.249043 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 41365.369436 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 44177.474403 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 44468.262411 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38126.941549 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42669.249043 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 41365.369436 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 688 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 159.500000 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 172 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1185134 # number of writebacks -system.cpu1.l2cache.writebacks::total 1185134 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 196 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 199 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 42850 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 42850 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 5641 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 5641 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 196 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 48491 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 48690 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 196 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 48491 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 48690 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12538 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9233 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 21771 # number of ReadReq MSHR misses -system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 4 # number of WritebackDirty MSHR misses -system.cpu1.l2cache.WritebackDirty_mshr_misses::total 4 # number of WritebackDirty MSHR misses -system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 2 # number of WritebackClean MSHR misses -system.cpu1.l2cache.WritebackClean_mshr_misses::total 2 # number of WritebackClean MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 776550 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 776550 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 239265 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 239265 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 195055 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 195055 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 256788 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 256788 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 558835 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 558835 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 997889 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 997889 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 236470 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::total 236470 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12538 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9233 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 558835 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1254677 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1835283 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12538 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9233 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 558835 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1254677 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 776550 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2611833 # number of overall MSHR misses +system.cpu1.l2cache.writebacks::writebacks 1085694 # number of writebacks +system.cpu1.l2cache.writebacks::total 1085694 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 5 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 200 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 205 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 34736 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 34736 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4713 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4713 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 6 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 5 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 200 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 39449 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 39654 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 5 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 200 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 39449 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 39654 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11422 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8260 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 19682 # number of ReadReq MSHR misses +system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 5 # number of WritebackDirty MSHR misses +system.cpu1.l2cache.WritebackDirty_mshr_misses::total 5 # number of WritebackDirty MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 718118 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 718118 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 231672 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 231672 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 186238 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 186238 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 11 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 247843 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 247843 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 510739 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 510739 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 936446 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 936446 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 223109 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::total 223109 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11422 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8260 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 510739 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1184289 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1714710 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11422 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8260 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 510739 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1184289 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 718118 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2432828 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6299 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6366 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 6428 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 6428 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5429 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5496 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5284 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5284 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 12727 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 12794 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 573471000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 464925500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1038396500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 46806898722 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 46806898722 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7460497999 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7460497999 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3758753499 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3758753499 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2850999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2850999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 12334341500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 12334341500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17934293500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17934293500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 34643944491 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 34643944491 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 13575517499 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 13575517499 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 573471000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 464925500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17934293500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 46978285991 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 65950975991 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 573471000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 464925500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17934293500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 46978285991 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46806898722 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 112757874713 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8332500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 677372000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 685704500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 811538500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 811538500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8332500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1488910500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1497243000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020908 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.045628 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027145 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses -system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses -system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses -system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10713 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10780 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 436185000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 314747000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 750932000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40592481689 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 40592481689 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7117149993 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7117149993 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3556198494 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3556198494 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5961498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5961498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11593238999 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11593238999 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16408482000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16408482000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 31352302486 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 31352302486 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 12578456999 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 12578456999 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 436185000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 314747000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16408482000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 42945541485 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 60104955485 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 436185000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 314747000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16408482000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 42945541485 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40592481689 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 100697437174 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8763500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 561342500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 570106000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 630451500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 630451500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8763500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1191794000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1200557500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026804 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996614 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996614 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999990 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999990 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997593 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997593 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222329 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222329 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.093564 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093564 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.249012 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249012 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.552554 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.552554 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020908 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.045628 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093564 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243042 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153745 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020908 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.045628 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093564 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243042 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.235701 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.235701 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097211 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.261133 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261133 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.562593 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.562593 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255366 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161372 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255366 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.218798 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 47696.316200 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60275.447456 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 60275.447456 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31180.899835 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31180.899835 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19270.223778 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19270.223778 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 2850999 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2850999 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48033.169385 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48033.169385 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32092.287527 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32092.287527 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34717.232569 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34717.232569 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 57409.047655 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 57409.047655 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32092.287527 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 37442.533808 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35935.044345 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32092.287527 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 37442.533808 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60275.447456 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43171.931250 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 107536.434355 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 107713.556393 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 126250.544493 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 126250.544493 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116988.331893 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 117026.965765 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228955 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38153.236460 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56526.199996 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 56526.199996 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30720.803520 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30720.803520 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19094.913466 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19094.913466 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 541954.363636 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 541954.363636 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46776.544018 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46776.544018 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32126.941549 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33480.096542 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33480.096542 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 56378.079768 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 56378.079768 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36262.720911 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35052.548527 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36262.720911 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56526.199996 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 41391.104169 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130798.507463 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 103397.034445 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 103731.077147 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 119313.304315 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 119313.304315 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130798.507463 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 111247.456361 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 111368.970315 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 23835470 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12272459 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1390 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 2000895 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2000561 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 334 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 900425 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10970003 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6428 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6428 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4651207 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 8011843 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2673516 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 976496 # Transaction distribution +system.cpu1.toL2Bus.snoop_filter.tot_requests 21246355 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10958434 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1131 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1866438 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1866138 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 300 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 825754 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9752282 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5284 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5284 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4201386 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7090370 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2466487 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 905169 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 442024 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 347278 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 498740 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1227372 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1161574 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5972779 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4961310 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 435892 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 427958 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17917345 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17734263 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 424426 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1271663 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 37347697 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 764444720 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 688461274 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1618840 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4797400 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1459322234 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6483444 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 19136823 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.123774 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.329377 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeReq 447608 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337242 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 479463 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 119 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1130462 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1058321 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5253902 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4579290 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 402900 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 396573 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15761317 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16025111 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 394044 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1160504 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 33340976 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 672467056 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 619232766 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1502776 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4371544 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1297574142 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6151657 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 17448758 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.126682 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.332668 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 16768514 87.62% 87.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2367975 12.37% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 334 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 15238612 87.33% 87.33% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2209846 12.66% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 300 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 19136823 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 23662576976 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 17448758 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 21067285470 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 176028266 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 170823638 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8965097194 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7886135987 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8193842587 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7380840948 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 222514103 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 206620146 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 672743976 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 614769571 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40336 # Transaction distribution -system.iobus.trans_dist::ReadResp 40336 # Transaction distribution -system.iobus.trans_dist::WriteReq 136625 # Transaction distribution -system.iobus.trans_dist::WriteResp 136625 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47628 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40283 # Transaction distribution +system.iobus.trans_dist::ReadResp 40283 # Transaction distribution +system.iobus.trans_dist::WriteReq 136631 # Transaction distribution +system.iobus.trans_dist::WriteResp 136631 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -3002,13 +2999,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122562 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231280 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231280 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353922 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353828 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3021,101 +3018,101 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155669 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339136 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339136 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338672 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338672 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496891 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36916001 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36944000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24643501 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24787502 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36442501 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36442000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 565518728 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567400129 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92668000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92684000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147976000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147860000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115636 # number of replacements -system.iocache.tags.tagsinuse 11.302848 # Cycle average of tags in use +system.iocache.tags.replacements 115578 # number of replacements +system.iocache.tags.tagsinuse 11.298905 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115652 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115594 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9125688591000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.411882 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.890966 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463243 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.243185 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706428 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9125697698000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.418105 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.880800 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463632 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.242550 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706182 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041117 # Number of tag accesses -system.iocache.tags.data_accesses 1041117 # Number of data accesses +system.iocache.tags.tag_accesses 1040595 # Number of tag accesses +system.iocache.tags.data_accesses 1040595 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8912 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8949 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8854 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8891 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8912 # number of demand (read+write) misses -system.iocache.demand_misses::total 8952 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8854 # number of demand (read+write) misses +system.iocache.demand_misses::total 8894 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8912 # number of overall misses -system.iocache.overall_misses::total 8952 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1705648493 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1710848493 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8854 # number of overall misses +system.iocache.overall_misses::total 8894 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5230500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1713293012 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1718523512 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13974401235 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13974401235 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1705648493 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1711217493 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1705648493 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1711217493 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13529785617 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13529785617 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5599500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1713293012 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1718892512 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5599500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1713293012 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1718892512 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8912 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8949 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8854 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8891 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8912 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8952 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8854 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8894 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8912 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8952 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8854 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8894 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3129,55 +3126,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 191387.847060 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 191177.616829 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141364.864865 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 193504.970861 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 193287.989203 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130934.724112 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130934.724112 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 191387.847060 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 191154.769102 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 191387.847060 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 191154.769102 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 35975 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126768.848072 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126768.848072 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139987.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 193504.970861 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 193264.280639 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139987.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 193504.970861 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 193264.280639 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34686 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3674 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3488 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.791780 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.944381 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8912 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8949 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8854 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8891 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8912 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8952 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8854 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8912 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8952 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1260048493 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1263398493 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8854 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8894 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3380500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1270593012 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1273973512 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8638001235 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8638001235 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3569000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1260048493 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1263617493 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3569000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1260048493 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1263617493 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8187257903 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8187257903 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3599500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1270593012 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1274192512 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3599500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1270593012 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1274192512 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3191,620 +3188,624 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141387.847060 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 141177.616829 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91364.864865 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143504.970861 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 143287.989203 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80934.724112 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80934.724112 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 141387.847060 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 141154.769102 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 141387.847060 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 141154.769102 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76711.433766 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76711.433766 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89987.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 143504.970861 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 143264.280639 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89987.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 143504.970861 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 143264.280639 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1576044 # number of replacements -system.l2c.tags.tagsinuse 63242.380291 # Cycle average of tags in use -system.l2c.tags.total_refs 6232719 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1635533 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.810818 # Average number of references to valid blocks. +system.l2c.tags.replacements 1550465 # number of replacements +system.l2c.tags.tagsinuse 63029.233494 # Cycle average of tags in use +system.l2c.tags.total_refs 6222316 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1609843 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.865169 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 20333.059620 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 44.017365 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 59.342117 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3579.623644 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5086.228075 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3815.151087 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 296.252046 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 450.100507 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3644.907232 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8614.023056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17319.675542 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.310258 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000672 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000905 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.054621 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.077610 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.058215 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004520 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006868 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.055617 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.131440 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.264277 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.965002 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9601 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 201 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49687 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1158 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 504 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 7939 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 193 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2840 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5617 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 40824 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.146500 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003067 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.758163 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 79314813 # Number of tag accesses -system.l2c.tags.data_accesses 79314813 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2898844 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2898844 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 4 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 4 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 171467 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 140817 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 312284 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 39034 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 42272 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 81306 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 165571 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 166162 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 331733 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6582 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4549 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 520761 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 620991 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 302233 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6543 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4534 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 509705 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 595476 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 292636 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2864010 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6582 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4549 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 520761 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 786562 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 302233 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6543 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4534 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 509705 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 761638 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 292636 # number of demand (read+write) hits -system.l2c.demand_hits::total 3195743 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6582 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4549 # number of overall hits -system.l2c.overall_hits::cpu0.inst 520761 # number of overall hits -system.l2c.overall_hits::cpu0.data 786562 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 302233 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6543 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4534 # number of overall hits -system.l2c.overall_hits::cpu1.inst 509705 # number of overall hits -system.l2c.overall_hits::cpu1.data 761638 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 292636 # number of overall hits -system.l2c.overall_hits::total 3195743 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 62046 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 61831 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 123877 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 12641 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 11279 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 23920 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 543765 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 121378 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 665143 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2350 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2224 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 62516 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 155884 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 318351 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2672 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2379 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 49130 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 126625 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 232724 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 954855 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2350 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2224 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 62516 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 699649 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 318351 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2672 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2379 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 49130 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 248003 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 232724 # number of demand (read+write) misses -system.l2c.demand_misses::total 1619998 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2350 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2224 # number of overall misses -system.l2c.overall_misses::cpu0.inst 62516 # number of overall misses -system.l2c.overall_misses::cpu0.data 699649 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 318351 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2672 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2379 # number of overall misses -system.l2c.overall_misses::cpu1.inst 49130 # number of overall misses -system.l2c.overall_misses::cpu1.data 248003 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 232724 # number of overall misses -system.l2c.overall_misses::total 1619998 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 1024631500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1063145500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2087777000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 193873000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 194795500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 388668500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 89836611997 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 17865168996 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 107701780993 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 337305500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 317505000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8570748002 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 22562577998 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 57125544763 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 382906000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 336227500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6715379500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 18141536999 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 41393713140 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 155883444402 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 337305500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 317505000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 8570748002 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 112399189995 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 57125544763 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 382906000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 336227500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 6715379500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 36006705995 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 41393713140 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 263585225395 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 337305500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 317505000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 8570748002 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 112399189995 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 57125544763 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 382906000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 336227500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 6715379500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 36006705995 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 41393713140 # number of overall miss cycles -system.l2c.overall_miss_latency::total 263585225395 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 2898844 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2898844 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 233513 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 202648 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 436161 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 51675 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 53551 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 105226 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 709336 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 287540 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 996876 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8932 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6773 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 583277 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 776875 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 620584 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9215 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6913 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 558835 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 722101 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 525360 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 3818865 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8932 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6773 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 583277 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1486211 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 620584 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9215 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6913 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 558835 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1009641 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 525360 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4815741 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8932 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6773 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 583277 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1486211 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 620584 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9215 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6913 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 558835 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1009641 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 525360 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4815741 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.265707 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.305115 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.284017 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.244625 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.210622 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.227320 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.766583 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.422126 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.667227 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.263099 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.328363 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.107181 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.200655 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.512986 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.289962 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.344134 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087915 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.175356 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.442980 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.250036 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.263099 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.328363 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.107181 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.470760 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.512986 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.289962 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.344134 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.087915 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.245635 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.442980 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.336396 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.263099 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.328363 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.107181 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.470760 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.512986 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.289962 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.344134 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.087915 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.245635 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.442980 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.336396 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16514.062147 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17194.376607 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 16853.629003 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15336.840440 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17270.635695 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 16248.683110 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 165212.200118 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 147186.219875 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 161922.745925 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 143534.255319 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 142763.039568 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137096.871233 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 144739.537079 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 179442.014515 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 143303.143713 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141331.441782 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 136685.925097 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143269.788738 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 177866.112391 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 163253.524778 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 143534.255319 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 142763.039568 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 137096.871233 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 160650.826336 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 179442.014515 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 143303.143713 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 141331.441782 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 136685.925097 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 145186.574336 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 177866.112391 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 162707.130129 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 143534.255319 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 142763.039568 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 137096.871233 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 160650.826336 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 179442.014515 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 143303.143713 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 141331.441782 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 136685.925097 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 145186.574336 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 177866.112391 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 162707.130129 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 17532 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 21079.795710 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 246.485529 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 359.766358 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4048.838393 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9854.606144 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15763.557433 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 96.147248 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 123.490081 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3067.505167 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4557.367994 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3831.673436 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.321652 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003761 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.005490 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.061780 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.150369 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.240533 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001467 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001884 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.046806 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.069540 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058467 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.961750 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10787 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 260 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 48331 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1394 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 453 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 8932 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 256 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2970 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5917 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 39033 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.164597 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.737473 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 79030194 # Number of tag accesses +system.l2c.tags.data_accesses 79030194 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 2899125 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2899125 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 179542 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 131751 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 311293 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 44871 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 37587 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 82458 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 177447 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 158953 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 336400 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6841 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4759 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 555678 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 657090 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 315358 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6220 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4455 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 465798 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 550752 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 288275 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2855226 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6841 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4759 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 555678 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 834537 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 315358 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6220 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4455 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 465798 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 709705 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 288275 # number of demand (read+write) hits +system.l2c.demand_hits::total 3191626 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6841 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4759 # number of overall hits +system.l2c.overall_hits::cpu0.inst 555678 # number of overall hits +system.l2c.overall_hits::cpu0.data 834537 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 315358 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6220 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4455 # number of overall hits +system.l2c.overall_hits::cpu1.inst 465798 # number of overall hits +system.l2c.overall_hits::cpu1.data 709705 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 288275 # number of overall hits +system.l2c.overall_hits::total 3191626 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 65170 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 60899 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 126069 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 13497 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 10880 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 24377 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 548373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 111880 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 660253 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3162 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3066 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 64369 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 165419 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 348485 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1778 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1336 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 44941 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 109371 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 194769 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 936696 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3162 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3066 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 64369 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 713792 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 348485 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1778 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1336 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 44941 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 221251 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 194769 # number of demand (read+write) misses +system.l2c.demand_misses::total 1596949 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3162 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3066 # number of overall misses +system.l2c.overall_misses::cpu0.inst 64369 # number of overall misses +system.l2c.overall_misses::cpu0.data 713792 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 348485 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1778 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1336 # number of overall misses +system.l2c.overall_misses::cpu1.inst 44941 # number of overall misses +system.l2c.overall_misses::cpu1.data 221251 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 194769 # number of overall misses +system.l2c.overall_misses::total 1596949 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 1078165500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1115927500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 2194093000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 212502500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 171734000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 384236500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 90582434499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 16447344495 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 107029778994 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 446300000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 433489000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8809361002 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 23863415500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 62552488059 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 257684000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 192911000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6154592500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 15830077997 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 35289320152 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 153829639210 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 446300000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 433489000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 8809361002 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 114445849999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 62552488059 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 257684000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 192911000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 6154592500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 32277422492 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 35289320152 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 260859418204 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 446300000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 433489000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 8809361002 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 114445849999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 62552488059 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 257684000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 192911000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 6154592500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 32277422492 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 35289320152 # number of overall miss cycles +system.l2c.overall_miss_latency::total 260859418204 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 2899125 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2899125 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 244712 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 192650 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 437362 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 58368 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 48467 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 106835 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 725820 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 270833 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 996653 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10003 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7825 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 620047 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 822509 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 663843 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7998 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5791 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 510739 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 660123 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 483044 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 3791922 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 10003 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7825 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 620047 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1548329 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 663843 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 7998 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5791 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 510739 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 930956 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 483044 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4788575 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 10003 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7825 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 620047 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1548329 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 663843 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 7998 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5791 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 510739 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 930956 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 483044 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4788575 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.266313 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.316112 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.288249 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.231240 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.224483 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.228174 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.755522 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.413096 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.662470 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.316105 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.391821 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.103813 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.201115 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.524951 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.222306 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.230703 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087992 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.165683 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.403212 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.247024 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.316105 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.391821 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.103813 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.461008 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.524951 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.222306 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.230703 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.087992 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.237660 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.403212 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.333491 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.316105 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.391821 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.103813 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.461008 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.524951 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.222306 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.230703 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.087992 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.237660 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.403212 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.333491 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16543.892896 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18324.233567 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 17403.905798 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15744.424687 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15784.375000 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 15762.255405 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 165183.979698 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 147008.799562 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 162104.191869 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141144.845035 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141385.844749 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 136857.198372 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 144260.426553 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 179498.365953 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 144929.133858 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 144394.461078 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 136948.276629 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 144737.434942 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 181185.507714 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 164225.788527 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141144.845035 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141385.844749 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 136857.198372 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 160335.013560 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 179498.365953 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 144929.133858 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 144394.461078 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 136948.276629 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 145885.995959 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 181185.507714 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 163348.621781 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141144.845035 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141385.844749 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 136857.198372 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 160335.013560 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 179498.365953 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 144929.133858 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 144394.461078 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 136948.276629 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 145885.995959 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181185.507714 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 163348.621781 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 8828 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 141 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 81 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 124.340426 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 108.987654 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1238890 # number of writebacks -system.l2c.writebacks::total 1238890 # number of writebacks -system.l2c.ReadExReq_mshr_hits::cpu0.data 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 219 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.data 33 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 244 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.data 32 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 528 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 219 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 34 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 244 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 32 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 529 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 219 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 34 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 244 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 32 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 529 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 60450 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 60450 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 62046 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 61831 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 123877 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12641 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11279 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 23920 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 543764 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 121378 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 665142 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2350 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2224 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 62297 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 155851 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 318351 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2672 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2379 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 48886 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 126593 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 232724 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 954327 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 2350 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2224 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 62297 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 699615 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 318351 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2672 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2379 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 48886 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 247971 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 232724 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 1619469 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 2350 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2224 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 62297 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 699615 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 318351 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2672 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2379 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 48886 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 247971 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 232724 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 1619469 # number of overall MSHR misses +system.l2c.writebacks::writebacks 1227229 # number of writebacks +system.l2c.writebacks::total 1227229 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 139 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 160 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 80 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 236 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 179 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 178 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 972 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 139 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 160 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 80 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 236 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 179 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 178 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 972 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 139 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 160 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 80 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 236 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 179 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 178 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 972 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 61997 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 61997 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 65170 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 60899 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 126069 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13497 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10880 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 24377 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 548373 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 111880 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 660253 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3162 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3066 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 64230 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 165259 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 348405 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1778 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1336 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44705 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 109192 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 194591 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 935724 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 3162 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3066 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 64230 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 713632 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 348405 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1778 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1336 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 44705 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 221072 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 194591 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1595977 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 3162 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3066 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 64230 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 713632 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 348405 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1778 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1336 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 44705 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 221072 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 194591 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1595977 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32157 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6297 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 59814 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31964 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 6428 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 38392 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5427 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 59665 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5284 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38225 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 64121 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 65819 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 12725 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 98206 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4564244502 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4544780000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 9109024502 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 967924994 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 862182998 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 1830107992 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 84398895997 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 16651388996 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 101050284993 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 313805500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 295265000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7922359002 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 21000185498 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 53942034763 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 356186000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 312437500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 6197673000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 16871940499 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 39066473140 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 146278359902 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 313805500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 295265000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 7922359002 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 105399081495 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 53942034763 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 356186000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 312437500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 6197673000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 33523329495 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 39066473140 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 247328644895 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 313805500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 295265000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 7922359002 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 105399081495 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 53942034763 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 356186000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 312437500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 6197673000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 33523329495 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 39066473140 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 247328644895 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10711 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 97890 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4609555998 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4294868996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 8904424994 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 994851497 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 800175997 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 1795027494 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 85098254939 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 15328209809 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 100426464748 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 414677007 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 402825012 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 8150526337 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 22190089460 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 59056286181 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 239897519 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 179549008 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5679666806 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 14716146780 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33314353434 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 144344017544 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 414677007 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 402825012 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 8150526337 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 107288344399 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 59056286181 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 239897519 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 179549008 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 5679666806 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 30044356589 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 33314353434 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 244770482292 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 414677007 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 402825012 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 8150526337 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 107288344399 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 59056286181 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 239897519 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 179549008 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 5679666806 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 30044356589 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33314353434 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 244770482292 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5339273500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7124500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 563876500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 8307082500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5257909033 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 701977500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5959886533 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5437993027 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7557000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 463514024 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 8305872051 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5417020065 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 540285518 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5957305583 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10597182533 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7124500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1265854000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 14266969033 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10855013092 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7557000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1003799542 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 14263177634 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.265707 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.305115 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.284017 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.244625 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.210622 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.227320 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.766582 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.422126 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.667226 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.263099 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.328363 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.106805 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.200613 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.512986 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.289962 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.344134 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.087478 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.175312 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.442980 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.249898 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.263099 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.328363 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.106805 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.470737 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.512986 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.289962 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.344134 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.087478 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.245603 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.442980 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.336287 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.263099 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.328363 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.106805 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.470737 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.512986 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.289962 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.344134 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.087478 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.245603 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.442980 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.336287 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73562.268349 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73503.258883 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73532.814824 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76570.286686 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76441.439667 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76509.531438 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 155212.364182 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137186.219875 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 151922.875105 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 133534.255319 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 132763.039568 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127170.794773 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 134745.272716 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169442.014515 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133303.143713 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 126778.075523 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133277.041377 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 153279.075099 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 133534.255319 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 132763.039568 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127170.794773 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 150652.975558 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169442.014515 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133303.143713 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126778.075523 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135190.524275 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 152722.061920 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 133534.255319 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 132763.039568 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127170.794773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 150652.975558 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169442.014515 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133303.143713 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126778.075523 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135190.524275 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 152722.061920 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.266313 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.316112 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.288249 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.231240 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.224483 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228174 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.755522 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.413096 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.662470 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.316105 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.200921 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.165412 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.246768 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.316105 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.460905 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.237468 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.333289 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.316105 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.460905 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.237468 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.333289 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70731.256683 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70524.458464 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70631.360557 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73709.083278 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73545.587960 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73636.111663 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 155183.159891 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137005.808089 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 152103.004073 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 134274.620202 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134773.122390 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 154259.180639 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 150341.274493 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135903.038779 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 153367.174021 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 150341.274493 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135903.038779 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 153367.174021 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166037.674534 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 89546.847705 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138881.908918 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164494.713834 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 109206.207218 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155237.719655 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165399.143105 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112791.044776 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 85408.885941 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139208.448018 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164446.132935 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102249.341030 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155848.412897 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 165268.516290 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 99477.721022 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 145275.940706 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164922.181923 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112791.044776 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 93716.697040 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 145706.176668 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 59814 # Transaction distribution -system.membus.trans_dist::ReadResp 1023090 # Transaction distribution -system.membus.trans_dist::WriteReq 38392 # Transaction distribution -system.membus.trans_dist::WriteResp 38392 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1345584 # Transaction distribution -system.membus.trans_dist::CleanEvict 266165 # Transaction distribution -system.membus.trans_dist::UpgradeReq 443726 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 302861 # Transaction distribution -system.membus.trans_dist::UpgradeResp 156448 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 676664 # Transaction distribution -system.membus.trans_dist::ReadExResp 656494 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 963276 # Transaction distribution +system.membus.trans_dist::ReadReq 59665 # Transaction distribution +system.membus.trans_dist::ReadResp 1004280 # Transaction distribution +system.membus.trans_dist::WriteReq 38225 # Transaction distribution +system.membus.trans_dist::WriteResp 38225 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1333923 # Transaction distribution +system.membus.trans_dist::CleanEvict 260984 # Transaction distribution +system.membus.trans_dist::UpgradeReq 453995 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 297100 # Transaction distribution +system.membus.trans_dist::UpgradeResp 23 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 671706 # Transaction distribution +system.membus.trans_dist::ReadExResp 651282 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 944615 # Transaction distribution system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122562 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5690514 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5839062 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342298 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342298 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6181360 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155669 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5471994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5619910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5857982 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51820 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 182696832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 182904877 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7257216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190162093 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 613313 # Total snoops (count) -system.membus.snoop_fanout::samples 4205672 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 180426240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 180632999 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7268224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 187901223 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 614880 # Total snoops (count) +system.membus.snoop_fanout::samples 4166995 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4205672 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4166995 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4205672 # Request fanout histogram -system.membus.reqLayer0.occupancy 98421997 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4166995 # Request fanout histogram +system.membus.reqLayer0.occupancy 98592998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 53000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21914471 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21315973 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9436458556 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9342770498 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8880795227 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8446463151 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228859415 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45344986 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3858,57 +3859,57 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 12199905 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6623903 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1949036 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 168152 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 152817 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 15335 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 59816 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4662380 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38392 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38392 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4244441 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1619343 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 747362 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 384167 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1131529 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 101 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1137603 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1137603 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4609811 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 12162467 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6606326 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1941011 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 162574 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 148386 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 14188 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 59667 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4643440 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38225 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38225 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4233094 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2736996 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 756317 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 379558 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1135875 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 201 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1140134 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1140134 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4591007 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9241165 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7356268 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16597433 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 283441843 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 210970938 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 494412781 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3322045 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8775737 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.344900 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.478998 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10341744 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7350795 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17692539 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 299067465 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 193620382 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 492687847 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3308925 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8737988 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.345814 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.479035 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5764320 65.68% 65.68% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2996082 34.14% 99.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 15335 0.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5730454 65.58% 65.58% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2993346 34.26% 99.84% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 14188 0.16% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8775737 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9513972562 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8737988 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9497901955 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2693663 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2589298 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5075177047 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5324917465 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4195991011 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3923923162 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 12889 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 12950 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5680 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5465 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |