diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
commit | 607c2772915628c2c67c1c5bfdefaa33ae66a06e (patch) | |
tree | f8f23fd4012f9a0053d65ac91792a7dc61d6baff /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt | |
parent | 71c982ff708cc3adc7c0eccf536fea34c20cc5f0 (diff) | |
download | gem5-607c2772915628c2c67c1c5bfdefaa33ae66a06e.tar.xz |
stats: Update stats to reflect recent changes to floats
Mostly just splitting out the floats ops and corresponding
reads/writes.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt | 6619 |
1 files changed, 3325 insertions, 3294 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 79f2acec9..e5ad0fb86 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.384943 # Number of seconds simulated -sim_ticks 47384942719000 # Number of ticks simulated -final_tick 47384942719000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.384924 # Number of seconds simulated +sim_ticks 47384923997000 # Number of ticks simulated +final_tick 47384923997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146603 # Simulator instruction rate (inst/s) -host_op_rate 172405 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7419029838 # Simulator tick rate (ticks/s) -host_mem_usage 776468 # Number of bytes of host memory used -host_seconds 6386.95 # Real time elapsed on the host -sim_insts 936348150 # Number of instructions simulated -sim_ops 1101141201 # Number of ops (including micro ops) simulated +host_inst_rate 222565 # Simulator instruction rate (inst/s) +host_op_rate 253955 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9938840366 # Simulator tick rate (ticks/s) +host_mem_usage 775220 # Number of bytes of host memory used +host_seconds 4767.65 # Real time elapsed on the host +sim_insts 1061113479 # Number of instructions simulated +sim_ops 1210768532 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 225984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 211072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4210272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 17875336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 22288384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 132032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 98944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3431264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10538960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 15414592 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory -system.physmem.bytes_read::total 74864536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4210272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3431264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7641536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 90448704 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 111296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 112064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3744224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13424584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 13993600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 40000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 28480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2827552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 6560336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 5891392 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 437568 # Number of bytes read from this memory +system.physmem.bytes_read::total 47171096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3744224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2827552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6571776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65473344 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 90469288 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3531 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3298 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 81738 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 279315 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 348256 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2063 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1546 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 53657 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 164684 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 240853 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1185780 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1413261 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 65493928 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1739 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1751 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 74456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 209772 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 218650 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 445 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44224 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 102518 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 92053 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6837 # Number of read requests responded to by this memory +system.physmem.num_reads::total 753070 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1023021 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1415835 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 4454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 88853 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 377237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 470368 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2786 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 72413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 222412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 325306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1579922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 88853 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 72413 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 161265 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1908807 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1025595 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 79017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 283309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 295318 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 138448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 124331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 995487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 79017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59672 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 138689 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1381734 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1909241 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1908807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 4454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 88853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 377671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 470368 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 72413 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 222412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 325306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3489164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1185780 # Number of read requests accepted -system.physmem.writeReqs 1415835 # Number of write requests accepted -system.physmem.readBursts 1185780 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1415835 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 75867200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue -system.physmem.bytesWritten 90467840 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 74864536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 90469288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1382168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1381734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 79017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 283743 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 295318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 138448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 124331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2377655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 753070 # Number of read requests accepted +system.physmem.writeReqs 1025595 # Number of write requests accepted +system.physmem.readBursts 753070 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1025595 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 48174848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue +system.physmem.bytesWritten 65493376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 47171096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65493928 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 74918 # Per bank write bursts -system.physmem.perBankRdBursts::1 82946 # Per bank write bursts -system.physmem.perBankRdBursts::2 75146 # Per bank write bursts -system.physmem.perBankRdBursts::3 74319 # Per bank write bursts -system.physmem.perBankRdBursts::4 73960 # Per bank write bursts -system.physmem.perBankRdBursts::5 83356 # Per bank write bursts -system.physmem.perBankRdBursts::6 71088 # Per bank write bursts -system.physmem.perBankRdBursts::7 75076 # Per bank write bursts -system.physmem.perBankRdBursts::8 69225 # Per bank write bursts -system.physmem.perBankRdBursts::9 91582 # Per bank write bursts -system.physmem.perBankRdBursts::10 63014 # Per bank write bursts -system.physmem.perBankRdBursts::11 68676 # Per bank write bursts -system.physmem.perBankRdBursts::12 68042 # Per bank write bursts -system.physmem.perBankRdBursts::13 71091 # Per bank write bursts -system.physmem.perBankRdBursts::14 73017 # Per bank write bursts -system.physmem.perBankRdBursts::15 69969 # Per bank write bursts -system.physmem.perBankWrBursts::0 88621 # Per bank write bursts -system.physmem.perBankWrBursts::1 92960 # Per bank write bursts -system.physmem.perBankWrBursts::2 88280 # Per bank write bursts -system.physmem.perBankWrBursts::3 90026 # Per bank write bursts -system.physmem.perBankWrBursts::4 89701 # Per bank write bursts -system.physmem.perBankWrBursts::5 97248 # Per bank write bursts -system.physmem.perBankWrBursts::6 87218 # Per bank write bursts -system.physmem.perBankWrBursts::7 89230 # Per bank write bursts -system.physmem.perBankWrBursts::8 86326 # Per bank write bursts -system.physmem.perBankWrBursts::9 88636 # Per bank write bursts -system.physmem.perBankWrBursts::10 82100 # Per bank write bursts -system.physmem.perBankWrBursts::11 87622 # Per bank write bursts -system.physmem.perBankWrBursts::12 86001 # Per bank write bursts -system.physmem.perBankWrBursts::13 87485 # Per bank write bursts -system.physmem.perBankWrBursts::14 85741 # Per bank write bursts -system.physmem.perBankWrBursts::15 86365 # Per bank write bursts +system.physmem.perBankRdBursts::0 46580 # Per bank write bursts +system.physmem.perBankRdBursts::1 53938 # Per bank write bursts +system.physmem.perBankRdBursts::2 49260 # Per bank write bursts +system.physmem.perBankRdBursts::3 49621 # Per bank write bursts +system.physmem.perBankRdBursts::4 42595 # Per bank write bursts +system.physmem.perBankRdBursts::5 51807 # Per bank write bursts +system.physmem.perBankRdBursts::6 43920 # Per bank write bursts +system.physmem.perBankRdBursts::7 48776 # Per bank write bursts +system.physmem.perBankRdBursts::8 40673 # Per bank write bursts +system.physmem.perBankRdBursts::9 65073 # Per bank write bursts +system.physmem.perBankRdBursts::10 36606 # Per bank write bursts +system.physmem.perBankRdBursts::11 43439 # Per bank write bursts +system.physmem.perBankRdBursts::12 41245 # Per bank write bursts +system.physmem.perBankRdBursts::13 45785 # Per bank write bursts +system.physmem.perBankRdBursts::14 46575 # Per bank write bursts +system.physmem.perBankRdBursts::15 46839 # Per bank write bursts +system.physmem.perBankWrBursts::0 64495 # Per bank write bursts +system.physmem.perBankWrBursts::1 70494 # Per bank write bursts +system.physmem.perBankWrBursts::2 68186 # Per bank write bursts +system.physmem.perBankWrBursts::3 67192 # Per bank write bursts +system.physmem.perBankWrBursts::4 60923 # Per bank write bursts +system.physmem.perBankWrBursts::5 66733 # Per bank write bursts +system.physmem.perBankWrBursts::6 61182 # Per bank write bursts +system.physmem.perBankWrBursts::7 63809 # Per bank write bursts +system.physmem.perBankWrBursts::8 61319 # Per bank write bursts +system.physmem.perBankWrBursts::9 65628 # Per bank write bursts +system.physmem.perBankWrBursts::10 58470 # Per bank write bursts +system.physmem.perBankWrBursts::11 62975 # Per bank write bursts +system.physmem.perBankWrBursts::12 59380 # Per bank write bursts +system.physmem.perBankWrBursts::13 62220 # Per bank write bursts +system.physmem.perBankWrBursts::14 64833 # Per bank write bursts +system.physmem.perBankWrBursts::15 65495 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 51113 # Number of times write queue was full causing retry -system.physmem.totGap 47384941205500 # Total gap between requests +system.physmem.numWrRetry 51084 # Number of times write queue was full causing retry +system.physmem.totGap 47384922418500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1164422 # Read request sizes (log2) +system.physmem.readPktSize::6 731712 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1413261 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 492558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 272193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 123866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 77106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 49827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 41505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 35214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 31591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 5210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 3059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1023021 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 370845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 159212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 67904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 40989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 21454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 19383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 16144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 215 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -189,147 +189,148 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26213 # 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Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 153.580618 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.695829 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 199.684011 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 694535 64.13% 64.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 223527 20.64% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 61545 5.68% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27125 2.50% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 21919 2.02% 94.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12312 1.14% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8465 0.78% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6818 0.63% 97.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 26799 2.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1083045 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 67614 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.532168 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 68.484066 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 67610 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 18155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 21368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 29807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 34041 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 6169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 25036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 120369 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 764267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 148.727500 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 100.859518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 194.434520 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 493267 64.54% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 163474 21.39% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 41666 5.45% 91.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17289 2.26% 93.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12509 1.64% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7716 1.01% 96.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5337 0.70% 96.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4250 0.56% 97.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 18759 2.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 764267 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 44107 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.065908 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 84.736057 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 44102 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 67614 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 67614 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.906321 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.453992 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 533.973047 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-2047 67611 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 44107 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 44107 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.201170 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.952947 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 661.116222 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-2047 44104 99.99% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::12288-14335 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::43008-45055 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::129024-131071 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 67614 # Writes before turning the bus around for reads -system.physmem.totQLat 72498378118 # Total ticks spent queuing -system.physmem.totMemAccLat 94725096868 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5927125000 # Total ticks spent in databus transfers -system.physmem.avgQLat 61158.13 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 44107 # Writes before turning the bus around for reads +system.physmem.totQLat 41283708010 # Total ticks spent queuing +system.physmem.totMemAccLat 55397433010 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3763660000 # Total ticks spent in databus transfers +system.physmem.avgQLat 54845.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 79908.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.60 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.91 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.91 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 73595.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.38 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing -system.physmem.readRowHits 894792 # Number of row buffer hits during reads -system.physmem.writeRowHits 621147 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.94 # Row buffer hit rate for writes -system.physmem.avgGap 18213663.90 # Average gap between requests -system.physmem.pageHitRate 58.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4041154320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2147920665 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4361176260 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3775542480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 33222521280.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 42262106220 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1577144160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 67404809070 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 44351104800 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 11290594038405 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11493753562350 # Total energy per rank (pJ) -system.physmem_0.averagePower 242.561305 # Core power per rank (mW) -system.physmem_0.totalIdleTime 47288119152834 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 2641670410 # Time in different power states -system.physmem_0.memoryStateTime::REF 14105156000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 47024804557250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 115497548988 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80076687506 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 147817098846 # Time in different power states -system.physmem_1.actEnergy 3691794120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1962235110 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4102758240 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3603240720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 31839581280.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 42875044890 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1564584000 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 59886050220 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 43118785440 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 11295073117425 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11487733544595 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.434260 # Core power per rank (mW) -system.physmem_1.totalIdleTime 47286801320918 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 2657158504 # Time in different power states -system.physmem_1.memoryStateTime::REF 13520630000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 47043190241000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 112288389331 # Time in different power states -system.physmem_1.memoryStateTime::ACT 81956603828 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 131329696337 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.78 # Average write queue length when enqueuing +system.physmem.readRowHits 561323 # Number of row buffer hits during reads +system.physmem.writeRowHits 450469 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 44.02 # Row buffer hit rate for writes +system.physmem.avgGap 26640723.47 # Average gap between requests +system.physmem.pageHitRate 56.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2854700520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1517297925 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2759588580 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2730133080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29211995280.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 33494587950 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1472320320 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 56725165950 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 41153148000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11302922668065 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11474856149160 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.162595 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47307603847909 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 2604858642 # Time in different power states +system.physmem_0.memoryStateTime::REF 12408932000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 47076037433500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 107169572536 # Time in different power states +system.physmem_0.memoryStateTime::ACT 62306306199 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 124396894123 # Time in different power states +system.physmem_1.actEnergy 2602215840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1383095340 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2614917900 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2611670400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 28356416400.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 34195829880 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1463733600 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 50772105900 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 40848981120 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11305996104720 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11470859465250 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.078250 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47306089548027 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 2606555105 # Time in different power states +system.physmem_1.memoryStateTime::REF 12048152000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 47088369465500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 106377666151 # Time in different power states +system.physmem_1.memoryStateTime::ACT 64179741868 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 111342416376 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -356,30 +357,30 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 139745078 # Number of BP lookups -system.cpu0.branchPred.condPredicted 92256746 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6767345 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 98774130 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 61692324 # Number of BTB hits +system.cpu0.branchPred.lookups 171085788 # Number of BP lookups +system.cpu0.branchPred.condPredicted 118750961 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6834189 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 131203024 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 82797286 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 62.457978 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 19130272 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 187780 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4236971 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2716946 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1520025 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 386103 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 63.106233 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 18455974 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 190741 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4318211 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2658051 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1660160 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 412902 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -409,87 +410,89 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 642249 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 642249 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 14371 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 105891 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 311173 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 331076 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2394.451727 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 14284.464178 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 328283 99.16% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 2041 0.62% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 492 0.15% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 140 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 49 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 15 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 532616 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 532616 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9645 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 81431 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 247073 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 285543 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2264.919819 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 12542.152959 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 283669 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1336 0.47% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 422 0.15% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 71 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 12 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 18 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 331076 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 352054 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 21918.096372 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18874.221671 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 17893.290078 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 347548 98.72% 98.72% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2975 0.85% 99.57% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 632 0.18% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 594 0.17% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 153 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 118 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 25 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 352054 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 539733877528 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.599244 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.552867 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 538149503028 99.71% 99.71% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 904434000 0.17% 99.87% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 320975500 0.06% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 139201000 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 110066000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 60836000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 22060500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 25840500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 959500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 539733877528 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 105891 88.05% 88.05% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 14371 11.95% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 120262 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 642249 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 285543 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 266524 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 21513.586019 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18398.741629 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 18436.018606 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 263851 99.00% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1863 0.70% 99.70% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 357 0.13% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 245 0.09% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 96 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 28 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 12 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 57 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::720896-786431 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 266524 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 526829631640 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.594347 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.546107 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 525653507140 99.78% 99.78% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 581220000 0.11% 99.89% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 279235500 0.05% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 118625000 0.02% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 95795000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 61233500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 16684500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 22309000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 986000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 36000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 526829631640 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 81432 89.41% 89.41% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9645 10.59% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 91077 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 532616 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 642249 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 120262 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 532616 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 91077 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 120262 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 762511 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 91077 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 623693 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 102850435 # DTB read hits -system.cpu0.dtb.read_misses 467880 # DTB read misses -system.cpu0.dtb.write_hits 83320332 # DTB write hits -system.cpu0.dtb.write_misses 174369 # DTB write misses -system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 121664189 # DTB read hits +system.cpu0.dtb.read_misses 378617 # DTB read misses +system.cpu0.dtb.write_hits 79494049 # DTB write hits +system.cpu0.dtb.write_misses 153999 # DTB write misses +system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 42516 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 599 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7036 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 38825 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36225 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 277 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 5846 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 38961 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 103318315 # DTB read accesses -system.cpu0.dtb.write_accesses 83494701 # DTB write accesses +system.cpu0.dtb.perms_faults 36132 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 122042806 # DTB read accesses +system.cpu0.dtb.write_accesses 79648048 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 186170767 # DTB hits -system.cpu0.dtb.misses 642249 # DTB misses -system.cpu0.dtb.accesses 186813016 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 201158238 # DTB hits +system.cpu0.dtb.misses 532616 # DTB misses +system.cpu0.dtb.accesses 201690854 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -519,1177 +522,1186 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 84160 # Table walker walks requested -system.cpu0.itb.walker.walksLong 84160 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1044 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58792 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10193 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 73967 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1726.006192 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 15527.215020 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-65535 73402 99.24% 99.24% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-131071 457 0.62% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-196607 56 0.08% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-262143 12 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-327679 7 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-393215 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-458751 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::524288-589823 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::589824-655359 22 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 73967 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 70029 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 27234.188693 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23423.171681 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 26401.977199 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 67612 96.55% 96.55% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1634 2.33% 98.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 479 0.68% 99.57% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 184 0.26% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 51 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 27 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 16 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 21 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 84620 # Table walker walks requested +system.cpu0.itb.walker.walksLong 84620 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1064 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60290 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 9899 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 74721 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1224.749401 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 11693.335691 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-65535 74465 99.66% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-131071 211 0.28% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-196607 17 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-327679 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::589824-655359 13 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 74721 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 71253 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25715.211991 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 22899.199736 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 22689.495972 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 69781 97.93% 97.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 978 1.37% 99.31% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 312 0.44% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 90 0.13% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 29 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 23 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 70029 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 423766533036 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.875739 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.330248 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 52705402108 12.44% 12.44% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 371016436928 87.55% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 42131000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1939000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 624000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 423766533036 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 58792 98.26% 98.26% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1044 1.74% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 59836 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 71253 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 385068972872 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.863923 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.343128 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 52431106232 13.62% 13.62% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 332607446140 86.38% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 28719500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1617500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 83500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 385068972872 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 60290 98.27% 98.27% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1064 1.73% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 61354 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84160 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84160 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84620 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84620 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59836 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59836 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 143996 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 220066677 # ITB inst hits -system.cpu0.itb.inst_misses 84160 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61354 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61354 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 145974 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 247137553 # ITB inst hits +system.cpu0.itb.inst_misses 84620 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 30584 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 38825 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26024 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 203568 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 210277 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 220150837 # ITB inst accesses -system.cpu0.itb.hits 220066677 # DTB hits -system.cpu0.itb.misses 84160 # DTB misses -system.cpu0.itb.accesses 220150837 # DTB accesses -system.cpu0.numPwrStateTransitions 10070 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 5035 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 9333517887.918768 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 154504325024.809692 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3827 76.01% 76.01% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 1181 23.46% 99.46% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 7 0.14% 99.60% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.62% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.06% 99.68% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.74% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 13 0.26% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 247222173 # ITB inst accesses +system.cpu0.itb.hits 247137553 # DTB hits +system.cpu0.itb.misses 84620 # DTB misses +system.cpu0.itb.accesses 247222173 # DTB accesses +system.cpu0.numPwrStateTransitions 10024 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 5012 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 9377758605.326616 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 105865716307.531311 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3741 74.64% 74.64% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1240 24.74% 99.38% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.40% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 4 0.08% 99.48% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.50% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.52% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.54% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 3 0.06% 99.60% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.64% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 18 0.36% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 6914082505000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 5035 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 390680153329 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46994262565671 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 781361530 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 1988782107984 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 5012 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 383597867103 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 47001326129897 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 767196996 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 89977379 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 618690334 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 139745078 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 83539542 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 647313928 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14578052 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1993554 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 302966 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 5990682 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 771527 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 852599 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 219863904 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1701332 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 27447 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 754491661 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.959990 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.215112 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 91423789 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 677610005 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 171085788 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 103911311 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 634233277 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14647700 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1877525 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 301361 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 5874017 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 723644 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 823593 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 246927402 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1755267 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 27806 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 742581056 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.048226 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.216568 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 407421945 54.00% 54.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 135112889 17.91% 71.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 46679176 6.19% 78.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 165277651 21.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 362128339 48.77% 48.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 152866679 20.59% 69.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 57232327 7.71% 77.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 170353711 22.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 754491661 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.178848 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.791811 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 107863691 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 373653702 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 228590583 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 39162463 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5221222 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 20030707 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2107727 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 640747867 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23352656 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5221222 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 144093047 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 59069591 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 244366962 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 230957488 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 70783351 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 623359263 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6158447 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 11021555 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 440656 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 940490 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 33921586 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11494 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 594689945 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 962815337 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 736259751 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 682623 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 536299590 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 58390349 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16178274 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14135285 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 78489785 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 102915286 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 86617273 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9593817 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8133429 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 600294247 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16347683 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 605471525 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2720884 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 54918264 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 35662191 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 285806 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 754491661 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.802489 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.061507 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 742581056 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.223001 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.883228 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 106308771 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 322958086 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 273818410 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 34299444 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5196345 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 25584090 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2168541 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 698124632 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23697866 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5196345 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 140217201 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 48265126 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 214765524 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 273791275 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 60345585 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 681004210 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6177353 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 9309706 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 255993 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 440694 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 28265124 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11577 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 651054888 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1024843126 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 780850511 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 751131 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 593650334 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 57404539 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 14068671 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 12084501 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 69307711 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 122420852 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 82711928 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 8893855 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 7669271 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 660071199 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 14190254 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 662533207 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2711266 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 53711593 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 34745859 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 272694 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 742581056 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.892203 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.090645 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 423297632 56.10% 56.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 139867580 18.54% 74.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 116427415 15.43% 90.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 66852551 8.86% 98.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8040953 1.07% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5530 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 387058469 52.12% 52.12% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 139937745 18.84% 70.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 131660547 17.73% 88.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 76428143 10.29% 98.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 7490821 1.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5331 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 754491661 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 742581056 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 62202700 45.10% 45.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 65869 0.05% 45.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 12866 0.01% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 27 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 36951420 26.79% 71.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 38701650 28.06% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 66589128 48.32% 48.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 76488 0.06% 48.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 21054 0.02% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 7 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 34108431 24.75% 73.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 36653931 26.60% 99.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 35680 0.03% 99.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 336881 0.24% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 413123878 68.23% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1535668 0.25% 68.49% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 80204 0.01% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 6 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 45354 0.01% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 106103331 17.52% 86.03% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 84583031 13.97% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 19 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 455471856 68.75% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1439073 0.22% 68.96% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 77169 0.01% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 26 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 52155 0.01% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 4 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 124717383 18.82% 87.81% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 80374226 12.13% 99.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 54363 0.01% 99.95% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 346932 0.05% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 605471525 # Type of FU issued -system.cpu0.iq.rate 0.774893 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 137934532 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.227813 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2104985611 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 671273361 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 587796479 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1104514 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 436534 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 408765 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 742719141 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 686865 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2818576 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 662533207 # Type of FU issued +system.cpu0.iq.rate 0.863576 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 137821600 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.208022 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2206895899 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 727628917 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 645910972 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1284434 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 480253 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 448459 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 799528739 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 826049 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2613047 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12827708 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17934 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 150945 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5597965 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12294694 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 15978 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 137291 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5350030 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2832815 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4794177 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2543221 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4059606 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5221222 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8523162 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 2018525 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 616773219 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5196345 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6516939 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1752683 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 674395512 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 102915286 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 86617273 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13889545 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 69101 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1866975 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 150945 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 1955799 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3092868 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5048667 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 597424685 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 102845914 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7413191 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 122420852 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 82711928 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 11855960 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 50620 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1645630 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 137291 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 1918568 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3145797 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5064365 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 654555035 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 121653240 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7451061 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 131289 # number of nop insts executed -system.cpu0.iew.exec_refs 186166471 # number of memory reference insts executed -system.cpu0.iew.exec_branches 112308682 # Number of branches executed -system.cpu0.iew.exec_stores 83320557 # Number of stores executed -system.cpu0.iew.exec_rate 0.764594 # Inst execution rate -system.cpu0.iew.wb_sent 588977240 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 588205244 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 286222957 # num instructions producing a value -system.cpu0.iew.wb_consumers 469478170 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.752795 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609662 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 48006701 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 16061877 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4699541 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 745382545 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.753605 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.560188 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 134059 # number of nop insts executed +system.cpu0.iew.exec_refs 201144943 # number of memory reference insts executed +system.cpu0.iew.exec_branches 144279686 # Number of branches executed +system.cpu0.iew.exec_stores 79491703 # Number of stores executed +system.cpu0.iew.exec_rate 0.853177 # Inst execution rate +system.cpu0.iew.wb_sent 647087647 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 646359431 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 309251056 # num instructions producing a value +system.cpu0.iew.wb_consumers 520070148 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.842495 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.594633 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 46740214 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 13917560 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4706684 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 733649612 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.845840 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.553610 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 499589625 67.02% 67.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 127846284 17.15% 84.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 54154407 7.27% 91.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 18022208 2.42% 93.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 12958039 1.74% 95.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8991225 1.21% 96.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6101110 0.82% 97.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3650180 0.49% 98.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14069467 1.89% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 452365639 61.66% 61.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 136210339 18.57% 80.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 77415879 10.55% 90.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 24022740 3.27% 94.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 12736407 1.74% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 8516612 1.16% 96.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 5825168 0.79% 97.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3494792 0.48% 98.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 13062036 1.78% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 745382545 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 478330111 # Number of instructions committed -system.cpu0.commit.committedOps 561723659 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 733649612 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 541241308 # Number of instructions committed +system.cpu0.commit.committedOps 620549845 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 171106885 # Number of memory references committed -system.cpu0.commit.loads 90087577 # Number of loads committed -system.cpu0.commit.membars 3940521 # Number of memory barriers committed -system.cpu0.commit.branches 106744395 # Number of branches committed -system.cpu0.commit.fp_insts 400838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 515553500 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14275050 # Number of function calls committed. +system.cpu0.commit.refs 187488051 # Number of memory references committed +system.cpu0.commit.loads 110126156 # Number of loads committed +system.cpu0.commit.membars 3681828 # Number of memory barriers committed +system.cpu0.commit.branches 138866442 # Number of branches committed +system.cpu0.commit.fp_insts 440023 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 558745881 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13735984 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 389225467 69.29% 69.29% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1288146 0.23% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 63590 0.01% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 39571 0.01% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 90087577 16.04% 85.58% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 81019308 14.42% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 431741221 69.57% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1213492 0.20% 69.77% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 61406 0.01% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 45675 0.01% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 110075333 17.74% 87.53% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77018370 12.41% 99.94% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemRead 50823 0.01% 99.94% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemWrite 343525 0.06% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 561723659 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14069467 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1336864700 # The number of ROB reads -system.cpu0.rob.rob_writes 1228532736 # The number of ROB writes -system.cpu0.timesIdled 1001309 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26869869 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93988523944 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 478330111 # Number of Instructions Simulated -system.cpu0.committedOps 561723659 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.633519 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.633519 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.612175 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.612175 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 705719528 # number of integer regfile reads -system.cpu0.int_regfile_writes 419138035 # number of integer regfile writes -system.cpu0.fp_regfile_reads 669802 # number of floating regfile reads -system.cpu0.fp_regfile_writes 321532 # number of floating regfile writes -system.cpu0.cc_regfile_reads 129631161 # number of cc regfile reads -system.cpu0.cc_regfile_writes 130314957 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1341639409 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16172326 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6359267 # number of replacements -system.cpu0.dcache.tags.tagsinuse 478.495579 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 158196405 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6359779 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 24.874513 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 620549845 # Class of committed instruction +system.cpu0.commit.bw_lim_events 13062036 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1383927534 # The number of ROB reads +system.cpu0.rob.rob_writes 1343471696 # The number of ROB writes +system.cpu0.timesIdled 977066 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 24615940 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 94002651032 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 541241308 # Number of Instructions Simulated +system.cpu0.committedOps 620549845 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.417477 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.417477 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.705479 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.705479 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 749870098 # number of integer regfile reads +system.cpu0.int_regfile_writes 449143556 # number of integer regfile writes +system.cpu0.fp_regfile_reads 735783 # number of floating regfile reads +system.cpu0.fp_regfile_writes 351380 # number of floating regfile writes +system.cpu0.cc_regfile_reads 158312331 # number of cc regfile reads +system.cpu0.cc_regfile_writes 158973081 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1390796279 # number of misc regfile reads +system.cpu0.misc_regfile_writes 13965731 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5697124 # number of replacements +system.cpu0.dcache.tags.tagsinuse 508.351019 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 176571011 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5697636 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.990223 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2049282000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.495579 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934562 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.934562 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.351019 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992873 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.992873 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 355337560 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 355337560 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 83119639 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83119639 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 70042361 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 70042361 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 205739 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 205739 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 143941 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 143941 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1893040 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1893040 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1948071 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1948071 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153305941 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153305941 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153511680 # number of overall hits -system.cpu0.dcache.overall_hits::total 153511680 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7167523 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7167523 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7883078 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7883078 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 755741 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 755741 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796292 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 796292 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 289192 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 289192 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197314 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 197314 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 15846893 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 15846893 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 16602634 # number of overall misses -system.cpu0.dcache.overall_misses::total 16602634 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 116616484000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 116616484000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 160918615442 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 160918615442 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 30600076090 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 30600076090 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4458676000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4458676000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4713253000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4713253000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2519000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2519000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 308135175532 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 308135175532 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 308135175532 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 308135175532 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 90287162 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 90287162 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77925439 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77925439 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 961480 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 961480 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 940233 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 940233 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2182232 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2182232 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2145385 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2145385 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 169152834 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 169152834 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 170114314 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 170114314 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.079386 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.079386 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101162 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.101162 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.786018 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.786018 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.846909 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.846909 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132521 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132521 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.091971 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.091971 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.093684 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.093684 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097597 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097597 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16270.123444 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16270.123444 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20413.170521 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20413.170521 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 38428.209865 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 38428.209865 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15417.701734 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15417.701734 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23887.068328 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23887.068328 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 387310320 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 387310320 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 104266262 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 104266262 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67643317 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 67643317 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 201589 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 201589 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 157769 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 157769 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1740953 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1740953 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1780734 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1780734 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 172067348 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 172067348 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 172268937 # number of overall hits +system.cpu0.dcache.overall_hits::total 172268937 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6301527 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6301527 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 6793475 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 6793475 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 634052 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 634052 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 800857 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 800857 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 257653 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 257653 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 179906 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 179906 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 13895859 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 13895859 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 14529911 # number of overall misses +system.cpu0.dcache.overall_misses::total 14529911 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 95042221000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 95042221000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 131968145043 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 131968145043 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29372616680 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 29372616680 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3694169500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3694169500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4281937500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4281937500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3493500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3493500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 256382982723 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 256382982723 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 256382982723 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 256382982723 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 110567789 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 110567789 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74436792 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74436792 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 835641 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 835641 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 958626 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 958626 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1998606 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1998606 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1960640 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1960640 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 185963207 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 185963207 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 186798848 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 186798848 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.056992 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.056992 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.091265 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.091265 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.758761 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.758761 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.835422 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.835422 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.128916 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.128916 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.091759 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.091759 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.074724 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.074724 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.077784 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.077784 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15082.411136 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15082.411136 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19425.720275 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19425.720275 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36676.481170 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36676.481170 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14337.770179 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14337.770179 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23800.971063 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23800.971063 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19444.516697 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19444.516697 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18559.415062 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18559.415062 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9297521 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 24817691 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 744023 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 779199 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.496282 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 31.850260 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6359403 # number of writebacks -system.cpu0.dcache.writebacks::total 6359403 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3686639 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3686639 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6327255 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6327255 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4271 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4271 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 148971 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 148971 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 10018165 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 10018165 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 10018165 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 10018165 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3480884 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3480884 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1555823 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1555823 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 748893 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 748893 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792021 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 792021 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140221 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140221 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197311 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 197311 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5828728 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5828728 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6577621 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6577621 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16980 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16980 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18801 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18801 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35781 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 35781 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 53164892500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 53164892500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34944889021 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34944889021 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18458336500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18458336500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 29638184090 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 29638184090 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1982757000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1982757000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4516003000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4516003000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2458000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2458000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 117747965611 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 117747965611 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 136206302111 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 136206302111 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3133590500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3133590500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3133590500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3133590500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038553 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038553 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019966 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019966 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.778896 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.778896 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.842367 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.842367 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064256 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064256 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.091970 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.091970 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034458 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.034458 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038666 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.038666 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15273.388168 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15273.388168 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22460.709876 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22460.709876 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24647.495036 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24647.495036 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 37420.957386 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 37420.957386 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14140.228639 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14140.228639 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22887.740673 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22887.740673 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18450.315502 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18450.315502 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17645.186039 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17645.186039 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8869783 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 19194961 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 737578 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 651751 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.025553 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 29.451372 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 5697132 # number of writebacks +system.cpu0.dcache.writebacks::total 5697132 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3191836 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3191836 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5417328 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 5417328 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4607 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4607 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 132998 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 132998 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 8613771 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 8613771 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 8613771 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 8613771 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3109691 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3109691 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1376147 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1376147 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 627210 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 627210 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 796250 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 796250 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 124655 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 124655 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 179906 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 179906 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5282088 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5282088 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5909298 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5909298 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16022 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16022 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17403 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17403 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33425 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 33425 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44727315000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44727315000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29679279164 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29679279164 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15040987500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15040987500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28394000680 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28394000680 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1654283000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1654283000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4102116500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4102116500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3408500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3408500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102800594844 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 102800594844 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 117841582344 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 117841582344 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2952800500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2952800500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2952800500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2952800500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028125 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028125 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750574 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.750574 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.830616 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.830616 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062371 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062371 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.091759 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.091759 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028404 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028404 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031635 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14383.202382 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14383.202382 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21566.939552 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21566.939552 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23980.783948 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23980.783948 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35659.655485 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35659.655485 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13270.891661 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13270.891661 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22801.443532 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22801.443532 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20201.314182 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20201.314182 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20707.532725 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20707.532725 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184545.965842 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184545.965842 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87576.940276 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87576.940276 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 6086800 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.960315 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 213393241 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6087312 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.055414 # Average number of references to valid blocks. +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19462.113248 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19462.113248 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19941.722747 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19941.722747 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184296.623393 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184296.623393 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88341.077038 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88341.077038 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 6253789 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.960237 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 240286309 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6254301 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 38.419371 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 13476237000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960315 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960237 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999922 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 445759262 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 445759262 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 213393241 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 213393241 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 213393241 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 213393241 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 213393241 # number of overall hits -system.cpu0.icache.overall_hits::total 213393241 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6442715 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6442715 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6442715 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6442715 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6442715 # number of overall misses -system.cpu0.icache.overall_misses::total 6442715 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71477790896 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 71477790896 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 71477790896 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 71477790896 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 71477790896 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 71477790896 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 219835956 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 219835956 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 219835956 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 219835956 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 219835956 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 219835956 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029307 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029307 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029307 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029307 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029307 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029307 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11094.358651 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 11094.358651 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11094.358651 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11094.358651 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11094.358651 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11094.358651 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10557387 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 2753 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 752829 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.023619 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 196.642857 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 6086800 # number of writebacks -system.cpu0.icache.writebacks::total 6086800 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355365 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 355365 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 355365 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 355365 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 355365 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 355365 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6087350 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6087350 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6087350 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6087350 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6087350 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6087350 # number of overall MSHR misses +system.cpu0.icache.tags.tag_accesses 500053900 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 500053900 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 240286309 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 240286309 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 240286309 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 240286309 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 240286309 # number of overall hits +system.cpu0.icache.overall_hits::total 240286309 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6613282 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6613282 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6613282 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6613282 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6613282 # number of overall misses +system.cpu0.icache.overall_misses::total 6613282 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 70780975211 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 70780975211 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 70780975211 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 70780975211 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 70780975211 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 70780975211 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 246899591 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 246899591 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 246899591 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 246899591 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 246899591 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 246899591 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.026785 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.026785 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.026785 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.026785 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.026785 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.026785 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10702.851506 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10702.851506 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10702.851506 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10702.851506 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10702.851506 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10702.851506 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 10321318 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 2209 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 763925 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.510905 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 169.923077 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 6253789 # number of writebacks +system.cpu0.icache.writebacks::total 6253789 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 358564 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 358564 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 358564 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 358564 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 358564 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 358564 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6254718 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6254718 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6254718 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6254718 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6254718 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6254718 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64448796094 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 64448796094 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64448796094 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 64448796094 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64448796094 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 64448796094 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 63975689306 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 63975689306 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 63975689306 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 63975689306 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 63975689306 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 63975689306 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2027158498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 2027158498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027690 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027690 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027690 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10587.332106 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10587.332106 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10587.332106 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.025333 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.025333 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.025333 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.025333 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.025333 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.025333 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10228.389083 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10228.389083 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10228.389083 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10228.389083 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10228.389083 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10228.389083 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95203.047856 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95203.047856 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8595677 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8603285 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 6909 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7458642 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7464953 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 5714 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1123339 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2781248 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15839.093178 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 10966307 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2797118 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.920574 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1000455 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2364779 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15742.421414 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 10647963 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2380148 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.473656 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 2357977000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15519.164563 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 33.011471 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 18.049668 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000001 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 268.867475 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.947215 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002015 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001102 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016410 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.966742 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 337 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15450 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 131 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 116 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 88 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1708 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7197 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4776 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1564 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020569 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.942993 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 434183760 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 434183760 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 639992 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 185315 # 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mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.087084 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238228 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.146934 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035613 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049939 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.087084 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238228 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229330 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34997.108322 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65391.691488 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18519.906505 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18519.906505 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15371.196205 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15371.196205 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400100 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400100 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50363.819503 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50363.819503 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31122.206006 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35189.856297 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35189.856297 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36508.154280 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36508.154280 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38296.878290 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36107.230903 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38296.878290 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45177.276679 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.208866 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25036.573820 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32637.001403 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27560.521849 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49377.061838 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49377.061838 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18677.903265 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18677.903265 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15284.116510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15284.116510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 461750 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461750 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 46954.415799 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 46954.415799 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 30668.714771 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30668.714771 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32335.749707 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32335.749707 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36894.990200 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36894.990200 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25036.573820 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32637.001403 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30668.714771 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35490.117793 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33867.990204 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25036.573820 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32637.001403 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30668.714771 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35490.117793 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49377.061838 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38466.702068 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176515.871614 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127105.256970 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176269.598053 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125730.979499 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83766.230681 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85234.949364 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 25828303 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13287358 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1712 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 676521 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 676518 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 990165 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11537181 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 18801 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 18801 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5966642 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8286555 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1378403 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1136481 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 480580 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352407 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 530357 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1327096 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1303956 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6087350 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5339261 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 842479 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 790170 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18304055 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20435509 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 413815 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1398403 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 40551782 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 779484304 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 775974521 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1575256 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5307368 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1562341449 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5999180 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 122789024 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 19760108 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.053277 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.224586 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 84493.388182 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85742.379107 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 24756799 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12708263 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2196 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 629051 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 629043 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 8 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 884546 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11093405 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 17403 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 17403 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5225908 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8238069 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1170453 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 945799 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 463366 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 326275 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 490425 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 190 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1168917 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1146769 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6254718 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4769163 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 850255 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 794480 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18805406 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18368662 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 418571 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1191985 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 38784624 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 800859216 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 691176446 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1598432 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4508184 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1498142278 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5240375 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 104025792 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 18364082 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.052502 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.223039 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 18707349 94.67% 94.67% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 1052756 5.33% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 17399941 94.75% 94.75% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 964133 5.25% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 8 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 19760108 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 25687014453 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 18364082 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 24622778944 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 182391125 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 185315667 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9158694684 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9409532092 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9158841551 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8142032744 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 217386526 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 219209106 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 735766915 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 629194022 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 134369829 # Number of BP lookups -system.cpu1.branchPred.condPredicted 89463085 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6609561 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 94230263 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 58109960 # Number of BTB hits +system.cpu1.branchPred.lookups 166724968 # Number of BP lookups +system.cpu1.branchPred.condPredicted 126846962 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6061099 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 131629441 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 75453810 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 61.668044 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17839939 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 183627 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4347444 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2695405 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1652039 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 417102 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 57.322898 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16000678 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 166104 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3768010 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2280408 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1487602 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 378018 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1719,86 +1731,84 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 561952 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 561952 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11814 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 88087 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 261651 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 300301 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2363.057399 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 13317.227915 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 298048 99.25% 99.25% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1567 0.52% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 436 0.15% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 167 0.06% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 40 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 300301 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 287935 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 21029.369476 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18280.568505 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15111.837725 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 285795 99.26% 99.26% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1436 0.50% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 377 0.13% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 181 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 86 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 11 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 16 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 287935 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 466714959496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.597643 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.555516 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 465490623496 99.74% 99.74% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 621983000 0.13% 99.87% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 266845500 0.06% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 131382500 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 96036000 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 60845000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 18797500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 27878000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 546500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 22000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 466714959496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 88088 88.17% 88.17% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11814 11.83% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 99902 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 561952 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 467692 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 467692 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8751 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 70596 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 217424 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 250268 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2074.929675 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 11460.901897 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 248915 99.46% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 899 0.36% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 341 0.14% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 97 0.04% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 250268 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 236712 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20830.925344 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18161.943529 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14226.641322 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 235430 99.46% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1000 0.42% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 142 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 87 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 6 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 6 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 38 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 236712 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 410863041148 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.552097 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.557280 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 409906147648 99.77% 99.77% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 459057000 0.11% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 219368000 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 102318000 0.02% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 84455000 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 58029500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 14454500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 18772000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 430000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 410863041148 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 70596 88.97% 88.97% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8751 11.03% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 79347 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 467692 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 561952 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 99902 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 467692 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 79347 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 99902 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 661854 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 79347 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 547039 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 97791245 # DTB read hits -system.cpu1.dtb.read_misses 385118 # DTB read misses -system.cpu1.dtb.write_hits 81245431 # DTB write hits -system.cpu1.dtb.write_misses 176834 # DTB write misses -system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 135065828 # DTB read hits +system.cpu1.dtb.read_misses 329885 # DTB read misses +system.cpu1.dtb.write_hits 69791052 # DTB write hits +system.cpu1.dtb.write_misses 137807 # DTB write misses +system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36850 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 268 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6109 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 38825 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36136 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 592 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 4990 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 40755 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 98176363 # DTB read accesses -system.cpu1.dtb.write_accesses 81422265 # DTB write accesses +system.cpu1.dtb.perms_faults 39336 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 135395713 # DTB read accesses +system.cpu1.dtb.write_accesses 69928859 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 179036676 # DTB hits -system.cpu1.dtb.misses 561952 # DTB misses -system.cpu1.dtb.accesses 179598628 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 204856880 # DTB hits +system.cpu1.dtb.misses 467692 # DTB misses +system.cpu1.dtb.accesses 205324572 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1828,1166 +1838,1181 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 84407 # Table walker walks requested -system.cpu1.itb.walker.walksLong 84407 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1027 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60740 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 10156 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 74251 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1057.238286 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8622.114888 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 74015 99.68% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 199 0.27% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 18 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 74251 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 71923 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24988.821378 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22597.090075 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18666.984039 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 70820 98.47% 98.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 715 0.99% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 265 0.37% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 63 0.09% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 24 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 78571 # Table walker walks requested +system.cpu1.itb.walker.walksLong 78571 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 897 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57010 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9455 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 69116 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 778.444933 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 6785.315207 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 69062 99.92% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 44 0.06% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::589824-655359 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69116 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 67362 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24032.236276 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22252.228108 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 15053.113927 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 66909 99.33% 99.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 314 0.47% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 86 0.13% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 23 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 6 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 71923 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 410850107648 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.878728 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.326631 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 49848543788 12.13% 12.13% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 360979116860 87.86% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 21177000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1227500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 42500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 410850107648 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 60740 98.34% 98.34% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 1027 1.66% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 61767 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::589824-655359 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 67362 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 372208258984 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.850822 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.356391 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 55541061216 14.92% 14.92% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 316652457768 85.07% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 13820000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 844000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 76000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 372208258984 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 57010 98.45% 98.45% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 897 1.55% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 57907 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 84407 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 84407 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 78571 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 78571 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61767 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61767 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 146174 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 210802915 # ITB inst hits -system.cpu1.itb.inst_misses 84407 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57907 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 57907 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 136478 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 233650950 # ITB inst hits +system.cpu1.itb.inst_misses 78571 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26222 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 38825 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25813 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 208943 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 177997 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 210887322 # ITB inst accesses -system.cpu1.itb.hits 210802915 # DTB hits -system.cpu1.itb.misses 84407 # DTB misses -system.cpu1.itb.accesses 210887322 # DTB accesses -system.cpu1.numPwrStateTransitions 27667 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 13834 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 3399006591.183533 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 87524078188.715500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3453 24.96% 24.96% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 10352 74.83% 99.79% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.04% 99.83% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 233729521 # ITB inst accesses +system.cpu1.itb.hits 233650950 # DTB hits +system.cpu1.itb.misses 78571 # DTB misses +system.cpu1.itb.accesses 233729521 # DTB accesses +system.cpu1.numPwrStateTransitions 26654 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 13327 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3530319846.850679 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 118121656427.394104 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3111 23.34% 23.34% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 10193 76.48% 99.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.91% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.92% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.94% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.95% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 7 0.05% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7390880477084 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 13834 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 363085536567 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47021857182433 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 726181462 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 7351151457424 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 13327 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 336351398021 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47048572598979 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 672713020 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 86390303 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 594062843 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 134369829 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 78645304 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 601498232 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 14253482 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1820697 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 287238 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 5988786 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 713679 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 819715 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 210572695 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1658938 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 27666 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 704645391 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.988963 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.222689 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 79728286 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 642468992 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 166724968 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 93734896 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 559167861 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13053646 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1631240 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 271905 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 4961771 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 667976 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 769069 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 233453036 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1554763 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 25728 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 653724931 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.120109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.251817 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 370929364 52.64% 52.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 130277469 18.49% 71.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 43725033 6.21% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 159713525 22.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 313299605 47.93% 47.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 112972876 17.28% 65.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 63087328 9.65% 74.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 164365122 25.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 704645391 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.185036 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.818064 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 103020673 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 337373962 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 222407115 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 36734416 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5109225 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 18739170 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2055775 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 616426802 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 23026844 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5109225 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 137867421 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 45074504 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 232811775 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 223900939 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 59881527 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 599411621 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 6042296 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9969882 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 242190 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 299313 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 25537080 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 11262 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 571214843 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 926423560 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 707359605 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 805393 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 514629531 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 56585312 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15957043 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 14048251 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 73992297 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 98060208 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 84478655 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8950565 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7675207 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 576680308 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 16104006 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 581772484 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2680133 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 53366771 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 34273904 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 266458 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 704645391 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.825624 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.067009 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 653724931 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.247840 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.955042 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 92976248 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 279392919 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 246557278 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 30153950 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4644536 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 16507277 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1918533 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 660010839 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21083339 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4644536 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 123063367 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 35472140 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 196207454 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 246305385 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 48032049 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 644623401 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5459169 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8046987 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 175179 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 243838 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 19778119 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 13544 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 568046285 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 920205364 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 738028680 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 778046 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 516650091 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 51396188 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 12941129 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 11231119 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 61203121 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 135763785 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 72651809 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8023262 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7007249 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 625560135 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 13098005 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 628187829 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2397096 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 48439446 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 31062607 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 245074 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 653724931 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.960936 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.128164 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 385934490 54.77% 54.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 135280434 19.20% 73.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 111501247 15.82% 89.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 64231431 9.12% 98.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7693682 1.09% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4107 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 329147367 50.35% 50.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 114620484 17.53% 67.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 122782429 18.78% 86.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 80699819 12.34% 99.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6471130 0.99% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3702 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 704645391 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 653724931 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 58591735 44.23% 44.23% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 49305 0.04% 44.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 21310 0.02% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 60 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 35005485 26.43% 70.71% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 38791699 29.29% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 51549181 44.86% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 41748 0.04% 44.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 12676 0.01% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 10 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 30585339 26.62% 71.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 32314734 28.12% 99.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 48210 0.04% 99.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 356758 0.31% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 36 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 397008075 68.24% 68.24% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1247296 0.21% 68.46% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 70487 0.01% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 78078 0.01% 68.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.48% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 100884939 17.34% 85.82% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 82483526 14.18% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 418102293 66.56% 66.56% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1205881 0.19% 66.75% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 68687 0.01% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 9 0.00% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 15 0.00% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 25 0.00% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 73390 0.01% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 1 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 137792676 21.93% 88.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 70525871 11.23% 99.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 69235 0.01% 99.94% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 349710 0.06% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 581772484 # Type of FU issued -system.cpu1.iq.rate 0.801139 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 132459594 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.227683 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 2001993843 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 645760406 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 564750025 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1336243 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 531893 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 495883 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 713403384 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 828658 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2572358 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 628187829 # Type of FU issued +system.cpu1.iq.rate 0.933813 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 114908656 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.182921 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 2026010950 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 686704768 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 613194933 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1395389 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 519993 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 487253 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 742199086 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 897363 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2245530 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 12226985 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16460 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 142391 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5497757 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11142517 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 14462 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 128111 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 4846687 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2564544 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4190277 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2292036 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3380084 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5109225 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6111838 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1648605 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 592918318 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4644536 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5369264 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1350152 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 638773601 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 98060208 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 84478655 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13792326 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 62841 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1527139 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 142391 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1885740 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 3046567 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4932307 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 573876367 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 97784309 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 7346483 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 135763785 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 72651809 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 10993874 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 39251 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1271644 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 128111 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1722302 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2773233 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4495535 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 621090126 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 135058369 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6634352 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 134004 # number of nop insts executed -system.cpu1.iew.exec_refs 179029158 # number of memory reference insts executed -system.cpu1.iew.exec_branches 107707763 # Number of branches executed -system.cpu1.iew.exec_stores 81244849 # Number of stores executed -system.cpu1.iew.exec_rate 0.790266 # Inst execution rate -system.cpu1.iew.wb_sent 565995055 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 565245908 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 273023556 # num instructions producing a value -system.cpu1.iew.wb_consumers 448078183 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.778381 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.609321 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 46535716 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15837548 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4592045 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 695790390 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.775259 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.568649 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 115461 # number of nop insts executed +system.cpu1.iew.exec_refs 204845438 # number of memory reference insts executed +system.cpu1.iew.exec_branches 142702777 # Number of branches executed +system.cpu1.iew.exec_stores 69787069 # Number of stores executed +system.cpu1.iew.exec_rate 0.923262 # Inst execution rate +system.cpu1.iew.wb_sent 614366699 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 613682186 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 312164308 # num instructions producing a value +system.cpu1.iew.wb_consumers 462317181 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.912250 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.675217 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 42230538 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 12852931 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4178812 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 645679168 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.914105 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.588407 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 457970279 65.82% 65.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 124243355 17.86% 83.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 52434114 7.54% 91.21% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 17645088 2.54% 93.75% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 12549968 1.80% 95.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8433891 1.21% 96.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5802471 0.83% 97.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3503250 0.50% 98.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 13207974 1.90% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 392186508 60.74% 60.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 104643933 16.21% 76.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 70768120 10.96% 87.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 40497706 6.27% 94.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10687024 1.66% 95.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7435797 1.15% 96.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5000033 0.77% 97.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3062259 0.47% 98.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 11397788 1.77% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 695790390 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 458018039 # Number of instructions committed -system.cpu1.commit.committedOps 539417542 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 645679168 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 519872171 # Number of instructions committed +system.cpu1.commit.committedOps 590218687 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 164814121 # Number of memory references committed -system.cpu1.commit.loads 85833223 # Number of loads committed -system.cpu1.commit.membars 3719425 # Number of memory barriers committed -system.cpu1.commit.branches 102343051 # Number of branches committed -system.cpu1.commit.fp_insts 486729 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 494686776 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13237013 # Number of function calls committed. +system.cpu1.commit.refs 192426389 # Number of memory references committed +system.cpu1.commit.loads 124621267 # Number of loads committed +system.cpu1.commit.membars 28164164 # Number of memory barriers committed +system.cpu1.commit.branches 137852750 # Number of branches committed +system.cpu1.commit.fp_insts 479347 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 552778663 # Number of committed integer instructions. +system.cpu1.commit.function_calls 11814414 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 373462182 69.23% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1014464 0.19% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 55738 0.01% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 70995 0.01% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 85833223 15.91% 85.36% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 78980898 14.64% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 396713394 67.21% 67.21% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 957424 0.16% 67.38% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 54002 0.01% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 8 0.00% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 13 0.00% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 21 0.00% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 67436 0.01% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 124556243 21.10% 88.50% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 67458277 11.43% 99.93% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 65024 0.01% 99.94% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 346845 0.06% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 539417542 # Class of committed instruction -system.cpu1.commit.bw_lim_events 13207974 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1264391907 # The number of ROB reads -system.cpu1.rob.rob_writes 1180722952 # The number of ROB writes -system.cpu1.timesIdled 944459 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 21536071 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94043695657 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 458018039 # Number of Instructions Simulated -system.cpu1.committedOps 539417542 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.585487 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.585487 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.630721 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.630721 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 677403787 # number of integer regfile reads -system.cpu1.int_regfile_writes 401367044 # number of integer regfile writes -system.cpu1.fp_regfile_reads 791707 # number of floating regfile reads -system.cpu1.fp_regfile_writes 438600 # number of floating regfile writes -system.cpu1.cc_regfile_reads 124889457 # number of cc regfile reads -system.cpu1.cc_regfile_writes 125620500 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1260290191 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15974322 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5362331 # number of replacements -system.cpu1.dcache.tags.tagsinuse 456.510727 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 153804268 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5362842 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.679620 # Average number of references to valid blocks. +system.cpu1.commit.op_class_0::total 590218687 # Class of committed instruction +system.cpu1.commit.bw_lim_events 11397788 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1262985389 # The number of ROB reads +system.cpu1.rob.rob_writes 1272910770 # The number of ROB writes +system.cpu1.timesIdled 874445 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 18988089 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94097134999 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 519872171 # Number of Instructions Simulated +system.cpu1.committedOps 590218687 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.293997 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.293997 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.772799 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.772799 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 710414372 # number of integer regfile reads +system.cpu1.int_regfile_writes 423863042 # number of integer regfile writes +system.cpu1.fp_regfile_reads 765235 # number of floating regfile reads +system.cpu1.fp_regfile_writes 456552 # number of floating regfile writes +system.cpu1.cc_regfile_reads 104682480 # number of cc regfile reads +system.cpu1.cc_regfile_writes 105389899 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1284615439 # number of misc regfile reads +system.cpu1.misc_regfile_writes 12778028 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 4692670 # number of replacements +system.cpu1.dcache.tags.tagsinuse 431.602875 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 183292694 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4693181 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.055109 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8517840775000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.510727 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.891623 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.891623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 431.602875 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.842974 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.842974 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 341608540 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 341608540 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 79940930 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 79940930 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 69078558 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 69078558 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191831 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 191831 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 170764 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 170764 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1820637 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1820637 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1828950 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1828950 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 149190252 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 149190252 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 149382083 # number of overall hits -system.cpu1.dcache.overall_hits::total 149382083 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6220385 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6220385 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7237581 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7237581 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 689658 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 689658 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 463987 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 463987 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 244543 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 244543 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 192296 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 192296 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13921953 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13921953 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14611611 # number of overall misses -system.cpu1.dcache.overall_misses::total 14611611 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96362388500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 96362388500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 134833660621 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 134833660621 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11613680644 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 11613680644 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3499456000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3499456000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4567503000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4567503000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3019500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3019500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 242809729765 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 242809729765 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 242809729765 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 242809729765 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 86161315 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 86161315 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 76316139 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 76316139 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 881489 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 881489 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 634751 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 634751 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2065180 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2065180 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2021246 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2021246 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 163112205 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 163112205 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 163993694 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 163993694 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072195 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.072195 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094837 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.094837 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.782378 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.782378 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.730975 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.730975 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118412 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118412 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095137 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095137 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085352 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.085352 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089099 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.089099 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15491.386546 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15491.386546 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18629.658255 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18629.658255 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25030.185423 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 25030.185423 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14310.186757 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14310.186757 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23752.459750 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23752.459750 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 395805519 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 395805519 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 119760214 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 119760214 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 59584318 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 59584318 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 168476 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 168476 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 151679 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 151679 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1458987 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1458987 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1477989 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1477989 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 179496211 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 179496211 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 179664687 # number of overall hits +system.cpu1.dcache.overall_hits::total 179664687 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 5543636 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 5543636 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 5953679 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 5953679 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 548675 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 548675 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 445037 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 445037 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 238823 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 238823 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 180840 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 180840 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 11942352 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 11942352 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 12491027 # number of overall misses +system.cpu1.dcache.overall_misses::total 12491027 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 78644271500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 78644271500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 105227667186 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 105227667186 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11004402882 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 11004402882 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3255486500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3255486500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4308460000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4308460000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4407500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4407500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 194876341568 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 194876341568 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 194876341568 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 194876341568 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 125303850 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 125303850 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 65537997 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 65537997 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 717151 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 717151 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 596716 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 596716 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1697810 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1697810 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1658829 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1658829 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 191438563 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 191438563 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 192155714 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 192155714 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044242 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044242 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.090843 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.090843 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.765076 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.765076 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.745810 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.745810 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140665 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140665 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109017 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109017 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.062382 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.062382 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.065005 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.065005 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14186.406088 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14186.406088 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17674.393797 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17674.393797 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24726.939293 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24726.939293 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13631.377631 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13631.377631 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23824.706923 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23824.706923 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17440.780741 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17440.780741 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16617.587873 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16617.587873 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 3018250 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 21738633 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 378529 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 731712 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.973629 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 29.709275 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5362354 # number of writebacks -system.cpu1.dcache.writebacks::total 5362354 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3187456 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3187456 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5861363 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5861363 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3594 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3594 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 128092 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 128092 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 9052413 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 9052413 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 9052413 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 9052413 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3032929 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3032929 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1376218 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1376218 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 689576 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 689576 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 460393 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 460393 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116451 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116451 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192288 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 192288 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4869540 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4869540 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5559116 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5559116 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21291 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21291 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19410 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 19410 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40701 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40701 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42726170500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42726170500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26732145261 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26732145261 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16635879000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16635879000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11021618644 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11021618644 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1587191500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1587191500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4375287000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4375287000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2947500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2947500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 80479934405 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 80479934405 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 97115813405 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 97115813405 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3797634000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3797634000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3797634000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3797634000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035201 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035201 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018033 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018033 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.782285 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.782285 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.725313 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.725313 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056388 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056388 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095133 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095133 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029854 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029854 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033898 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033898 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14087.428522 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14087.428522 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19424.353744 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19424.353744 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24124.794076 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.794076 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23939.587796 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23939.587796 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13629.694034 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13629.694034 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22753.822391 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22753.822391 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16318.087222 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16318.087222 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15601.306567 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15601.306567 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 2879860 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 16425129 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 370474 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 590630 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.773447 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 27.809507 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 4692685 # number of writebacks +system.cpu1.dcache.writebacks::total 4692685 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 2832127 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 2832127 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 4784793 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 4784793 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3576 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3576 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 122254 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 122254 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 7620496 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 7620496 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 7620496 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 7620496 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2711509 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2711509 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1168886 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1168886 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 548581 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 548581 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 441461 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 441461 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116569 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116569 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 180840 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 180840 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4321856 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4321856 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4870437 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4870437 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22628 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22628 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21158 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21158 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 43786 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 43786 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 35845036500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 35845036500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21809849574 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21809849574 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12123846500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12123846500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10446547382 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10446547382 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1530530500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1530530500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4127725000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4127725000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4302500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4302500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68101433456 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 68101433456 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 80225279956 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 80225279956 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4008317000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4008317000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4008317000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4008317000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.021639 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.021639 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017835 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017835 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.764945 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.764945 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.739818 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.739818 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068658 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068658 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109017 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109017 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.022576 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.022576 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.025346 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.025346 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13219.589719 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13219.589719 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18658.662670 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18658.662670 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22100.376243 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22100.376243 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23663.579301 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23663.579301 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13129.824396 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13129.824396 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22825.287547 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22825.287547 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16527.214974 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16527.214974 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17469.650463 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17469.650463 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178368.042835 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 178368.042835 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 93305.668165 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 93305.668165 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 5902862 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.529159 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 204324856 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5903374 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 34.611538 # Average number of references to valid blocks. +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15757.450840 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15757.450840 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16471.885368 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16471.885368 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177139.694184 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177139.694184 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91543.347189 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91543.347189 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 5471432 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.529158 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 227657285 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5471944 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 41.604462 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8518180301500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.529159 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.529158 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979549 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.979549 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 427035149 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 427035149 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 204324856 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 204324856 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 204324856 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 204324856 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 204324856 # number of overall hits -system.cpu1.icache.overall_hits::total 204324856 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6241016 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6241016 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6241016 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6241016 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6241016 # number of overall misses -system.cpu1.icache.overall_misses::total 6241016 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 68483006769 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 68483006769 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 68483006769 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 68483006769 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 68483006769 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 68483006769 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 210565872 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 210565872 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 210565872 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 210565872 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 210565872 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 210565872 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029639 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029639 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029639 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029639 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029639 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029639 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10973.054190 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10973.054190 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10973.054190 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10973.054190 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10973.054190 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10973.054190 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 10089385 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 780 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 729550 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.829600 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 390 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 5902862 # number of writebacks -system.cpu1.icache.writebacks::total 5902862 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 337611 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 337611 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 337611 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 337611 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 337611 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 337611 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5903405 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5903405 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5903405 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5903405 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5903405 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5903405 # number of overall MSHR misses +system.cpu1.icache.tags.tag_accesses 472364897 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 472364897 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 227657285 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 227657285 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 227657285 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 227657285 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 227657285 # number of overall hits +system.cpu1.icache.overall_hits::total 227657285 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5789178 # 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number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5471971 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5471971 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5471971 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 61792345334 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 61792345334 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 61792345334 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 61792345334 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 61792345334 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 61792345334 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 56670933881 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 56670933881 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 56670933881 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 56670933881 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 56670933881 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 56670933881 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7079498 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7079498 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7079498 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 7079498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028036 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.028036 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.028036 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10467.238032 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10467.238032 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10467.238032 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023440 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023440 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023440 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023440 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023440 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023440 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10356.585201 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10356.585201 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10356.585201 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10356.585201 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10356.585201 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10356.585201 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 105664.149254 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 105664.149254 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7372835 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7380898 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 7290 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6370815 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6378826 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 7261 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 895622 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2111480 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 12950.875249 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10279593 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2126904 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.833125 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 806238 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 1756578 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 12752.912837 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 9300002 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1772385 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.247168 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12615.195694 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 33.253837 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 24.384299 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 278.041418 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.769970 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002030 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001488 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.016970 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.790459 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 414 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14899 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 65 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 128 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 114 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 107 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 89 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 279 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1377 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5586 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5487 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2170 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.025269 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.909363 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 393006433 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 393006433 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 563217 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 188120 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 751337 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3404083 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3404083 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 7859423 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 7859423 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 37 # number of UpgradeReq hits +system.cpu1.l2cache.tags.occ_blocks::writebacks 12466.059831 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 25.971588 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 14.261261 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 246.620158 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.760868 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001585 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000870 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.015052 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.778376 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 338 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15390 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 133 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 109 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 42 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 203 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1774 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7283 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4523 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1607 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020630 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.939331 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 354225697 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 354225697 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 466688 # 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average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55438.584063 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 38774.214418 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.209743 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 20908.732599 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 22098.900435 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21285.211941 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30457.422742 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30457.422742 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18832.337842 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18832.337842 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15312.408700 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15312.408700 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 501785.428571 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 501785.428571 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32728.538455 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32728.538455 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29918.930595 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29918.930595 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27017.436190 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27017.436190 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26149.159101 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26149.159101 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 20908.732599 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 22098.900435 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29918.930595 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28246.439217 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28671.963985 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 20908.732599 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 22098.900435 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29918.930595 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28246.439217 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30457.422742 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29168.503494 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170357.991640 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 170131.472984 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169131.584762 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168922.031284 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 89115.549986 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 89130.396389 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 23401917 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12050394 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1685 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 583324 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 583320 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 4 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 895492 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10720388 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 19410 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 19410 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4582624 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 7861129 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1298468 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 967756 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 436519 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348532 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 480708 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1183332 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1160512 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5903405 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4845353 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 522418 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 458323 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17709789 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17335665 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 416038 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1239832 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 36701324 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 755601072 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 668583302 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1583448 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4670440 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1430438262 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5153113 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 82064432 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 17599300 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.053842 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.225707 # Request fanout histogram +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87404.866852 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87421.282466 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 21096907 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10844448 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1776 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 550847 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 550845 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 772948 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9709968 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 21158 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 21158 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 3884973 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7223497 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1103932 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 773517 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 20 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 412740 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 326097 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 449655 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 92 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 190 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 993079 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 971172 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5471971 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4312998 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 499008 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 439419 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16415488 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15276269 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 387820 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1031669 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 33111246 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 700377584 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 584403341 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1476688 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3877200 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1290134813 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4431345 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 67169608 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 15631904 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.053925 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.225870 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 16651717 94.62% 94.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 947579 5.38% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 4 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 14788958 94.61% 94.61% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 842944 5.39% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 17599300 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 23252082447 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 15631904 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 20975087949 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 167523282 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 172744273 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8861086123 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8213479520 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7965231666 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 6968060036 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 218506693 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 203672612 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 656902733 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 547726569 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40332 # Transaction distribution -system.iobus.trans_dist::ReadResp 40332 # Transaction distribution -system.iobus.trans_dist::WriteReq 136631 # Transaction distribution -system.iobus.trans_dist::WriteResp 136631 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40379 # Transaction distribution +system.iobus.trans_dist::ReadResp 40379 # Transaction distribution +system.iobus.trans_dist::WriteReq 136662 # Transaction distribution +system.iobus.trans_dist::WriteResp 136662 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47802 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -3000,13 +3025,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231266 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231266 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353926 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354082 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47822 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3019,13 +3044,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155843 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339080 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496841 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36933004 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7497009 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37065503 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -3047,75 +3072,75 @@ system.iobus.reqLayer16.occupancy 13000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24511500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24279001 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36406001 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36411000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569333352 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569676929 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92684000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92805000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147958000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147962000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115627 # number of replacements -system.iocache.tags.tagsinuse 11.209625 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115614 # number of replacements +system.iocache.tags.tagsinuse 11.210449 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115643 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 9156281985000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.417323 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.792302 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463583 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.237019 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.700602 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.838554 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.371895 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239910 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.460743 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.700653 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041036 # Number of tag accesses -system.iocache.tags.data_accesses 1041036 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1041054 # Number of tag accesses +system.iocache.tags.data_accesses 1041054 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8905 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8942 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115631 # number of demand (read+write) misses -system.iocache.demand_misses::total 115671 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115633 # number of demand (read+write) misses +system.iocache.demand_misses::total 115673 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115631 # number of overall misses -system.iocache.overall_misses::total 115671 # number of overall misses +system.iocache.overall_misses::realview.ide 115633 # number of overall misses +system.iocache.overall_misses::total 115673 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1786499757 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1791699757 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1855240026 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1860440026 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13185420595 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13185420595 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13135197903 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13135197903 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14971920352 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14977489352 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14990437929 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14996006929 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14971920352 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14977489352 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14990437929 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14996006929 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8942 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115631 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115671 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115633 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115673 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115631 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115671 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115633 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115673 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3130,52 +3155,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 200662.670673 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 200413.843065 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 208336.892308 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 208056.366137 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123542.281266 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 123542.281266 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123071.714105 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 123071.714105 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129480.159750 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129483.529597 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129638.061185 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129641.376371 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129480.159750 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129483.529597 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 39692 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 129638.061185 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129641.376371 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 43392 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3537 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3516 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.221939 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.341297 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8903 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8940 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8905 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8942 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115631 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115671 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115633 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115673 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115631 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115671 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 115633 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115673 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1341349757 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1344699757 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1409990026 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1413340026 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7839860905 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7839860905 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7789853273 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7789853273 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3569000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9181210662 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9184779662 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9199843299 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9203412299 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3569000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9181210662 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9184779662 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9199843299 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9203412299 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3190,658 +3215,663 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 150662.670673 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 150413.843065 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 158336.892308 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 158056.366137 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73456.458521 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73456.458521 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 72987.906388 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 72987.906388 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 79400.944920 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 79404.342160 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 79560.707575 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 79564.049510 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 79400.944920 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 79404.342160 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1712520 # number of replacements -system.l2c.tags.tagsinuse 65207.555116 # Cycle average of tags in use -system.l2c.tags.total_refs 7020190 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1774780 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.955527 # Average number of references to valid blocks. +system.iocache.overall_avg_mshr_miss_latency::realview.ide 79560.707575 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 79564.049510 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1186255 # number of replacements +system.l2c.tags.tagsinuse 65124.636684 # Cycle average of tags in use +system.l2c.tags.total_refs 6073175 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1247618 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.867816 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 3083323500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 10815.100932 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 305.602667 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 366.195320 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3964.024216 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 19638.791484 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14261.868883 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.853339 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 181.379081 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3223.101636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5938.767305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6360.870252 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.165025 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004663 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.005588 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.060486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.299664 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217619 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002317 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002768 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.049181 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.090618 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.097059 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994988 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11498 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 249 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50513 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1395 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 577 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9525 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 12698.793405 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 377.952725 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 459.111638 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5017.563285 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 20561.842939 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15825.160631 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 16.393148 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 11.333355 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4086.466074 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4153.822571 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1916.196912 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.193768 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.005767 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.007005 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.076562 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.313749 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.241473 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000250 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000173 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.062355 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.063382 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.029239 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.286942 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.203895 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.278758 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.223410 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.415837 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.286942 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.203895 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.278758 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20295.679445 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20793.680153 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20544.742838 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24188.080495 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24720.642769 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24484.192440 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98536.210915 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99453.454152 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 98845.895687 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101990.786172 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108368.427426 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126261.676330 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24695.536494 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20746.752089 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23945.493776 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100826.884185 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 105776.617110 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 122894.565469 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100826.884185 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 105776.617110 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 122894.565469 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.123756 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.149703 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.135738 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.012953 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.019531 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.016242 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.609481 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.406325 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.528844 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.144507 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.276401 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.097678 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.196486 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444353 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.052271 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.078901 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.086142 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.120941 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.235855 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.190704 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.789687 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.402230 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.676093 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.144507 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.276401 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097678 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.261992 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444353 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.052271 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.078901 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.086142 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.157472 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.235855 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.211497 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.144507 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.276401 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097678 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.261992 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444353 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.052271 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.078901 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.086142 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.157472 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.235855 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.211497 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20125.776162 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21094.517200 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20619.154668 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24245.967742 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24594.652406 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24455.627010 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98466.130420 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 101908.953583 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 99516.082516 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 94261.070155 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 93401.772130 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99627.097049 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 103308.103342 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 134928.725943 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 105728.003200 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 103378.651685 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 103727.664833 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 110212.090931 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134821.738450 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 119723.659458 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 25004.085714 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 21013.723427 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24308.081645 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 94261.070155 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 93401.772130 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99627.097049 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 101521.503967 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 134928.725943 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 105728.003200 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 103378.651685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 103727.664833 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 107469.633684 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134821.738450 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 116616.562666 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 94261.070155 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 93401.772130 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99627.097049 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 101521.503967 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 134928.725943 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 105728.003200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 103378.651685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 103727.664833 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 107469.633684 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134821.738450 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 116616.562666 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158502.709069 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158248.658158 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152366.950068 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124514.405742 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 151137.960886 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124061.141914 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75218.020737 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75855.198235 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 79700.729748 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 75885.828904 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 4262418 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2509154 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3063 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 78102.674561 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 75527.407238 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3300545 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2017233 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3015 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 59629 # Transaction distribution -system.membus.trans_dist::ReadResp 1085265 # Transaction distribution -system.membus.trans_dist::WriteReq 38211 # Transaction distribution -system.membus.trans_dist::WriteResp 38211 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1413261 # Transaction distribution -system.membus.trans_dist::CleanEvict 284296 # Transaction distribution -system.membus.trans_dist::UpgradeReq 353595 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 284030 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 60008 # Transaction distribution +system.membus.trans_dist::ReadResp 683640 # Transaction distribution +system.membus.trans_dist::WriteReq 38561 # Transaction distribution +system.membus.trans_dist::WriteResp 38561 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1023021 # Transaction distribution +system.membus.trans_dist::CleanEvict 202426 # Transaction distribution +system.membus.trans_dist::UpgradeReq 359792 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 266371 # Transaction distribution system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::ReadExReq 155418 # Transaction distribution -system.membus.trans_dist::ReadExResp 141619 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1025636 # Transaction distribution -system.membus.trans_dist::InvalidateReq 695069 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 125029 # Transaction distribution +system.membus.trans_dist::ReadExResp 110917 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 623632 # Transaction distribution +system.membus.trans_dist::InvalidateReq 649188 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122736 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5185454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5333270 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238137 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238137 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5571407 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3790913 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3940187 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238124 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238124 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4178311 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155843 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 158067712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 158274271 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7266112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 165540383 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 598647 # Total snoops (count) -system.membus.snoopTraffic 181312 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2611590 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013385 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.114916 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52924 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 105399040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 105608363 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7265984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7265984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 112874347 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 584671 # Total snoops (count) +system.membus.snoopTraffic 181568 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2122585 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015284 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.122681 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2576634 98.66% 98.66% # Request fanout histogram -system.membus.snoop_fanout::1 34956 1.34% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2090143 98.47% 98.47% # Request fanout histogram +system.membus.snoop_fanout::1 32442 1.53% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2611590 # Request fanout histogram -system.membus.reqLayer0.occupancy 98274995 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2122585 # Request fanout histogram +system.membus.reqLayer0.occupancy 98177996 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20993495 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22142995 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9731390131 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7123082230 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6232103011 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3974452270 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45620246 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45639777 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3884,82 +3914,83 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 12430379 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6756092 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1976828 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 231635 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 213178 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 18457 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 59631 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4752657 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38211 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38211 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4279629 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2861492 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 742959 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 389463 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1132422 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 304770 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 304770 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4693673 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 888953 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 857088 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10167135 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8009990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18177125 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 258318649 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198738470 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 457057119 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3168754 # Total snoops (count) -system.toL2Bus.snoopTraffic 137382864 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 8831298 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.353414 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.482382 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 10730258 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5842336 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1839840 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 143689 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 131126 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 12563 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 60010 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4055865 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38561 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38561 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3364400 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2413469 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 699420 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 360553 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1059973 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 190 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 190 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 262551 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262551 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3996472 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 835150 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 805766 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8799068 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6846513 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15645581 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 216011198 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 161148653 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 377159851 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2609772 # Total snoops (count) +system.toL2Bus.snoopTraffic 111390096 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7440116 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.386181 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.490329 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5728650 64.87% 64.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3084191 34.92% 99.79% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 18457 0.21% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4579449 61.55% 61.55% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2848104 38.28% 99.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 12563 0.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8831298 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9716591105 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7440116 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8239335116 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2596400 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2574912 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4626263938 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4018530287 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3958447661 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3394272097 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5035 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 5012 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13834 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 13327 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |