stats: Update stats to reflect ARM changes

1 files changed, 9 insertions, 9 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
index 10b007358..bdfed319a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 47.384315                       # Nu
 sim_ticks                                47384315163000                       # Number of ticks simulated
 final_tick                               47384315163000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 162093                       # Simulator instruction rate (inst/s)
-host_op_rate                                   190619                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8503081814                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 814268                       # Number of bytes of host memory used
-host_seconds                                  5572.60                       # Real time elapsed on the host
+host_inst_rate                                 151085                       # Simulator instruction rate (inst/s)
+host_op_rate                                   177673                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7925620115                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 773240                       # Number of bytes of host memory used
+host_seconds                                  5978.63                       # Real time elapsed on the host
 sim_insts                                   903281747                       # Number of instructions simulated
 sim_ops                                    1062243320                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -471,7 +471,7 @@ system.cpu0.dtb.flush_tlb                          14                       # Nu
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid              42813                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                   1051                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   35541                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                   35477                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                      482                       # Number of TLB faults due to alignment restrictions
 system.cpu0.dtb.prefetch_faults                  6442                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
@@ -582,7 +582,7 @@ system.cpu0.itb.flush_tlb                          14                       # Nu
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid              42813                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                   1051                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   25342                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                   25278                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
@@ -1797,7 +1797,7 @@ system.cpu1.dtb.flush_tlb                          14                       # Nu
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid              42813                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                   1051                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   40949                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                   40885                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                      397                       # Number of TLB faults due to alignment restrictions
 system.cpu1.dtb.prefetch_faults                  6052                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
@@ -1905,7 +1905,7 @@ system.cpu1.itb.flush_tlb                          14                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid              42813                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                   1051                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   29991                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                   29927                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions