diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:50:15 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:50:15 -0500 |
| commit | 29cd50e14e0709c28200bcbdbc08c1093ba300d7 (patch) | |
| tree | ce3db836e947d154cbd0e4d7e1959f7617a7cc0c /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual | |
| parent | 7a0bf814b6eb2db57f37977a0cca6c442f957d68 (diff) | |
| download | gem5-29cd50e14e0709c28200bcbdbc08c1093ba300d7.tar.xz | |
arm, tests: Add 64-bit ARM regression tests
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual')
4 files changed, 5745 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini new file mode 100644 index 000000000..7c36695c6 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini @@ -0,0 +1,2245 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain +atags_addr=134217728 +boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=timing +mem_ranges=2147483648:2415919103 +memories=system.realview.nvmem system.physmem system.realview.vram +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5.latest/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0] +type=DerivO3CPU +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +LFSTSize=1024 +LQEntries=16 +LSQCheckLoads=true +LSQDepCheckShift=0 +SQEntries=16 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu0.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=2 +decodeWidth=3 +dispatchWidth=6 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu +dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=16 +fetchQueueSize=32 +fetchToDecodeDelay=3 +fetchTrapLatency=1 +fetchWidth=3 +forwardComSize=5 +fuPool=system.cpu0.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +issueToExecuteDelay=1 +issueWidth=8 +istage2_mmu=system.cpu0.istage2_mmu +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=32 +numPhysCCRegs=640 +numPhysFloatRegs=192 +numPhysIntRegs=128 +numROBEntries=40 +numRobs=1 +numThreads=1 +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=1 +renameToROBDelay=1 +renameWidth=3 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu0.tracer +trapLatency=13 +wbWidth=8 +workload= +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.branchPred] +type=BranchPredictor +BTBEntries=2048 +BTBTagSize=18 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=bi-mode + +[system.cpu0.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=6 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.dcache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=16 +cpu_side=system.cpu0.dcache_port +mem_side=system.cpu0.toL2Bus.slave[1] + +[system.cpu0.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[5] + +[system.cpu0.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[3] + +[system.cpu0.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 +FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 +eventq_index=0 + +[system.cpu0.fuPool.FUList0] +type=FUDesc +children=opList +count=2 +eventq_index=0 +opList=system.cpu0.fuPool.FUList0.opList + +[system.cpu0.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu0.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 opList2 +count=1 +eventq_index=0 +opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 system.cpu0.fuPool.FUList1.opList2 + +[system.cpu0.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu0.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +issueLat=12 +opClass=IntDiv +opLat=12 + +[system.cpu0.fuPool.FUList1.opList2] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IprAccess +opLat=3 + +[system.cpu0.fuPool.FUList2] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu0.fuPool.FUList2.opList + +[system.cpu0.fuPool.FUList2.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemRead +opLat=2 + +[system.cpu0.fuPool.FUList3] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu0.fuPool.FUList3.opList + +[system.cpu0.fuPool.FUList3.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemWrite +opLat=2 + +[system.cpu0.fuPool.FUList4] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=2 +eventq_index=0 +opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25 + +[system.cpu0.fuPool.FUList4.opList00] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAdd +opLat=4 + +[system.cpu0.fuPool.FUList4.opList01] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAddAcc +opLat=4 + +[system.cpu0.fuPool.FUList4.opList02] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAlu +opLat=4 + +[system.cpu0.fuPool.FUList4.opList03] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCmp +opLat=4 + +[system.cpu0.fuPool.FUList4.opList04] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCvt +opLat=3 + +[system.cpu0.fuPool.FUList4.opList05] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMisc +opLat=3 + +[system.cpu0.fuPool.FUList4.opList06] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMult +opLat=5 + +[system.cpu0.fuPool.FUList4.opList07] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMultAcc +opLat=5 + +[system.cpu0.fuPool.FUList4.opList08] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShift +opLat=3 + +[system.cpu0.fuPool.FUList4.opList09] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShiftAcc +opLat=3 + +[system.cpu0.fuPool.FUList4.opList10] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdSqrt +opLat=9 + +[system.cpu0.fuPool.FUList4.opList11] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAdd +opLat=5 + +[system.cpu0.fuPool.FUList4.opList12] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAlu +opLat=5 + +[system.cpu0.fuPool.FUList4.opList13] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCmp +opLat=3 + +[system.cpu0.fuPool.FUList4.opList14] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCvt +opLat=3 + +[system.cpu0.fuPool.FUList4.opList15] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatDiv +opLat=3 + +[system.cpu0.fuPool.FUList4.opList16] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMisc +opLat=3 + +[system.cpu0.fuPool.FUList4.opList17] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMult +opLat=3 + +[system.cpu0.fuPool.FUList4.opList18] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu0.fuPool.FUList4.opList19] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatSqrt +opLat=9 + +[system.cpu0.fuPool.FUList4.opList20] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatAdd +opLat=5 + +[system.cpu0.fuPool.FUList4.opList21] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCmp +opLat=5 + +[system.cpu0.fuPool.FUList4.opList22] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCvt +opLat=5 + +[system.cpu0.fuPool.FUList4.opList23] +type=OpDesc +eventq_index=0 +issueLat=9 +opClass=FloatDiv +opLat=9 + +[system.cpu0.fuPool.FUList4.opList24] +type=OpDesc +eventq_index=0 +issueLat=33 +opClass=FloatSqrt +opLat=33 + +[system.cpu0.fuPool.FUList4.opList25] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu0.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=1 +is_top_level=true +max_miss_count=0 +mshrs=2 +prefetch_on_access=false +prefetcher=Null +response_latency=1 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.icache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.cpu0.toL2Bus.slave[0] + +[system.cpu0.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=1 +sequential_access=false +size=32768 + +[system.cpu0.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu0.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[4] + +[system.cpu0.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[2] + +[system.cpu0.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu0.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu0.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu0.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu0.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu0.l2cache.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu1] +type=DerivO3CPU +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +LFSTSize=1024 +LQEntries=16 +LSQCheckLoads=true +LSQDepCheckShift=0 +SQEntries=16 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu1.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=1 +decodeToFetchDelay=1 +decodeToRenameDelay=2 +decodeWidth=3 +dispatchWidth=6 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu +dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=16 +fetchQueueSize=32 +fetchToDecodeDelay=3 +fetchTrapLatency=1 +fetchWidth=3 +forwardComSize=5 +fuPool=system.cpu1.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu1.interrupts +isa=system.cpu1.isa +issueToExecuteDelay=1 +issueWidth=8 +istage2_mmu=system.cpu1.istage2_mmu +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=32 +numPhysCCRegs=640 +numPhysFloatRegs=192 +numPhysIntRegs=128 +numROBEntries=40 +numRobs=1 +numThreads=1 +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=1 +renameToROBDelay=1 +renameWidth=3 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu1.tracer +trapLatency=13 +wbWidth=8 +workload= +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.branchPred] +type=BranchPredictor +BTBEntries=2048 +BTBTagSize=18 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=bi-mode + +[system.cpu1.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=6 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu1.dcache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=16 +cpu_side=system.cpu1.dcache_port +mem_side=system.cpu1.toL2Bus.slave[1] + +[system.cpu1.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[5] + +[system.cpu1.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[3] + +[system.cpu1.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 +FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 +eventq_index=0 + +[system.cpu1.fuPool.FUList0] +type=FUDesc +children=opList +count=2 +eventq_index=0 +opList=system.cpu1.fuPool.FUList0.opList + +[system.cpu1.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu1.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 opList2 +count=1 +eventq_index=0 +opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 system.cpu1.fuPool.FUList1.opList2 + +[system.cpu1.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu1.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +issueLat=12 +opClass=IntDiv +opLat=12 + +[system.cpu1.fuPool.FUList1.opList2] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IprAccess +opLat=3 + +[system.cpu1.fuPool.FUList2] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu1.fuPool.FUList2.opList + +[system.cpu1.fuPool.FUList2.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemRead +opLat=2 + +[system.cpu1.fuPool.FUList3] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu1.fuPool.FUList3.opList + +[system.cpu1.fuPool.FUList3.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemWrite +opLat=2 + +[system.cpu1.fuPool.FUList4] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=2 +eventq_index=0 +opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25 + +[system.cpu1.fuPool.FUList4.opList00] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAdd +opLat=4 + +[system.cpu1.fuPool.FUList4.opList01] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAddAcc +opLat=4 + +[system.cpu1.fuPool.FUList4.opList02] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAlu +opLat=4 + +[system.cpu1.fuPool.FUList4.opList03] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCmp +opLat=4 + +[system.cpu1.fuPool.FUList4.opList04] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCvt +opLat=3 + +[system.cpu1.fuPool.FUList4.opList05] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMisc +opLat=3 + +[system.cpu1.fuPool.FUList4.opList06] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMult +opLat=5 + +[system.cpu1.fuPool.FUList4.opList07] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMultAcc +opLat=5 + +[system.cpu1.fuPool.FUList4.opList08] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShift +opLat=3 + +[system.cpu1.fuPool.FUList4.opList09] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShiftAcc +opLat=3 + +[system.cpu1.fuPool.FUList4.opList10] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdSqrt +opLat=9 + +[system.cpu1.fuPool.FUList4.opList11] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAdd +opLat=5 + +[system.cpu1.fuPool.FUList4.opList12] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAlu +opLat=5 + +[system.cpu1.fuPool.FUList4.opList13] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCmp +opLat=3 + +[system.cpu1.fuPool.FUList4.opList14] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCvt +opLat=3 + +[system.cpu1.fuPool.FUList4.opList15] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatDiv +opLat=3 + +[system.cpu1.fuPool.FUList4.opList16] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMisc +opLat=3 + +[system.cpu1.fuPool.FUList4.opList17] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMult +opLat=3 + +[system.cpu1.fuPool.FUList4.opList18] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu1.fuPool.FUList4.opList19] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatSqrt +opLat=9 + +[system.cpu1.fuPool.FUList4.opList20] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatAdd +opLat=5 + +[system.cpu1.fuPool.FUList4.opList21] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCmp +opLat=5 + +[system.cpu1.fuPool.FUList4.opList22] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCvt +opLat=5 + +[system.cpu1.fuPool.FUList4.opList23] +type=OpDesc +eventq_index=0 +issueLat=9 +opClass=FloatDiv +opLat=9 + +[system.cpu1.fuPool.FUList4.opList24] +type=OpDesc +eventq_index=0 +issueLat=33 +opClass=FloatSqrt +opLat=33 + +[system.cpu1.fuPool.FUList4.opList25] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu1.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=1 +is_top_level=true +max_miss_count=0 +mshrs=2 +prefetch_on_access=false +prefetcher=Null +response_latency=1 +sequential_access=false +size=32768 +system=system +tags=system.cpu1.icache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.cpu1.toL2Bus.slave[0] + +[system.cpu1.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=1 +sequential_access=false +size=32768 + +[system.cpu1.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu1.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[4] + +[system.cpu1.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[2] + +[system.cpu1.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu1.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu1.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[1] + +[system.cpu1.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu1.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu1.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu1.l2cache.cpu_side +slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu1.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=true +width=8 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.l2c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.l2c.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.l2c.cpu_side +slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr new file mode 100644 index 000000000..bbb1cd360 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr @@ -0,0 +1,12 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: allocating bonus target for snoop +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout new file mode 100644 index 000000000..c9871ea6d --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout @@ -0,0 +1,17 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 11:56:54 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 + 0: system.cpu0.isa: ISA system set to: 0x5878b00 0x5878b00 + 0: system.cpu1.isa: ISA system set to: 0x5878b00 0x5878b00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80080000 +info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 47379674621500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt new file mode 100644 index 000000000..a72ace5ed --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -0,0 +1,3471 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 47.379675 # Number of seconds simulated +sim_ticks 47379674621500 # Number of ticks simulated +final_tick 47379674621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 109387 # Simulator instruction rate (inst/s) +host_op_rate 128661 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5550125892 # Simulator tick rate (ticks/s) +host_mem_usage 850512 # Number of bytes of host memory used +host_seconds 8536.68 # Real time elapsed on the host +sim_insts 933798389 # Number of instructions simulated +sim_ops 1098335322 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 528 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.ide 472128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 353088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 523648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1152800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 18354072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 38298624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 338240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 462784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 532064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12967328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 29162240 # Number of bytes read from this memory +system.physmem.bytes_read::total 102617016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1152800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 532064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1684864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 56488832 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 66623564 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 34275268 # Number of bytes written to this memory +system.physmem.bytes_written::total 164218256 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 7377 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 5517 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 8182 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 33965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 286804 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 598416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 5285 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 7231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 8357 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 202629 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 455660 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1619423 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 882638 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 1043270 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 535552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2568188 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 9965 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 7452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 11052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 24331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 387383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 808334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 7139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 9768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 11230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 273690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 615501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2165845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 24331 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 11230 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 35561 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1192259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 144167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 1406163 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 723417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3466006 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1192259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 154132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 7452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 11052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 24331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1793546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 808334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 7139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 9768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 11230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 997107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 615501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5631851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1619423 # Number of read requests accepted +system.physmem.writeReqs 2568188 # Number of write requests accepted +system.physmem.readBursts 1619423 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2568188 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 103371328 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 271744 # Total number of bytes read from write queue +system.physmem.bytesWritten 158872640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 102617016 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 164218256 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 4246 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 85771 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 103144 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 111705 # Per bank write bursts +system.physmem.perBankRdBursts::1 107185 # Per bank write bursts +system.physmem.perBankRdBursts::2 95216 # Per bank write bursts +system.physmem.perBankRdBursts::3 93593 # Per bank write bursts +system.physmem.perBankRdBursts::4 97040 # Per bank write bursts +system.physmem.perBankRdBursts::5 109538 # Per bank write bursts +system.physmem.perBankRdBursts::6 103640 # Per bank write bursts +system.physmem.perBankRdBursts::7 104459 # Per bank write bursts +system.physmem.perBankRdBursts::8 87345 # Per bank write bursts +system.physmem.perBankRdBursts::9 119689 # Per bank write bursts +system.physmem.perBankRdBursts::10 87550 # Per bank write bursts +system.physmem.perBankRdBursts::11 102455 # Per bank write bursts +system.physmem.perBankRdBursts::12 98167 # Per bank write bursts +system.physmem.perBankRdBursts::13 96293 # Per bank write bursts +system.physmem.perBankRdBursts::14 97699 # Per bank write bursts +system.physmem.perBankRdBursts::15 103603 # Per bank write bursts +system.physmem.perBankWrBursts::0 151797 # Per bank write bursts +system.physmem.perBankWrBursts::1 157102 # Per bank write bursts +system.physmem.perBankWrBursts::2 173467 # Per bank write bursts +system.physmem.perBankWrBursts::3 129226 # Per bank write bursts +system.physmem.perBankWrBursts::4 217724 # Per bank write bursts +system.physmem.perBankWrBursts::5 151423 # Per bank write bursts +system.physmem.perBankWrBursts::6 153455 # Per bank write bursts +system.physmem.perBankWrBursts::7 181552 # Per bank write bursts +system.physmem.perBankWrBursts::8 127836 # Per bank write bursts +system.physmem.perBankWrBursts::9 166575 # Per bank write bursts +system.physmem.perBankWrBursts::10 140595 # Per bank write bursts +system.physmem.perBankWrBursts::11 139064 # Per bank write bursts +system.physmem.perBankWrBursts::12 135611 # Per bank write bursts +system.physmem.perBankWrBursts::13 129688 # Per bank write bursts +system.physmem.perBankWrBursts::14 173219 # Per bank write bursts +system.physmem.perBankWrBursts::15 154051 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 280 # Number of times write queue was full causing retry +system.physmem.totGap 47379673169000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 37 # Read request sizes (log2) +system.physmem.readPktSize::4 21333 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1598053 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 2 # Write request sizes (log2) +system.physmem.writePktSize::3 2601 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 2565585 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 575288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 378276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 198870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 124070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 84552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 66107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 57559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 49842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 42131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 14414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 7965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 5242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 3374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1439 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 50077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 80336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 91349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 103691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 113552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 135687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 144994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 161556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 168861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 188844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 173768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 166459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 153274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 157126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 123678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 118188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 114281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 106686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 15195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 11268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 9055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 4660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 3546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 674 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 968355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 270.813741 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.322670 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.242545 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 500729 51.71% 51.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 182951 18.89% 70.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 62910 6.50% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 30320 3.13% 80.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 27676 2.86% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15651 1.62% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 12433 1.28% 85.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 15606 1.61% 87.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 120079 12.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 968355 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 90300 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.886467 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 201.343157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 90297 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 90300 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 90300 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.490421 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 23.640759 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.748039 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 56859 62.97% 62.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 8057 8.92% 71.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 12273 13.59% 85.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 3990 4.42% 89.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 1898 2.10% 92.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 944 1.05% 93.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 2681 2.97% 96.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1258 1.39% 97.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 729 0.81% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 233 0.26% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 328 0.36% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 174 0.19% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 473 0.52% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 16 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 44 0.05% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 33 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 16 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 34 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 77 0.09% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 57 0.06% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 40 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 6 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 21 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 22 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 7 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 90300 # Writes before turning the bus around for reads +system.physmem.totQLat 65880977516 # Total ticks spent queuing +system.physmem.totMemAccLat 96165546266 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8075885000 # Total ticks spent in databus transfers +system.physmem.avgQLat 40788.70 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 59538.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.47 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 3.63 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing +system.physmem.readRowHits 1266207 # Number of row buffer hits during reads +system.physmem.writeRowHits 1862998 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.05 # Row buffer hit rate for writes +system.physmem.avgGap 11314248.90 # Average gap between requests +system.physmem.pageHitRate 76.37 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 45458713155000 # Time in different power states +system.physmem.memoryStateTime::REF 1582111440000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 338849669500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3771472320 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3549283920 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2057847000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1936613250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 6414501600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 6183847800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 8526034080 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 7559820720 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3094609976640 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3094609976640 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1215510046335 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1201972779180 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 27361567580250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 27373442376000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 31692457458225 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 31689254697510 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.904083 # Core power per rank (mW) +system.physmem.averagePower::1 668.836485 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 1503713 # Transaction distribution +system.membus.trans_dist::ReadResp 1503713 # Transaction distribution +system.membus.trans_dist::WriteReq 38586 # Transaction distribution +system.membus.trans_dist::WriteResp 38586 # Transaction distribution +system.membus.trans_dist::Writeback 882638 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 1682947 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 1682947 # Transaction distribution +system.membus.trans_dist::UpgradeReq 373970 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 331267 # Transaction distribution +system.membus.trans_dist::UpgradeResp 103150 # Transaction distribution +system.membus.trans_dist::ReadExReq 170539 # Transaction distribution +system.membus.trans_dist::ReadExResp 155861 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123084 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26002 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 8087433 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 8236597 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 229762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 8466359 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156191 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52004 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 259532552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 259741319 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7302720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 267044039 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 618323 # Total snoops (count) +system.membus.snoop_fanout::samples 4885385 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 4885385 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 4885385 # Request fanout histogram +system.membus.reqLayer0.occupancy 98770920 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 21644945 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 25191464236 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 16556458898 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 187451430 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.l2c.tags.replacements 1387044 # number of replacements +system.l2c.tags.tagsinuse 64427.808632 # Cycle average of tags in use +system.l2c.tags.total_refs 7620997 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1449367 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.258155 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10003.170740 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 188.441651 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 243.424548 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 921.507825 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 8419.959281 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24297.060802 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 189.151688 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 259.454485 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 442.813505 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5057.928398 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 14404.895708 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.152636 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002875 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003714 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.014061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.128478 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370744 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002886 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003959 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.006757 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.077178 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.219801 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983090 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 33631 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 302 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 28390 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 86 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 2393 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1787 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 29347 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 16 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 34 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 216 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2265 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4264 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 21604 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.513168 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004608 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.433197 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 91165244 # Number of tag accesses +system.l2c.tags.data_accesses 91165244 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 7553 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4301 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 170694 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 696092 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1825935 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 8223 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5157 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 162945 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 691200 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1816536 # number of ReadReq hits +system.l2c.ReadReq_hits::total 5388636 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2284318 # number of Writeback hits +system.l2c.Writeback_hits::total 2284318 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 28567 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 31425 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 59992 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 8944 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 7440 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 16384 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 53362 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 53750 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107112 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 7553 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4301 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 170694 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 749454 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 1825935 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 8223 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5157 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 162945 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 744950 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 1816536 # number of demand (read+write) hits +system.l2c.demand_hits::total 5495748 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 7553 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4301 # number of overall hits +system.l2c.overall_hits::cpu0.inst 170694 # number of overall hits +system.l2c.overall_hits::cpu0.data 749454 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 1825935 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 8223 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5157 # number of overall hits +system.l2c.overall_hits::cpu1.inst 162945 # number of overall hits +system.l2c.overall_hits::cpu1.data 744950 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 1816536 # number of overall hits +system.l2c.overall_hits::total 5495748 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 5517 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 8182 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 12718 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 197063 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 598730 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 5285 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 7231 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 8328 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 136549 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 456002 # number of ReadReq misses +system.l2c.ReadReq_misses::total 1435605 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 38751 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 39177 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 77928 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 11922 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 9604 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 21526 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 91592 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 67962 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 159554 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 5517 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 8182 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 12718 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 288655 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 598730 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 5285 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 7231 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 8328 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 204511 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 456002 # number of demand (read+write) misses +system.l2c.demand_misses::total 1595159 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 5517 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 8182 # number of overall misses +system.l2c.overall_misses::cpu0.inst 12718 # number of overall misses +system.l2c.overall_misses::cpu0.data 288655 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 598730 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 5285 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 7231 # number of overall misses +system.l2c.overall_misses::cpu1.inst 8328 # number of overall misses +system.l2c.overall_misses::cpu1.data 204511 # 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number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 660185236 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1228334988 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 25732141326 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 72887603477 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 440607992 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 598540979 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 788794491 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 18249861178 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 55801999034 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 176846928195 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4307750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 913284750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11755622000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.220588 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.246804 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.391250 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.583710 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.164922 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.210253 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.575641 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.554899 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.565023 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.571360 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.563483 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.567819 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.631869 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.224847 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80451.468412 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 81359.470904 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 101975.362824 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10304.809373 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10376.553947 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10340.877759 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10367.861265 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10379.670762 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10373.130168 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68715.351155 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67723.577249 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 68292.905223 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76726.958771 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76827.288132 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 98604.649565 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 7757807 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7750243 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38586 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38586 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2284318 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1682954 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1576219 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 430271 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 347651 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 777922 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 191 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 316482 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 316482 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11788342 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9897130 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 21685472 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 381410986 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 320139805 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 701550791 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1633796 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 12761522 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.009063 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.094770 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 12645858 99.09% 99.09% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115664 0.91% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 12761522 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 21862906503 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 6130500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 19509958221 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 17925237290 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40417 # Transaction distribution +system.iobus.trans_dist::ReadResp 40417 # Transaction distribution +system.iobus.trans_dist::WriteReq 136643 # Transaction distribution +system.iobus.trans_dist::WriteResp 136782 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 139 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48150 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354398 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48170 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156191 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7497229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 982013630 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179230570 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu0.branchPred.lookups 146587108 # Number of BP lookups +system.cpu0.branchPred.condPredicted 96932064 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7164901 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 103453764 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 67642054 # Number of BTB hits +system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.branchPred.BTBHitPct 65.383850 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20270932 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 203679 # Number of incorrect RAS predictions. +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 106134781 # DTB read hits +system.cpu0.dtb.read_misses 438400 # DTB read misses +system.cpu0.dtb.write_hits 87107060 # DTB write hits +system.cpu0.dtb.write_misses 166320 # DTB write misses +system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 41289 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 449 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7213 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 39737 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 106573181 # DTB read accesses +system.cpu0.dtb.write_accesses 87273380 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 193241841 # DTB hits +system.cpu0.dtb.misses 604720 # DTB misses +system.cpu0.dtb.accesses 193846561 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 230537480 # ITB inst hits +system.cpu0.itb.inst_misses 86000 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 29668 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 226388 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 230623480 # ITB inst accesses +system.cpu0.itb.hits 230537480 # DTB hits +system.cpu0.itb.misses 86000 # DTB misses +system.cpu0.itb.accesses 230623480 # DTB accesses +system.cpu0.numCycles 786965482 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.fetch.icacheStallCycles 90387711 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 647691070 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 146587108 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 87912986 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 665690431 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15471710 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1846295 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 143165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6476529 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 786234 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 320116 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 230311190 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1742140 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 28723 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 773386336 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.980975 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.219702 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 409957196 53.01% 53.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 140998975 18.23% 71.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 49617031 6.42% 77.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 172813134 22.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 773386336 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.186269 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.823023 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 108593313 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 378356513 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 240969730 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 39977542 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5489238 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 21224089 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2292433 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 668689408 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 25030555 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5489238 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 146312922 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 57383456 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 250430469 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 242520551 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 71249700 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 650266707 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6336504 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 9477139 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 381865 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 840506 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 33815177 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 14484 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 619540415 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1001273329 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 768127423 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 806411 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 558016180 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 61524234 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16309942 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14158531 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 81487680 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 106551444 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90697387 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9851628 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8566406 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 626998472 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16435650 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 631073777 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2910747 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 54340762 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 37568320 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 303534 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 773386336 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.815988 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.066561 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 429333552 55.51% 55.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 143479671 18.55% 74.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 122471651 15.84% 89.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 69760577 9.02% 98.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8335355 1.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5527 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 3 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 773386336 # Number of insts issued each cycle +system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 65856729 45.73% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 73447 0.05% 45.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 22232 0.02% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 47 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 37876967 26.30% 72.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 40192311 27.91% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 431505224 68.38% 68.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1606072 0.25% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 80666 0.01% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 12 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 46680 0.01% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 109370672 17.33% 85.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88464450 14.02% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::total 631073777 # Type of FU issued +system.cpu0.iq.rate 0.801908 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 144021733 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228217 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2181305203 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 697468177 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 613392938 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1161167 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 463347 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 426941 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 774373560 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 721950 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2923759 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.squashedLoads 13150556 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17424 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 157648 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6172607 # Number of stores squashed +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.rescheduledLoads 2931375 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4759724 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewSquashCycles 5489238 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8266633 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 4717216 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 643560247 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 106551444 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90697387 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13867290 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 61805 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4582618 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 157648 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2155844 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3101202 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5257046 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 622852330 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 106129153 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7624905 # Number of squashed instructions skipped in execute +system.cpu0.iew.exec_swp 0 # number of swp insts executed +system.cpu0.iew.exec_nop 126125 # number of nop insts executed +system.cpu0.iew.exec_refs 193235409 # number of memory reference insts executed +system.cpu0.iew.exec_branches 117777762 # Number of branches executed +system.cpu0.iew.exec_stores 87106256 # Number of stores executed +system.cpu0.iew.exec_rate 0.791461 # Inst execution rate +system.cpu0.iew.wb_sent 614619625 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 613819879 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 298670143 # num instructions producing a value +system.cpu0.iew.wb_consumers 489758313 # num instructions consuming a value +system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu0.iew.wb_rate 0.779983 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609832 # average fanout of values written-back +system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu0.commit.commitSquashedInsts 50622338 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 16132116 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4918284 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 763797135 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.766621 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.569865 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 508551807 66.58% 66.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 131505056 17.22% 83.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 56862924 7.44% 91.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18814885 2.46% 93.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13980697 1.83% 95.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9342143 1.22% 96.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6309382 0.83% 97.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 4063980 0.53% 98.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14366261 1.88% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 763797135 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 498729441 # Number of instructions committed +system.cpu0.commit.committedOps 585543302 # Number of ops (including micro ops) committed +system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu0.commit.refs 177925668 # Number of memory references committed +system.cpu0.commit.loads 93400888 # Number of loads committed +system.cpu0.commit.membars 4075726 # Number of memory barriers committed +system.cpu0.commit.branches 111746625 # Number of branches committed +system.cpu0.commit.fp_insts 417930 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 537600399 # Number of committed integer instructions. +system.cpu0.commit.function_calls 15117239 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 406177320 69.37% 69.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1336444 0.23% 69.60% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 63141 0.01% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 40729 0.01% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 93400888 15.95% 85.56% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 84524780 14.44% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::total 585543302 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14366261 # number cycles where commit BW limit reached +system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu0.rob.rob_reads 1380974813 # The number of ROB reads +system.cpu0.rob.rob_writes 1281884282 # The number of ROB writes +system.cpu0.timesIdled 846185 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 13579146 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93972383800 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 498729441 # Number of Instructions Simulated +system.cpu0.committedOps 585543302 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.577941 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.577941 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.633737 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.633737 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 735405419 # number of integer regfile reads +system.cpu0.int_regfile_writes 437369435 # number of integer regfile writes +system.cpu0.fp_regfile_reads 697220 # number of floating regfile reads +system.cpu0.fp_regfile_writes 340900 # number of floating regfile writes +system.cpu0.cc_regfile_reads 134840784 # number of cc regfile reads +system.cpu0.cc_regfile_writes 135500502 # number of cc regfile writes +system.cpu0.misc_regfile_reads 3071585466 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16203449 # number of misc regfile writes +system.cpu0.toL2Bus.trans_dist::ReadReq 15637085 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 12009481 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 33046 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33046 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3548344 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 4365503 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1683195 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 1040668 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 461767 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 386684 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 535373 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1436156 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1297014 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 13051451 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18246800 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 419537 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1341455 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 33059243 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 416613216 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 664873226 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1541384 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4934904 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1087962730 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 9586812 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 27467610 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.337349 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.472805 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 18201451 66.27% 66.27% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 9266159 33.73% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 27467610 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 13754094390 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 197445482 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 9792438220 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 9396795912 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 228193109 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 726243001 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu0.icache.tags.replacements 6503720 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.971418 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 223511778 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6504232 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.364054 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8400074750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.971418 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999944 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999944 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 266 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 184 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 467078613 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 467078613 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 223511778 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 223511778 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 223511778 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 223511778 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 223511778 # number of overall hits +system.cpu0.icache.overall_hits::total 223511778 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6775226 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6775226 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6775226 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6775226 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6775226 # number of overall misses +system.cpu0.icache.overall_misses::total 6775226 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 58809305620 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 58809305620 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 58809305620 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 58809305620 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 58809305620 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 58809305620 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 230287004 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 230287004 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 230287004 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 230287004 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 230287004 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 230287004 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029421 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029421 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029421 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029421 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029421 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029421 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8680.050764 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8680.050764 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8680.050764 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8680.050764 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8680.050764 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8680.050764 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4711788 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 167 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 607280 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.758839 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 167 # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 270621 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 270621 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 270621 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 270621 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 270621 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 270621 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6504605 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6504605 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6504605 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6504605 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6504605 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6504605 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 47647231055 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 47647231055 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 47647231055 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 47647231055 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 47647231055 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 47647231055 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1699559498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1699559498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028246 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028246 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028246 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028246 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028246 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028246 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7325.153650 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7325.153650 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7325.153650 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7325.153650 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7325.153650 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7325.153650 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 59245032 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2351166 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 52469358 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1249562 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 200789 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2974157 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4925432 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.tags.replacements 3747306 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16276.136731 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 13593053 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 3763332 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.611973 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 6997709500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4266.822439 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 59.073583 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 61.998615 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 875.814301 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3003.067946 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8009.359846 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.260426 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003606 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003784 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.053455 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.183293 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.488853 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.993417 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8909 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 95 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7022 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 203 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 252 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3635 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3246 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1573 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 11 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 72 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 759 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2892 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2491 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 768 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.543762 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005798 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.428589 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 294843936 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 294843936 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 600493 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 179726 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 6257574 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 3196043 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 10233836 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 3548335 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 3548335 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 119384 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 119384 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 38955 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 38955 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 985595 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 985595 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 600493 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 179726 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 6257574 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 4181638 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 11219431 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 600493 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 179726 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 6257574 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 4181638 # number of overall hits +system.cpu0.l2cache.overall_hits::total 11219431 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 16370 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12947 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 246684 # 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mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.818029 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.200020 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.200020 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026536 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066288 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.028093 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.251089 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.126143 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026536 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066288 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.028093 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.251089 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.354862 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 30124.578689 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29676.550699 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 35601.440437 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 35601.440437 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17421.943421 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17421.943421 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13837.367604 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13837.367604 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 181083.277778 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 181083.277778 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40961.276755 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40961.276755 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32082.226080 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31451.797521 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32082.226080 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 35601.440437 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34126.366499 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.tags.replacements 6421778 # number of replacements +system.cpu0.dcache.tags.tagsinuse 503.783649 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 165065902 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6422290 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.702032 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1750084500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.783649 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983952 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.983952 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 369226254 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 369226254 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 86280065 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86280065 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73574281 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73574281 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 230862 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 230862 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 1040668 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 1040668 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1948592 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1948592 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1987329 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1987329 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 159854346 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 159854346 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 160085208 # number of overall hits +system.cpu0.dcache.overall_hits::total 160085208 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7331765 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7331765 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7708797 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7708797 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 740087 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 740087 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 294779 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 294779 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 214098 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 214098 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 15040562 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 15040562 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 15780649 # number of overall misses +system.cpu0.dcache.overall_misses::total 15780649 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 115068880578 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 115068880578 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 135208359707 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 135208359707 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4223400082 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4223400082 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4534810216 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4534810216 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4219500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4219500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 250277240285 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 250277240285 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 250277240285 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 250277240285 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 93611830 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 93611830 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81283078 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81283078 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 970949 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 970949 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1040668 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1040668 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2243371 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2243371 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2201427 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2201427 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 174894908 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 174894908 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 175865857 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 175865857 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078321 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.078321 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.094839 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.094839 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.762231 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.762231 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.131400 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.131400 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097254 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097254 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085998 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.085998 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089731 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.089731 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15694.567485 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15694.567485 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17539.488938 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17539.488938 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14327.343814 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14327.343814 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21181.002233 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21181.002233 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16640.152162 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16640.152162 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15859.755849 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15859.755849 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 17082084 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 19003690 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 950552 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 748671 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.970699 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 25.383232 # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 1040668 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 3548346 # number of writebacks +system.cpu0.dcache.writebacks::total 3548346 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3808172 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3808172 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6155071 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6155071 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 150940 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 150940 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9963243 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9963243 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9963243 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9963243 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3523593 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3523593 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1532184 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1532184 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 733570 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 733570 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 143839 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 143839 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 214091 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 214091 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5055777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5055777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5789347 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5789347 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48006705459 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48006705459 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27570008615 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27570008615 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18661725527 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18661725527 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 57519686561 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 57519686561 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1764532424 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1764532424 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4095364784 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4095364784 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4027500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4027500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 75576714074 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 75576714074 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94238439601 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 94238439601 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5807383412 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5807383412 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5600359921 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5600359921 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11407743333 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11407743333 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037640 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037640 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018850 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018850 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.755519 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.755519 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064117 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064117 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097251 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097251 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028908 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028908 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032919 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032919 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13624.361684 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13624.361684 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17993.928024 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17993.928024 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25439.597485 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25439.597485 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12267.413038 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12267.413038 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19129.084287 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19129.084287 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14948.585366 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14948.585366 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16277.904849 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16277.904849 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.branchPred.lookups 126883394 # Number of BP lookups +system.cpu1.branchPred.condPredicted 85166335 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6223569 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 90014178 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 58475937 # Number of BTB hits +system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.branchPred.BTBHitPct 64.963029 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16774062 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 171946 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 93423769 # DTB read hits +system.cpu1.dtb.read_misses 385141 # DTB read misses +system.cpu1.dtb.write_hits 77506370 # DTB write hits +system.cpu1.dtb.write_misses 166753 # DTB write misses +system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 38053 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 411 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6413 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 42956 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 93808910 # DTB read accesses +system.cpu1.dtb.write_accesses 77673123 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 170930139 # DTB hits +system.cpu1.dtb.misses 551894 # DTB misses +system.cpu1.dtb.accesses 171482033 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 200532583 # ITB inst hits +system.cpu1.itb.inst_misses 85074 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26827 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 221691 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 200617657 # ITB inst accesses +system.cpu1.itb.hits 200532583 # DTB hits +system.cpu1.itb.misses 85074 # DTB misses +system.cpu1.itb.accesses 200617657 # DTB accesses +system.cpu1.numCycles 671498045 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.fetch.icacheStallCycles 76057268 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 563958948 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 126883394 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 75249999 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 570112426 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13401984 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1796129 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 140886 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6366912 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 711415 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 284551 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 200289545 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1511940 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 28568 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 662170579 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.001134 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.225253 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 344731960 52.06% 52.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 123888404 18.71% 70.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 41617512 6.29% 77.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 151932703 22.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 662170579 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.188956 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.839852 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 93652150 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 319101856 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 208055943 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 36600277 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4760353 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17735520 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1981049 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 585316730 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21686226 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4760353 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 127273008 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 44978505 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 215016897 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 210494675 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 59647141 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 569572737 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5483527 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8310630 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 236317 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 296206 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 25698514 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 13591 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 543172602 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 884661173 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 673765883 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 933137 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 489609146 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 53563450 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15680851 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13859127 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 73666324 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 93680638 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 80687792 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8658535 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7660349 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 547737456 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15869030 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 553093233 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2542275 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 47705580 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 32628806 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 263861 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 662170579 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.835273 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.067651 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 358036858 54.07% 54.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 130663379 19.73% 73.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 105371554 15.91% 89.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 60712008 9.17% 98.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7383178 1.11% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3602 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 662170579 # Number of insts issued each cycle +system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 55137578 43.73% 43.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 43337 0.03% 43.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 11462 0.01% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 21 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 33948572 26.92% 70.70% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 36949037 29.30% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 376818141 68.13% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1181294 0.21% 68.34% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 70304 0.01% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 78003 0.01% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 96248927 17.40% 85.77% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 78696516 14.23% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::total 553093233 # Type of FU issued +system.cpu1.iq.rate 0.823671 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 126090007 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227972 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1895671563 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 610922154 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 537423673 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1317762 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 530370 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 489519 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 678367586 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 815653 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2464833 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread0.squashedLoads 11666973 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 15967 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 141534 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5620813 # Number of stores squashed +system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread0.rescheduledLoads 2485085 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 4066782 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu1.iew.iewSquashCycles 4760353 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6088373 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2643428 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 563729528 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 93680638 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 80687792 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13644540 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 61293 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2520664 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 141534 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1916152 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2651693 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4567845 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 545961284 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 93419699 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6590982 # Number of squashed instructions skipped in execute +system.cpu1.iew.exec_swp 0 # number of swp insts executed +system.cpu1.iew.exec_nop 123042 # number of nop insts executed +system.cpu1.iew.exec_refs 170926883 # number of memory reference insts executed +system.cpu1.iew.exec_branches 102016204 # Number of branches executed +system.cpu1.iew.exec_stores 77507184 # Number of stores executed +system.cpu1.iew.exec_rate 0.813050 # Inst execution rate +system.cpu1.iew.wb_sent 538581721 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 537913192 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 259879872 # num instructions producing a value +system.cpu1.iew.wb_consumers 425846883 # num instructions consuming a value +system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu1.iew.wb_rate 0.801064 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610266 # average fanout of values written-back +system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu1.commit.commitSquashedInsts 44555907 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15605169 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4282930 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 653744993 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.784392 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.576833 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 427404365 65.38% 65.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 119117281 18.22% 83.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 49133324 7.52% 91.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 16524443 2.53% 93.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11998035 1.84% 95.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8093886 1.24% 96.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5471403 0.84% 97.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3473274 0.53% 98.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12528982 1.92% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::total 653744993 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 435068948 # Number of instructions committed +system.cpu1.commit.committedOps 512792020 # Number of ops (including micro ops) committed +system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu1.commit.refs 157080643 # Number of memory references committed +system.cpu1.commit.loads 82013664 # Number of loads committed +system.cpu1.commit.membars 3580423 # Number of memory barriers committed +system.cpu1.commit.branches 96770677 # Number of branches committed +system.cpu1.commit.fp_insts 477739 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 470356347 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12430117 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 354618766 69.15% 69.15% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 966577 0.19% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 56200 0.01% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 69792 0.01% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 82013664 15.99% 85.36% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 75066979 14.64% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::total 512792020 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12528982 # number cycles where commit BW limit reached +system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu1.rob.rob_reads 1194813735 # The number of ROB reads +system.cpu1.rob.rob_writes 1123082959 # The number of ROB writes +system.cpu1.timesIdled 724798 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 9327466 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94087851225 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 435068948 # Number of Instructions Simulated +system.cpu1.committedOps 512792020 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.543429 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.543429 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.647908 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.647908 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 645605353 # number of integer regfile reads +system.cpu1.int_regfile_writes 381721004 # number of integer regfile writes +system.cpu1.fp_regfile_reads 775313 # number of floating regfile reads +system.cpu1.fp_regfile_writes 445860 # number of floating regfile writes +system.cpu1.cc_regfile_reads 118711593 # number of cc regfile reads +system.cpu1.cc_regfile_writes 119446570 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2680324006 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15740060 # number of misc regfile writes +system.cpu1.toL2Bus.trans_dist::ReadReq 14195138 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10319504 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5540 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5540 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3043633 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 4072942 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 7 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1683351 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 535551 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 440112 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 381311 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 495883 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1326326 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1162072 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11031290 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15072798 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 408972 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1223990 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27737050 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 352998000 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 552975725 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1478304 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4387432 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 911839461 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 10107713 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 25138246 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.388398 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.487386 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 15374612 61.16% 61.16% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 9763634 38.84% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 25138246 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 11278575992 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 196968741 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 8281966249 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 7967439656 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 225433169 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 677266087 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.icache.tags.replacements 5515063 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.927395 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 194540892 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5515575 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 35.271190 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8512592975000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.927395 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980327 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980327 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 406089111 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 406089111 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 194540892 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 194540892 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 194540892 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 194540892 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 194540892 # number of overall hits +system.cpu1.icache.overall_hits::total 194540892 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5745874 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5745874 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5745874 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5745874 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5745874 # number of overall misses +system.cpu1.icache.overall_misses::total 5745874 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 49972720911 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 49972720911 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 49972720911 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 49972720911 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 49972720911 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 49972720911 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 200286766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 200286766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 200286766 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 200286766 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 200286766 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 200286766 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028688 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.028688 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028688 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.028688 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028688 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.028688 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8697.148756 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8697.148756 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8697.148756 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8697.148756 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8697.148756 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8697.148756 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 4058036 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 525950 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.715631 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 230295 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 230295 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 230295 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 230295 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 230295 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 230295 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5515579 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5515579 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5515579 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5515579 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5515579 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5515579 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 40507461081 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 40507461081 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 40507461081 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 40507461081 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 40507461081 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 40507461081 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6176248 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6176248 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6176248 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6176248 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027538 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027538 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027538 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7344.190171 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7344.190171 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7344.190171 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 50505684 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2064047 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 44628493 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 907161 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 133845 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2772138 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4283124 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.tags.replacements 3436745 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13730.844001 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 11600969 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 3452900 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 3.359776 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9794240275500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4681.996556 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.505551 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 81.585621 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 599.676687 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2582.188700 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5714.890886 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.285766 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004303 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004980 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036601 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.157604 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.348809 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.838064 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9001 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7069 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 110 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 838 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3805 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2947 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1301 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 61 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 786 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3475 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2116 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 647 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.549377 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.431458 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 248779915 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 248779915 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 532626 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 172045 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5284751 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 2703668 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 8693090 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3043623 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3043623 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 90999 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 90999 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33582 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 33582 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 896481 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 896481 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 532626 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 172045 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 5284751 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3600149 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 9589571 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 532626 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 172045 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 5284751 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3600149 # number of overall hits +system.cpu1.l2cache.overall_hits::total 9589571 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 15803 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 12743 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 230826 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 1092537 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1351909 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 10 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 10 # number of Writeback misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 129352 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 129352 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 172689 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 172689 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 17 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 17 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 259572 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 259572 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 15803 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 12743 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 230826 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1352109 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1611481 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 15803 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 12743 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 230826 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1352109 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1611481 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 757783063 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 830879579 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 5925678894 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 36970844217 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 44485185753 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2628732175 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 2628732175 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3477493272 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3477493272 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3782000 # 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average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13637.442900 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183352.941176 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183352.941176 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36902.824973 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36902.824973 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28528.009575 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28138.464180 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28528.009575 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32053.702935 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30671.695797 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.tags.replacements 5270583 # number of replacements +system.cpu1.dcache.tags.tagsinuse 418.735038 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 145844611 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5271093 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.668761 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8472891797000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 418.735038 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.817842 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.817842 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 326008687 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 326008687 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 76031229 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 76031229 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 65289331 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 65289331 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 171825 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 171825 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 535551 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 535551 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1744878 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1744878 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734724 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1734724 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 141320560 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 141320560 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 141492385 # number of overall hits +system.cpu1.dcache.overall_hits::total 141492385 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6360074 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6360074 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 7315323 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 7315323 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 690767 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 690767 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 239985 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 239985 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 206300 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 206300 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13675397 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13675397 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 14366164 # number of overall misses +system.cpu1.dcache.overall_misses::total 14366164 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96502365280 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 96502365280 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 122289774326 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 122289774326 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3384586861 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3384586861 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4391846948 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4391846948 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4067000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4067000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 218792139606 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 218792139606 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 218792139606 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 218792139606 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 82391303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 82391303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 72604654 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 72604654 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 862592 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 862592 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 535551 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 535551 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1984863 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1984863 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1941024 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1941024 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 154995957 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 154995957 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 155858549 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 155858549 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.077194 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.077194 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.100756 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.100756 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.800804 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.800804 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120908 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120908 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088231 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.088231 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092174 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.092174 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15173.151331 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15173.151331 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16716.934348 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16716.934348 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14103.326712 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14103.326712 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21288.642501 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21288.642501 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15998.960733 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15998.960733 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15229.684111 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15229.684111 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 8615413 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 17976416 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 462301 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 741969 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 18.635938 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 24.227988 # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 535551 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 3043634 # number of writebacks +system.cpu1.dcache.writebacks::total 3043634 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3366977 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3366977 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5934775 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5934775 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 123858 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 123858 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 9301752 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 9301752 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 9301752 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 9301752 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2993097 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2993097 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1369794 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1369794 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 690691 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 690691 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116127 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116127 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 206288 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 206288 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4362891 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4362891 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5053582 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5053582 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38940153004 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38940153004 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23265516814 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23265516814 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16955467787 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16955467787 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 29882890933 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 29882890933 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1431846930 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1431846930 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3970245052 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3970245052 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3877000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3877000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62205669818 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 62205669818 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 79161137605 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 79161137605 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 568928684 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 568928684 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 634602446 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 634602446 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1203531130 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1203531130 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036328 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036328 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018866 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018866 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.800716 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.800716 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058506 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058506 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106278 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106278 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028148 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028148 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032424 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032424 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13009.986981 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13009.986981 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16984.682963 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16984.682963 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24548.557585 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24548.557585 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.008783 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.008783 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19246.127026 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19246.127026 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14257.901428 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14257.901428 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15664.361953 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15664.361953 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.tags.replacements 115615 # number of replacements +system.iocache.tags.tagsinuse 11.386738 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115631 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 9111214571000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.838966 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.547771 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239935 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.471736 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.711671 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 1042022 # Number of tag accesses +system.iocache.tags.data_accesses 1042022 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses +system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses +system.iocache.WriteReq_misses::total 3 # number of WriteReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 139 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 139 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8889 # number of demand (read+write) misses +system.iocache.demand_misses::total 8929 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ethernet 40 # number of overall misses +system.iocache.overall_misses::realview.ide 8889 # number of overall misses +system.iocache.overall_misses::total 8929 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5695000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1981823591 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1987518591 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 365000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 365000 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6060000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1981823591 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1987883591 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6060000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1981823591 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1987883591 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106867 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106867 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8889 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8929 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8889 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8929 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.001301 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.001301 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 153918.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 222952.367083 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 222666.210060 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 121666.666667 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 121666.666667 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 151500 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 222952.367083 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 222632.275843 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 151500 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 222952.367083 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 222632.275843 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 55347 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.081421 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 106728 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8889 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8929 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8889 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8929 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3771000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1519438621 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1523209621 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 209000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 209000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6630698579 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6630698579 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3980000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1519438621 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1523418621 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3980000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1519438621 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1523418621 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 101918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170934.708179 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 170648.624356 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 69666.666667 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 69666.666667 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99500 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 170934.708179 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 170614.696047 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99500 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 170934.708179 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 170614.696047 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 14096 # number of quiesce instructions executed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 4921 # number of quiesce instructions executed + +---------- End Simulation Statistics ---------- |