diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:39 -0400 |
| commit | 80cd107e51ceb5aac262ec7dd82870e48d345b43 (patch) | |
| tree | 4bb545ae29522161963a8028f34ca850c98a3403 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual | |
| parent | 2847d5f5177304236dcdbab112a0369f0bd96aea (diff) | |
| download | gem5-80cd107e51ceb5aac262ec7dd82870e48d345b43.tar.xz | |
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt | 6316 |
1 files changed, 3180 insertions, 3136 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 417d3b817..49f083338 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,167 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.305566 # Number of seconds simulated -sim_ticks 47305566199500 # Number of ticks simulated -final_tick 47305566199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.385466 # Number of seconds simulated +sim_ticks 47385466309500 # Number of ticks simulated +final_tick 47385466309500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108918 # Simulator instruction rate (inst/s) -host_op_rate 128082 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5794473291 # Simulator tick rate (ticks/s) -host_mem_usage 707548 # Number of bytes of host memory used -host_seconds 8163.91 # Real time elapsed on the host -sim_insts 889196991 # Number of instructions simulated -sim_ops 1045647845 # Number of ops (including micro ops) simulated +host_inst_rate 109383 # Simulator instruction rate (inst/s) +host_op_rate 128637 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5566054279 # Simulator tick rate (ticks/s) +host_mem_usage 771804 # Number of bytes of host memory used +host_seconds 8513.30 # Real time elapsed on the host +sim_insts 931207580 # Number of instructions simulated +sim_ops 1095127739 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 75776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 60928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4503136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 12909720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 13016640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 167424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 164416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2523040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10482528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 14576384 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 439104 # Number of bytes read from this memory -system.physmem.bytes_read::total 58919096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4503136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2523040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7026176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75116864 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 167872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 148672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4509472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 15471624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 18877376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 171456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 164224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3092064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12069648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 17196544 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 427520 # Number of bytes read from this memory +system.physmem.bytes_read::total 72296472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4509472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3092064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7601536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 87689472 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 75137680 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1184 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 952 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 86314 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 201736 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 203385 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2569 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 39466 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 163804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 227756 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6861 # Number of read requests responded to by this memory -system.physmem.num_reads::total 936643 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1173701 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 87710056 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2623 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2323 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 86413 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 241757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 294959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2679 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2566 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 48357 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 188601 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 268696 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6680 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1145654 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1370148 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1176304 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 95193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 272901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 275161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3539 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 221592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 308133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1245500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 95193 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 148527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1587908 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 440 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1372722 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 95166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 326506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 398379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 65253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 254712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 362908 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1525710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 95166 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 65253 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 160419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1850556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1588348 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1587908 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 95193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 273341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 275161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 221592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 308133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2833848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 936643 # Number of read requests accepted -system.physmem.writeReqs 1837953 # Number of write requests accepted -system.physmem.readBursts 936643 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1837953 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59924608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue -system.physmem.bytesWritten 114470976 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 58919096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 117483216 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 49325 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 117374 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 55305 # Per bank write bursts -system.physmem.perBankRdBursts::1 59995 # Per bank write bursts -system.physmem.perBankRdBursts::2 52034 # Per bank write bursts -system.physmem.perBankRdBursts::3 56018 # Per bank write bursts -system.physmem.perBankRdBursts::4 58058 # Per bank write bursts -system.physmem.perBankRdBursts::5 68871 # Per bank write bursts -system.physmem.perBankRdBursts::6 59545 # Per bank write bursts -system.physmem.perBankRdBursts::7 57406 # Per bank write bursts -system.physmem.perBankRdBursts::8 51483 # Per bank write bursts -system.physmem.perBankRdBursts::9 77850 # Per bank write bursts -system.physmem.perBankRdBursts::10 53930 # Per bank write bursts -system.physmem.perBankRdBursts::11 57982 # Per bank write bursts -system.physmem.perBankRdBursts::12 54532 # Per bank write bursts -system.physmem.perBankRdBursts::13 56851 # Per bank write bursts -system.physmem.perBankRdBursts::14 60976 # Per bank write bursts -system.physmem.perBankRdBursts::15 55486 # Per bank write bursts -system.physmem.perBankWrBursts::0 110085 # Per bank write bursts -system.physmem.perBankWrBursts::1 112883 # Per bank write bursts -system.physmem.perBankWrBursts::2 108062 # Per bank write bursts -system.physmem.perBankWrBursts::3 109070 # Per bank write bursts -system.physmem.perBankWrBursts::4 113169 # Per bank write bursts -system.physmem.perBankWrBursts::5 118310 # Per bank write bursts -system.physmem.perBankWrBursts::6 115499 # Per bank write bursts -system.physmem.perBankWrBursts::7 111959 # Per bank write bursts -system.physmem.perBankWrBursts::8 107874 # Per bank write bursts -system.physmem.perBankWrBursts::9 113071 # Per bank write bursts -system.physmem.perBankWrBursts::10 109141 # Per bank write bursts -system.physmem.perBankWrBursts::11 113654 # Per bank write bursts -system.physmem.perBankWrBursts::12 105244 # Per bank write bursts -system.physmem.perBankWrBursts::13 111328 # Per bank write bursts -system.physmem.perBankWrBursts::14 115976 # Per bank write bursts -system.physmem.perBankWrBursts::15 113284 # Per bank write bursts +system.physmem.bw_write::total 1850991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1850556 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 95166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 326940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 398379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 65253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 254712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 362908 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3376701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1145654 # Number of read requests accepted +system.physmem.writeReqs 2060182 # Number of write requests accepted +system.physmem.readBursts 1145654 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2060182 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 73301632 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20224 # Total number of bytes read from write queue +system.physmem.bytesWritten 128743424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 72296472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 131707496 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 316 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 48535 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 120456 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 65572 # Per bank write bursts +system.physmem.perBankRdBursts::1 75328 # Per bank write bursts +system.physmem.perBankRdBursts::2 66668 # Per bank write bursts +system.physmem.perBankRdBursts::3 73797 # Per bank write bursts +system.physmem.perBankRdBursts::4 73498 # Per bank write bursts +system.physmem.perBankRdBursts::5 82651 # Per bank write bursts +system.physmem.perBankRdBursts::6 70750 # Per bank write bursts +system.physmem.perBankRdBursts::7 70075 # Per bank write bursts +system.physmem.perBankRdBursts::8 62480 # Per bank write bursts +system.physmem.perBankRdBursts::9 88491 # Per bank write bursts +system.physmem.perBankRdBursts::10 66146 # Per bank write bursts +system.physmem.perBankRdBursts::11 72268 # Per bank write bursts +system.physmem.perBankRdBursts::12 67491 # Per bank write bursts +system.physmem.perBankRdBursts::13 74959 # Per bank write bursts +system.physmem.perBankRdBursts::14 69333 # Per bank write bursts +system.physmem.perBankRdBursts::15 65831 # Per bank write bursts +system.physmem.perBankWrBursts::0 122352 # Per bank write bursts +system.physmem.perBankWrBursts::1 129436 # Per bank write bursts +system.physmem.perBankWrBursts::2 124260 # Per bank write bursts +system.physmem.perBankWrBursts::3 131298 # Per bank write bursts +system.physmem.perBankWrBursts::4 127700 # Per bank write bursts +system.physmem.perBankWrBursts::5 133890 # Per bank write bursts +system.physmem.perBankWrBursts::6 125807 # Per bank write bursts +system.physmem.perBankWrBursts::7 124647 # Per bank write bursts +system.physmem.perBankWrBursts::8 116114 # Per bank write bursts +system.physmem.perBankWrBursts::9 124444 # Per bank write bursts +system.physmem.perBankWrBursts::10 122980 # Per bank write bursts +system.physmem.perBankWrBursts::11 126137 # Per bank write bursts +system.physmem.perBankWrBursts::12 123363 # Per bank write bursts +system.physmem.perBankWrBursts::13 128612 # Per bank write bursts +system.physmem.perBankWrBursts::14 126014 # Per bank write bursts +system.physmem.perBankWrBursts::15 124562 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 81608 # Number of times write queue was full causing retry -system.physmem.totGap 47305564753000 # Total gap between requests +system.physmem.numWrRetry 81198 # Number of times write queue was full causing retry +system.physmem.totGap 47385464863500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 37 # Read request sizes (log2) +system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 915273 # Read request sizes (log2) +system.physmem.readPktSize::6 1124296 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) -system.physmem.writePktSize::3 2601 # Write request sizes (log2) +system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1835350 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 429452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 211261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 82392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 54481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 35792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 29912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 27031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 22393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 8038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2057608 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 487455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 272298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 106854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 72030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 47157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 39210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35683 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 33198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -188,136 +188,136 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 42762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 50992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 57625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 67617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 70370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 78632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 77296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 79817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 88544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 82050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 81883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 102987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 87472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 82523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 74776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 11408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 9295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 8966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 9255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 7640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 7439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 6226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 5791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 5896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 4222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 3205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 3127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 3002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 2825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 2954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 7063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 7984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 354953 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 953575 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 182.885667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.719338 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 252.430373 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 592274 62.11% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 190618 19.99% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51298 5.38% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22604 2.37% 89.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16941 1.78% 91.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10334 1.08% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7600 0.80% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7080 0.74% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 54826 5.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 953575 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60764 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.409042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 72.355469 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 60757 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 29112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 57284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 64958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 76298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 77584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 81647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 91142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 91147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 94824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 104842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 97550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 99736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 122228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 105767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 99735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 90681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 12739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 9828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 8556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 10053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 7840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 7547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 6708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 6021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 6115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 5369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 3218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 352485 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1120451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 180.324302 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.099448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 247.440504 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 698811 62.37% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 221320 19.75% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 61667 5.50% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27543 2.46% 90.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21267 1.90% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12605 1.12% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9064 0.81% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8274 0.74% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 59900 5.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1120451 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 73379 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.608158 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 65.872388 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 73373 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60764 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60764 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 29.435340 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.473917 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 995.068690 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-4095 60761 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 73379 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 73379 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.414056 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.095862 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 903.451601 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-4095 73376 100.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::98304-102399 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::102400-106495 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192512-196607 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60764 # Writes before turning the bus around for reads -system.physmem.totQLat 43948740923 # Total ticks spent queuing -system.physmem.totMemAccLat 61504778423 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4681610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 46937.64 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 73379 # Writes before turning the bus around for reads +system.physmem.totQLat 58866128789 # Total ticks spent queuing +system.physmem.totMemAccLat 80341216289 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5726690000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51396.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 65687.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.48 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 70146.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.58 # Average write queue length when enqueuing -system.physmem.readRowHits 706637 # Number of row buffer hits during reads -system.physmem.writeRowHits 1064717 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.53 # Row buffer hit rate for writes -system.physmem.avgGap 17049532.53 # Average gap between requests -system.physmem.pageHitRate 65.01 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3636465840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1984182750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3644362800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5825759760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1155369631905 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27369856613250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31630086518865 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.633528 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45532077679143 # Time in different power states -system.physmem_0.memoryStateTime::REF 1579636760000 # Time in different power states +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing +system.physmem.readRowHits 867894 # Number of row buffer hits during reads +system.physmem.writeRowHits 1168605 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.09 # Row buffer hit rate for writes +system.physmem.avgGap 14781000.92 # Average gap between requests +system.physmem.pageHitRate 64.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4336385760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2366083500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4510974000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6605647200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3094987836720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1170067048560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27404900969250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31687774944990 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.723600 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45590272941113 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582304620000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 193851315857 # Time in different power states +system.physmem_0.memoryStateTime::ACT 212884395887 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3572561160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1949314125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3658902000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5764426560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1152447208560 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27372420142500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31629582057465 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.622864 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45536350688414 # Time in different power states -system.physmem_1.memoryStateTime::REF 1579636760000 # Time in different power states +system.physmem_1.actEnergy 4134208680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2255768625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4422568800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6429624480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3094987836720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1167604821270 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27407060817750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31686895646325 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.705044 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45593855726560 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582304620000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 189577142836 # Time in different power states +system.physmem_1.memoryStateTime::ACT 209300747940 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -351,15 +351,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 136259129 # Number of BP lookups -system.cpu0.branchPred.condPredicted 90543195 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6799058 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 95853282 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 62504832 # Number of BTB hits +system.cpu0.branchPred.lookups 143219505 # Number of BP lookups +system.cpu0.branchPred.condPredicted 95215917 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6874228 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 100849572 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 65904871 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.208860 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 18504887 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 186011 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.349678 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 19505246 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 190029 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -390,85 +390,88 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 520196 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 520196 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10690 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 81668 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 225929 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 294267 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 1575.669375 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 10064.565371 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 292845 99.52% 99.52% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1067 0.36% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 263 0.09% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 47 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 294267 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 252771 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 15945.045037 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 13637.155107 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 11018.196964 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 241135 95.40% 95.40% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10520 4.16% 99.56% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 548 0.22% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 339 0.13% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 68 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 47 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 65 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 16 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 252771 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 499007353192 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.597965 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.527283 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 498187132192 99.84% 99.84% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 450171500 0.09% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 169118500 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 80846500 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 62229500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 34680000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 10096500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 12800000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 278500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 499007353192 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 81668 88.43% 88.43% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10690 11.57% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 92358 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 520196 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 557114 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 557114 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11925 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88835 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 245678 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 311436 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 1783.814331 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 11278.873416 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 309571 99.40% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1396 0.45% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 332 0.11% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 57 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 59 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 14 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 311436 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 275434 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 16916.133019 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 14128.427647 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15086.481481 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 261399 94.90% 94.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 11343 4.12% 99.02% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1146 0.42% 99.44% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 802 0.29% 99.73% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 102 0.04% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 163 0.06% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 287 0.10% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 70 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 43 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 36 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 22 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 275434 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 527372589640 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.581951 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.533395 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 526425698140 99.82% 99.82% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 513345500 0.10% 99.92% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 204440500 0.04% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 94120000 0.02% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 67519500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 37561500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 13535000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 16113500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 245000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 527372589640 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 88835 88.16% 88.16% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11925 11.84% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 100760 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 557114 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 520196 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92358 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 557114 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 100760 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92358 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 612554 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 100760 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 657874 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 98496070 # DTB read hits -system.cpu0.dtb.read_misses 369414 # DTB read misses -system.cpu0.dtb.write_hits 81551465 # DTB write hits -system.cpu0.dtb.write_misses 150782 # DTB write misses +system.cpu0.dtb.read_hits 103903304 # DTB read hits +system.cpu0.dtb.read_misses 386941 # DTB read misses +system.cpu0.dtb.write_hits 87265042 # DTB write hits +system.cpu0.dtb.write_misses 170173 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36102 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 400 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5365 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 37535 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 216 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 6819 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 40284 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 98865484 # DTB read accesses -system.cpu0.dtb.write_accesses 81702247 # DTB write accesses +system.cpu0.dtb.perms_faults 40407 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 104290245 # DTB read accesses +system.cpu0.dtb.write_accesses 87435215 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 180047535 # DTB hits -system.cpu0.dtb.misses 520196 # DTB misses -system.cpu0.dtb.accesses 180567731 # DTB accesses +system.cpu0.dtb.hits 191168346 # DTB hits +system.cpu0.dtb.misses 557114 # DTB misses +system.cpu0.dtb.accesses 191725460 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -498,1116 +501,1134 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 81590 # Table walker walks requested -system.cpu0.itb.walker.walksLong 81590 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 901 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59909 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 9188 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 72402 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 845.170023 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 6470.995618 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 72024 99.48% 99.48% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 242 0.33% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 56 0.08% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 61 0.08% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 85759 # Table walker walks requested +system.cpu0.itb.walker.walksLong 85759 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 908 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 62470 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 9907 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 75852 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1136.575173 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 8938.964276 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 75266 99.23% 99.23% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 257 0.34% 99.57% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 133 0.18% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 159 0.21% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 72402 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 69998 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 20035.793294 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 17827.568317 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 13688.582598 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 69301 99.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 578 0.83% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 67 0.10% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 29 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 75852 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 73285 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 21415.899529 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 18467.660437 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19009.032462 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 71796 97.97% 97.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1220 1.66% 99.63% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 122 0.17% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 69 0.09% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 44 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 12 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 69998 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 370135740312 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.825869 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.379347 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 64468447528 17.42% 17.42% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 305652352784 82.58% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 13699000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1205500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 370135740312 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 59909 98.52% 98.52% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 901 1.48% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 60810 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 73285 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 394225556964 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.858766 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.348387 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 55694159292 14.13% 14.13% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 338516533172 85.87% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 13791500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1055500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 17500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 394225556964 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 62470 98.57% 98.57% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 908 1.43% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 63378 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81590 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81590 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85759 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85759 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60810 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60810 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 142400 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 213929001 # ITB inst hits -system.cpu0.itb.inst_misses 81590 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 63378 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 63378 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 149137 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 225166936 # ITB inst hits +system.cpu0.itb.inst_misses 85759 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25953 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26709 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 203878 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 217420 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 214010591 # ITB inst accesses -system.cpu0.itb.hits 213929001 # DTB hits -system.cpu0.itb.misses 81590 # DTB misses -system.cpu0.itb.accesses 214010591 # DTB accesses -system.cpu0.numCycles 728554790 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 225252695 # ITB inst accesses +system.cpu0.itb.hits 225166936 # DTB hits +system.cpu0.itb.misses 85759 # DTB misses +system.cpu0.itb.accesses 225252695 # DTB accesses +system.cpu0.numCycles 777590959 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 88185009 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 601844339 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 136259129 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81009719 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 601618645 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14617520 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1590376 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 274448 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 5655980 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 730298 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 721373 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 213725526 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1720356 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 27419 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 706084889 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.998504 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.224315 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 90148881 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 632830647 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 143219505 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 85410117 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 647310508 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14846236 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1771940 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 282653 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6199385 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 737729 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 721364 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 224948990 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1718929 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 28705 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 754595578 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.984480 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.221164 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 368651970 52.21% 52.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 130906496 18.54% 70.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 45457211 6.44% 77.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 161069212 22.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 398817072 52.85% 52.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 138444624 18.35% 71.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 47562041 6.30% 77.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 169771841 22.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 706084889 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.187027 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.826080 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 103877352 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 333585554 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 228251571 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 35190646 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5179766 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19720762 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2170804 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 623516514 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23718954 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5179766 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 138234059 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 46790455 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 227164838 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 228535971 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 60179800 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 606373965 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6065859 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 8641063 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 231610 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 454065 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 27284745 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11061 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 577786095 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 931076470 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 716156173 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 752358 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 519674265 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 58111818 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 14452887 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 12546195 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 71496186 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 99205558 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 84922074 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 8773729 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 7651066 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 585335843 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 14506928 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 587846614 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2739409 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 54557687 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 35502721 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 263475 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 706084889 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.832544 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.074450 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 754595578 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.184184 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.813835 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 107688832 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 365256192 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 237731032 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 38638584 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5280938 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 20683549 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2184734 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 657953246 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23988018 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5280938 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 144086550 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 51798126 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 247348242 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 239349699 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 66732023 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 640403541 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6134927 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 9593053 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 279391 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 288384 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 30790790 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11378 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 609803525 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 987601051 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 757009838 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 819226 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 550929032 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 58874487 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16040201 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14019715 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 78263207 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 104115554 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90761559 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9526213 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8179417 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 617656959 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16134834 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 622248752 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2762846 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 55648828 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 35830856 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 282296 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 754595578 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.824612 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.071196 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 387752647 54.92% 54.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 129908491 18.40% 73.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 115071565 16.30% 89.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 65618038 9.29% 98.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7729861 1.09% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 4287 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 416444489 55.19% 55.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 139981431 18.55% 73.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 120577545 15.98% 89.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 69261363 9.18% 98.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8325608 1.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5142 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 706084889 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 754595578 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 62081849 46.00% 46.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 53806 0.04% 46.04% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 26012 0.02% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 10 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 34882864 25.85% 71.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 37902238 28.09% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 64632492 45.32% 45.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 49764 0.03% 45.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 24321 0.02% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 8 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 36912792 25.88% 71.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 41006253 28.75% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 401971331 68.38% 68.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1424969 0.24% 68.62% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 76351 0.01% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 44028 0.01% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 101506921 17.27% 85.91% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82822965 14.09% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 425093937 68.32% 68.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1435088 0.23% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 72707 0.01% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 80017 0.01% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 106973715 17.19% 85.76% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88593239 14.24% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 587846614 # Type of FU issued -system.cpu0.iq.rate 0.806867 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 134946779 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.229561 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2018256641 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 654059965 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 571438682 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1207660 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 478909 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 443638 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 722040340 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 753051 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2688850 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 622248752 # Type of FU issued +system.cpu0.iq.rate 0.800226 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 142625630 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.229210 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2143120412 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 689044772 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 604966692 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1361144 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 552290 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 506244 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 764032585 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 841796 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2890526 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12347690 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 15246 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 139538 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5796061 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12594321 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 16775 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 157768 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6060902 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2638151 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4049170 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2889033 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4437246 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5179766 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6081153 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 2925805 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 599957845 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5280938 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6404578 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 3121375 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 633914393 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 99205558 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 84922074 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 12284210 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 51884 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2819346 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 139538 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2067264 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2909526 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4976790 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 580052597 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 98485742 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7283117 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 104115554 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90761559 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13746258 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 66239 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2987519 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 157768 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2095186 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2941806 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5036992 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 614307958 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 103896068 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7396426 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 115074 # number of nop insts executed -system.cpu0.iew.exec_refs 180036231 # number of memory reference insts executed -system.cpu0.iew.exec_branches 109604684 # Number of branches executed -system.cpu0.iew.exec_stores 81550489 # Number of stores executed -system.cpu0.iew.exec_rate 0.796169 # Inst execution rate -system.cpu0.iew.wb_sent 572646335 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 571882320 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 278067639 # num instructions producing a value -system.cpu0.iew.wb_consumers 456095391 # num instructions consuming a value +system.cpu0.iew.exec_nop 122600 # number of nop insts executed +system.cpu0.iew.exec_refs 191163401 # number of memory reference insts executed +system.cpu0.iew.exec_branches 115873704 # Number of branches executed +system.cpu0.iew.exec_stores 87267333 # Number of stores executed +system.cpu0.iew.exec_rate 0.790014 # Inst execution rate +system.cpu0.iew.wb_sent 606266119 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 605472936 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 293481694 # num instructions producing a value +system.cpu0.iew.wb_consumers 481488998 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.784954 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609670 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.778652 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609529 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 47584416 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14243453 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4670064 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 697066716 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.782257 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.580851 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 48614829 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15852538 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4732048 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 745378077 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775637 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.576449 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 460295975 66.03% 66.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 120461861 17.28% 83.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 53495228 7.67% 90.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 18161397 2.61% 93.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13064824 1.87% 95.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8746806 1.25% 96.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5864289 0.84% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3641188 0.52% 98.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 13335148 1.91% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 493396348 66.19% 66.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 129662648 17.40% 83.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 56044004 7.52% 91.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18992920 2.55% 93.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13761945 1.85% 95.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9179296 1.23% 96.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6220016 0.83% 97.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3818014 0.51% 98.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14302886 1.92% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 697066716 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 464477894 # Number of instructions committed -system.cpu0.commit.committedOps 545285068 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 745378077 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 491403423 # Number of instructions committed +system.cpu0.commit.committedOps 578142958 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 165983876 # Number of memory references committed -system.cpu0.commit.loads 86857868 # Number of loads committed -system.cpu0.commit.membars 3594521 # Number of memory barriers committed -system.cpu0.commit.branches 103961213 # Number of branches committed -system.cpu0.commit.fp_insts 434735 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 500421802 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13758946 # Number of function calls committed. +system.cpu0.commit.refs 176221889 # Number of memory references committed +system.cpu0.commit.loads 91521232 # Number of loads committed +system.cpu0.commit.membars 3904419 # Number of memory barriers committed +system.cpu0.commit.branches 110044339 # Number of branches committed +system.cpu0.commit.fp_insts 493876 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 530522943 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14584303 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 378032624 69.33% 69.33% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1169798 0.21% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 60419 0.01% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 38309 0.01% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 86857868 15.93% 85.49% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 79126008 14.51% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 400598379 69.29% 69.29% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1193753 0.21% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 57671 0.01% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 71224 0.01% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 91521232 15.83% 85.35% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 84700657 14.65% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 545285068 # Class of committed instruction -system.cpu0.commit.bw_lim_events 13335148 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1272468420 # The number of ROB reads -system.cpu0.rob.rob_writes 1194722923 # The number of ROB writes -system.cpu0.timesIdled 998377 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 22469901 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93882577668 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 464477894 # Number of Instructions Simulated -system.cpu0.committedOps 545285068 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.568546 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.568546 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.637533 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.637533 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 684802624 # number of integer regfile reads -system.cpu0.int_regfile_writes 407591789 # number of integer regfile writes -system.cpu0.fp_regfile_reads 737398 # number of floating regfile reads -system.cpu0.fp_regfile_writes 323628 # number of floating regfile writes -system.cpu0.cc_regfile_reads 126081114 # number of cc regfile reads -system.cpu0.cc_regfile_writes 126833812 # number of cc regfile writes -system.cpu0.misc_regfile_reads 2842254449 # number of misc regfile reads -system.cpu0.misc_regfile_writes 14406777 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 5807270 # number of replacements -system.cpu0.dcache.tags.tagsinuse 503.185727 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 154700200 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5807781 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.636714 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1931738500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.185727 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.982785 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.982785 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 578142958 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14302886 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1353470869 # The number of ROB reads +system.cpu0.rob.rob_writes 1262695982 # The number of ROB writes +system.cpu0.timesIdled 1015060 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 22995381 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93993341722 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 491403423 # Number of Instructions Simulated +system.cpu0.committedOps 578142958 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.582388 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.582388 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.631956 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.631956 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 725839901 # number of integer regfile reads +system.cpu0.int_regfile_writes 430463320 # number of integer regfile writes +system.cpu0.fp_regfile_reads 805500 # number of floating regfile reads +system.cpu0.fp_regfile_writes 450680 # number of floating regfile writes +system.cpu0.cc_regfile_reads 133543353 # number of cc regfile reads +system.cpu0.cc_regfile_writes 134332816 # number of cc regfile writes +system.cpu0.misc_regfile_reads 3015329804 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16059632 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6141043 # number of replacements +system.cpu0.dcache.tags.tagsinuse 503.422627 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 163818652 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6141554 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.673811 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1929842500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.422627 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983247 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.983247 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 344453115 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 344453115 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 80805507 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80805507 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69071717 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69071717 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209524 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 209524 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 255543 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 255543 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1772811 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1772811 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1798532 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1798532 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149877224 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 149877224 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 150086748 # number of overall hits -system.cpu0.dcache.overall_hits::total 150086748 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6456855 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6456855 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6956516 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 6956516 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 664764 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 664764 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 829133 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 829133 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 256042 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 256042 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194087 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 194087 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 13413371 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 13413371 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 14078135 # number of overall misses -system.cpu0.dcache.overall_misses::total 14078135 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 92345367100 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 92345367100 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 122121346040 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 122121346040 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 37689944158 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 37689944158 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3513328512 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3513328512 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4123602814 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4123602814 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5259500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5259500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 214466713140 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 214466713140 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 214466713140 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 214466713140 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87262362 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 87262362 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 76028233 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 76028233 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 874288 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 874288 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1084676 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1084676 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2028853 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2028853 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1992619 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1992619 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 163290595 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 163290595 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164164883 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 164164883 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073994 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.073994 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.091499 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.091499 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760349 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760349 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.764406 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.764406 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.126200 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.126200 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097403 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097403 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082144 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.082144 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085756 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.085756 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14301.911240 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14301.911240 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17554.957976 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17554.957976 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 45457.054728 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 45457.054728 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13721.688286 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13721.688286 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21246.156693 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21246.156693 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 365108655 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 365108655 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 84789793 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 84789793 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73815215 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73815215 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 223529 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 223529 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 254722 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 254722 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1935633 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1935633 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1977053 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1977053 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 158605008 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 158605008 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 158828537 # number of overall hits +system.cpu0.dcache.overall_hits::total 158828537 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6791004 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6791004 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7631461 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7631461 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 739012 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 739012 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 806083 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 806083 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 273207 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 273207 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195599 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 195599 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 14422465 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 14422465 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 15161477 # number of overall misses +system.cpu0.dcache.overall_misses::total 15161477 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 101570086088 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 101570086088 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 139050346077 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 139050346077 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 37625975422 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 37625975422 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3995007021 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3995007021 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4127543324 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4127543324 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2928500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2928500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 240620432165 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 240620432165 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 240620432165 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 240620432165 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 91580797 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 91580797 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81446676 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81446676 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 962541 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 962541 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1060805 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1060805 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2208840 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2208840 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2172652 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2172652 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 173027473 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 173027473 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 173990014 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 173990014 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074153 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.074153 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.093699 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.093699 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.767772 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.767772 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.759879 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.759879 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.123688 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.123688 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.090028 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.090028 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.083354 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.083354 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087140 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.087140 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14956.564020 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14956.564020 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18220.671779 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18220.671779 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 46677.544896 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 46677.544896 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14622.637857 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14622.637857 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21102.067618 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21102.067618 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15989.024171 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15989.024171 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15234.028736 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15234.028736 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 10974284 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 17020056 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 751732 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 670987 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.598665 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 25.365702 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16683.724465 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16683.724465 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15870.513946 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15870.513946 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10994171 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 20243365 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 733732 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 746062 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.983906 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 27.133623 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3967066 # number of writebacks -system.cpu0.dcache.writebacks::total 3967066 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3312893 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3312893 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5560546 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 5560546 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4546 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4546 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 132684 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 132684 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 8873439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 8873439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 8873439 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 8873439 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3143962 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3143962 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1395970 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1395970 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 657971 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 657971 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 824587 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 824587 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123358 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123358 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194072 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 194072 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4539932 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4539932 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5197903 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5197903 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41375173894 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41375173894 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26017592924 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26017592924 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14556234769 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14556234769 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 36285250520 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 36285250520 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1556312588 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1556312588 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3823478686 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3823478686 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5096000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5096000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 67392766818 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 67392766818 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81949001587 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 81949001587 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5745168998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5745168998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5504162016 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5504162016 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11249331014 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11249331014 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036029 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036029 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018361 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018361 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.752579 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752579 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.760215 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.760215 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060802 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060802 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097395 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097395 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027803 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027803 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031663 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031663 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13160.201648 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13160.201648 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18637.644737 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18637.644737 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22122.912361 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22122.912361 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 44004.150587 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 44004.150587 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12616.227468 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12616.227468 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19701.341183 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19701.341183 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 4196368 # number of writebacks +system.cpu0.dcache.writebacks::total 4196368 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3475469 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3475469 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6119501 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6119501 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4173 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4173 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 141236 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 141236 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9594970 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9594970 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9594970 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9594970 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3315535 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3315535 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1511960 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1511960 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 732291 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 732291 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 801910 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 801910 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 131971 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 131971 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195594 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 195594 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4827495 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4827495 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5559786 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5559786 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31767 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31767 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31179 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31179 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62946 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62946 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45402822425 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45402822425 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28839272084 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28839272084 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16627256811 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16627256811 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 36253693272 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 36253693272 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1734403771 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1734403771 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3825076676 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3825076676 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2835500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2835500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 74242094509 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 74242094509 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 90869351320 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 90869351320 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5616435750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5616435750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5304462017 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5304462017 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10920897767 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10920897767 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036203 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036203 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018564 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018564 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.760789 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.760789 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.755945 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.755945 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059747 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059747 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.090025 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.090025 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027900 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027900 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031955 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031955 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13693.965657 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13693.965657 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19074.097254 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19074.097254 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22705.805221 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22705.805221 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 45209.179674 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 45209.179674 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13142.309833 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13142.309833 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19556.206612 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19556.206612 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14844.444106 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14844.444106 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15765.781237 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15765.781237 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15379.010130 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15379.010130 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16344.037580 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16344.037580 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176800.949098 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176800.949098 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170129.318355 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170129.318355 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 173496.294713 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173496.294713 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6071622 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.960367 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 207290998 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6072134 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.138080 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 14063099250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960367 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 6182706 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.960451 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 218406038 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6183218 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.322390 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14060425250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960451 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999923 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999923 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 329 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 92 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 433467798 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 433467798 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 207290998 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 207290998 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 207290998 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 207290998 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 207290998 # number of overall hits -system.cpu0.icache.overall_hits::total 207290998 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6406823 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6406823 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6406823 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6406823 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6406823 # number of overall misses -system.cpu0.icache.overall_misses::total 6406823 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 67980327142 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 67980327142 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 67980327142 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 67980327142 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 67980327142 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 67980327142 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 213697821 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 213697821 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 213697821 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 213697821 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 213697821 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 213697821 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029981 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029981 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029981 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029981 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029981 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029981 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10610.614206 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10610.614206 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10610.614206 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10610.614206 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10610.614206 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10610.614206 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 9344678 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 782 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 720412 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.971297 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 78.200000 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 456025787 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 456025787 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 218406038 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 218406038 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 218406038 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 218406038 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 218406038 # number of overall hits +system.cpu0.icache.overall_hits::total 218406038 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6515233 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6515233 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6515233 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6515233 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6515233 # number of overall misses +system.cpu0.icache.overall_misses::total 6515233 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 69121769887 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 69121769887 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 69121769887 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 69121769887 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 69121769887 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 69121769887 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 224921271 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 224921271 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 224921271 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 224921271 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 224921271 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 224921271 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028967 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.028967 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028967 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.028967 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028967 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.028967 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10609.255246 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10609.255246 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10609.255246 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10609.255246 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10609.255246 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10609.255246 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 9343070 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 429 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 716553 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.038910 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 47.666667 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 334667 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 334667 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 334667 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 334667 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 334667 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 334667 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6072156 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6072156 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6072156 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6072156 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6072156 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6072156 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 58462486516 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 58462486516 # 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number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 59487086557 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 59487086557 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 59487086557 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 59487086557 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1881164498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1881164498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028415 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1442 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5343 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4502 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3254 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079102 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.896057 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 290229122 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 290229122 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 541748 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 180817 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5534153 # 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number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 48655967065 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 108665528662 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5486110502 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7197622502 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5256416460 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5256416460 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5362208750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7073720750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5065245463 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5065245463 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10742526962 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12454038962 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.253956 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.154529 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000003 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000003 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10427454213 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12138966213 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022271 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046941 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.104972 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.257835 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.157336 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.722802 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.722802 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.550623 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.550623 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.824919 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.824919 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.740176 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.740176 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.531164 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.531164 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.813558 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813558 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.220782 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.220782 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.246358 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.161046 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.246358 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.218696 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.218696 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022271 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046941 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.104972 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248713 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.163628 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022271 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046941 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.104972 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248713 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.219706 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27494.820566 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26462.092491 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49836.623813 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49836.623813 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48324.735965 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 48324.735965 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20003.630551 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20003.630551 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14795.152488 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14795.152488 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 225131.473684 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 225131.473684 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40411.076926 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40411.076926 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30146.046820 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28342.966722 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30146.046820 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49836.623813 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34081.682009 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227508 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 29450.316582 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27776.376553 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61570.737006 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61570.737006 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48815.140097 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 48815.140097 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20109.679205 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20109.679205 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14820.003343 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14820.003343 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 473999.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 473999.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41416.056756 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41416.056756 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31902.456753 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 29645.931619 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31902.456753 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61570.737006 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38609.808035 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80375.316991 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168798.084490 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133312.993536 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162456.957022 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162456.957022 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80375.316991 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165657.138071 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 144099.788853 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 13109671 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10998966 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 32265 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32265 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3967064 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 987402 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1170476 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 822992 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 487373 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 355558 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 509064 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 118 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1297704 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1174184 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12186882 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16978089 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390292 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1142423 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 30697686 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 388957536 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 639747662 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404248 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4100656 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1034210102 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4435865 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 21321710 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.191876 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.393776 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 13667246 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11407678 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31179 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 4196361 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1120333 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1176973 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 800387 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 496358 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 355576 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 523512 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1407436 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1277584 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12409061 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17898439 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414925 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1222034 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 31944459 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 396067296 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 675577736 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1519008 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4432728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1077596768 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4739028 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 22459193 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.235945 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.424588 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 17230589 80.81% 80.81% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 4091121 19.19% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 17160060 76.41% 76.41% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 5299133 23.59% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 21321710 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 13464993223 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 22459193 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14039414488 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 208995484 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 204401970 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9149850308 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9316604024 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8376078494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8912883405 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 215375806 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 225880552 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 630757127 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 669143268 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 124182653 # Number of BP lookups -system.cpu1.branchPred.condPredicted 82299269 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6251064 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 87493813 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 57426824 # Number of BTB hits +system.cpu1.branchPred.lookups 128543512 # Number of BP lookups +system.cpu1.branchPred.condPredicted 85865577 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6421624 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 90850028 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 59627534 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 65.635297 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17076023 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 176220 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.632929 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17292026 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 181846 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1637,81 +1658,83 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 534049 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 534049 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11595 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85531 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 242787 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 291262 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2048.229773 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 11850.953616 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 289126 99.27% 99.27% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1672 0.57% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 329 0.11% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 62 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 62 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 291262 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 270383 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 17183.802917 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 14328.415565 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16454.576356 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 267229 98.83% 98.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2235 0.83% 99.66% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 352 0.13% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 368 0.14% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 149 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 270383 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 438879688048 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.596096 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.540539 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 437883178548 99.77% 99.77% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 543837500 0.12% 99.90% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 218551000 0.05% 99.95% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 91365500 0.02% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 75836500 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 38561500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 12555000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 15271000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 530000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 438879688048 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 85532 88.06% 88.06% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11595 11.94% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 97127 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 534049 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 599268 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 599268 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13824 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 99235 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 280644 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 318624 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 1973.247464 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 12034.928654 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 316338 99.28% 99.28% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1742 0.55% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 377 0.12% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 71 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 83 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 318624 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 319817 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 17305.058052 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 14691.969456 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15678.724582 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 316762 99.04% 99.04% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2191 0.69% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 345 0.11% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 267 0.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 157 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 61 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 16 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 319817 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 467242764496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.609754 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.540089 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 466086530996 99.75% 99.75% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 677505500 0.15% 99.90% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 222526000 0.05% 99.95% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 100711000 0.02% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 81855500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 40422000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 15395000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 17231500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 579500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 7500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 467242764496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 99236 87.77% 87.77% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 13824 12.23% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 113060 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 599268 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 534049 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97127 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 599268 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 113060 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97127 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 631176 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 113060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 712328 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91849877 # DTB read hits -system.cpu1.dtb.read_misses 382442 # DTB read misses -system.cpu1.dtb.write_hits 75119650 # DTB write hits -system.cpu1.dtb.write_misses 151607 # DTB write misses +system.cpu1.dtb.read_hits 95146273 # DTB read hits +system.cpu1.dtb.read_misses 436726 # DTB read misses +system.cpu1.dtb.write_hits 76756681 # DTB write hits +system.cpu1.dtb.write_misses 162542 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 39274 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 401 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 5573 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 41064 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 604 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6738 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 36948 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 92232319 # DTB read accesses -system.cpu1.dtb.write_accesses 75271257 # DTB write accesses +system.cpu1.dtb.perms_faults 39860 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 95582999 # DTB read accesses +system.cpu1.dtb.write_accesses 76919223 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 166969527 # DTB hits -system.cpu1.dtb.misses 534049 # DTB misses -system.cpu1.dtb.accesses 167503576 # DTB accesses +system.cpu1.dtb.hits 171902954 # DTB hits +system.cpu1.dtb.misses 599268 # DTB misses +system.cpu1.dtb.accesses 172502222 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1741,1114 +1764,1128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 85651 # Table walker walks requested -system.cpu1.itb.walker.walksLong 85651 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 898 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61483 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9913 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 75738 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1212.145818 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8774.873802 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 75006 99.03% 99.03% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 365 0.48% 99.52% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 180 0.24% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 161 0.21% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 83675 # Table walker walks requested +system.cpu1.itb.walker.walksLong 83675 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 922 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60249 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9641 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 74034 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1137.571926 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8570.962609 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 73376 99.11% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 334 0.45% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 142 0.19% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 157 0.21% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 75738 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 72294 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 21947.554182 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 18825.235250 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19960.579515 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 70492 97.51% 97.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1482 2.05% 99.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 157 0.22% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 99 0.14% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 72294 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 404519897680 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.847972 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.359205 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 61519279012 15.21% 15.21% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 342981503668 84.79% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 17484500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1520000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 101500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 9000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 404519897680 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61483 98.56% 98.56% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 898 1.44% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 62381 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::total 74034 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 70812 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21947.603838 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 18689.139556 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 20589.258424 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 68933 97.35% 97.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1547 2.18% 99.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 153 0.22% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 111 0.16% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 27 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 70812 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 419972060240 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.852209 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.355033 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 62087724216 14.78% 14.78% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 357865938524 85.21% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 17105000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1290000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 2500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 419972060240 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 60249 98.49% 98.49% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 922 1.51% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 61171 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85651 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85651 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 83675 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 83675 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62381 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62381 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 148032 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 196330607 # ITB inst hits -system.cpu1.itb.inst_misses 85651 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61171 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61171 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 144846 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 203060553 # ITB inst hits +system.cpu1.itb.inst_misses 83675 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 28544 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 29792 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 219679 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 217868 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 196416258 # ITB inst accesses -system.cpu1.itb.hits 196330607 # DTB hits -system.cpu1.itb.misses 85651 # DTB misses -system.cpu1.itb.accesses 196416258 # DTB accesses -system.cpu1.numCycles 659201565 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 203144228 # ITB inst accesses +system.cpu1.itb.hits 203060553 # DTB hits +system.cpu1.itb.misses 83675 # DTB misses +system.cpu1.itb.accesses 203144228 # DTB accesses +system.cpu1.numCycles 689224896 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 81623724 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 551229784 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 124182653 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 74502847 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 545141022 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13475474 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1814701 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 236397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6195125 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 729177 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 658891 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 196089515 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1603144 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 28612 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 643136774 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.007577 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.226676 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 83111859 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 570743281 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 128543512 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 76919560 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 571668142 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13828506 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1777982 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 253475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6260799 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 781198 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 699050 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 202821648 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1630400 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 27635 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 671466758 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.996773 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.223843 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 333162826 51.80% 51.80% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 120232758 18.69% 70.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 41446819 6.44% 76.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 148294371 23.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 351036099 52.28% 52.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 124470987 18.54% 70.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 43050208 6.41% 77.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 152909464 22.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 643136774 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.188383 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.836208 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 97937463 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 300403958 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 205522733 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 34511986 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4760634 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17730932 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2017504 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 571814983 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21511068 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4760634 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 130465176 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 39849524 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 206232237 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 207101717 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 54727486 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 556322152 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5380569 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 8461915 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 304416 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 605845 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 22227660 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 11247 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 528347539 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 856455710 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 657084844 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 755426 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 475426080 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 52921453 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14732861 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 12829203 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 69624573 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 92331469 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 78236769 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8977003 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7612209 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 535459998 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 14979383 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 539826932 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2475624 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 50076597 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 32301398 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 273094 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 643136774 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.839366 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.069808 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 671466758 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.186504 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.828094 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 100354838 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 318587695 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 211284340 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 36331371 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4908514 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 18177231 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2045887 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 591006296 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22089664 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4908514 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 134210773 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 44178364 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 216212349 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 213325919 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 58630839 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 574898328 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5600894 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8989963 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 383271 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 860464 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 24265786 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 10988 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 548407946 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 889065279 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 679031773 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 678204 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 493384651 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 55023295 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15514043 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13585261 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 73076002 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 95606432 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 79961275 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8917606 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7761424 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 553073173 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15730545 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 557717167 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2597694 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 51818937 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 33853803 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 272876 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 671466758 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.830595 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.066249 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 347132433 53.97% 53.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 125915806 19.58% 73.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 103467009 16.09% 89.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 59513725 9.25% 98.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7103072 1.10% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4729 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 364901654 54.34% 54.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 131371089 19.56% 73.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 106572496 15.87% 89.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 61289322 9.13% 98.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7327865 1.09% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 4332 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 643136774 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 671466758 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 53820631 43.79% 43.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 63940 0.05% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 7561 0.01% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 33515144 27.27% 71.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 35487446 28.88% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 55930906 44.08% 44.08% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 67479 0.05% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 9405 0.01% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 14 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 34760931 27.40% 71.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 36114343 28.46% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 367420702 68.06% 68.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1281309 0.24% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 73255 0.01% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 4 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 2 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 83298 0.02% 68.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 94677124 17.54% 85.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 76291227 14.13% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 41 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 380161908 68.16% 68.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1344725 0.24% 68.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 78828 0.01% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 3 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 5 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 45642 0.01% 68.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 98115732 17.59% 86.02% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 77970283 13.98% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 539826932 # Type of FU issued -system.cpu1.iq.rate 0.818910 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 122894739 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.227656 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1846883379 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 600138356 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 524462260 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1277620 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 518844 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 476158 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 661932910 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 788750 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2478321 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 557717167 # Type of FU issued +system.cpu1.iq.rate 0.809195 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 126883078 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227504 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1915274546 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 620324151 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 541832642 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1107318 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 438573 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 407875 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 683910466 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 689738 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2496582 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11570290 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16551 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 142141 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5437069 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11949439 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 17528 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 140940 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5567236 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2465198 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3688063 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2504839 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3936319 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4760634 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6603988 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1453249 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 550562460 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4908514 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7583348 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1594599 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 568926208 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 92331469 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 78236769 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12610859 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 52882 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1339609 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 142141 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1900150 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2649580 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4549730 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 532747017 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 91844367 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6553150 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 95606432 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 79961275 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13359998 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 58436 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1466228 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 140940 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1941130 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2763310 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4704440 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 550354066 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 95142052 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6771828 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 123079 # number of nop insts executed -system.cpu1.iew.exec_refs 166962398 # number of memory reference insts executed -system.cpu1.iew.exec_branches 99765376 # Number of branches executed -system.cpu1.iew.exec_stores 75118031 # Number of stores executed -system.cpu1.iew.exec_rate 0.808170 # Inst execution rate -system.cpu1.iew.wb_sent 525632708 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 524938418 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 254712512 # num instructions producing a value -system.cpu1.iew.wb_consumers 416314102 # num instructions consuming a value +system.cpu1.iew.exec_nop 122490 # number of nop insts executed +system.cpu1.iew.exec_refs 171896040 # number of memory reference insts executed +system.cpu1.iew.exec_branches 103292614 # Number of branches executed +system.cpu1.iew.exec_stores 76753988 # Number of stores executed +system.cpu1.iew.exec_rate 0.798512 # Inst execution rate +system.cpu1.iew.wb_sent 542951378 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 542240517 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 263529127 # num instructions producing a value +system.cpu1.iew.wb_consumers 431811268 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.796325 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.611828 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.786740 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610288 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 43862550 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14706289 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4273961 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 634802902 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.788218 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.581621 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 45371481 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15457669 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4415885 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 662874998 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.779913 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.574524 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 414870625 65.35% 65.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 114759147 18.08% 83.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 48245889 7.60% 91.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 16373665 2.58% 93.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11678245 1.84% 95.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 7925650 1.25% 96.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5354812 0.84% 97.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3238197 0.51% 98.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12356672 1.95% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 435019222 65.63% 65.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 119535237 18.03% 83.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 49733246 7.50% 91.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 16752738 2.53% 93.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 12005106 1.81% 95.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8186664 1.24% 96.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5495672 0.83% 97.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3379842 0.51% 98.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12767271 1.93% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 634802902 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 424719097 # Number of instructions committed -system.cpu1.commit.committedOps 500362777 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 662874998 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 439804157 # Number of instructions committed +system.cpu1.commit.committedOps 516984781 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 153560878 # Number of memory references committed -system.cpu1.commit.loads 80761178 # Number of loads committed -system.cpu1.commit.membars 3652883 # Number of memory barriers committed -system.cpu1.commit.branches 94624372 # Number of branches committed -system.cpu1.commit.fp_insts 463166 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 459868567 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12685398 # Number of function calls committed. +system.cpu1.commit.refs 158051032 # Number of memory references committed +system.cpu1.commit.loads 83656993 # Number of loads committed +system.cpu1.commit.membars 3709079 # Number of memory barriers committed +system.cpu1.commit.branches 98009532 # Number of branches committed +system.cpu1.commit.fp_insts 399401 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 474457036 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12875376 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 345616008 69.07% 69.07% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1054252 0.21% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 58059 0.01% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 73580 0.01% 69.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 80761178 16.14% 85.45% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 72799700 14.55% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 357731742 69.20% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1099808 0.21% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 62550 0.01% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 39649 0.01% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 83656993 16.18% 85.61% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 74394039 14.39% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 500362777 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12356672 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1162834468 # The number of ROB reads -system.cpu1.rob.rob_writes 1096743807 # The number of ROB writes -system.cpu1.timesIdled 924876 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 16064791 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 93951930875 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 424719097 # Number of Instructions Simulated -system.cpu1.committedOps 500362777 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.552088 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.552088 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.644293 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.644293 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 629086185 # number of integer regfile reads -system.cpu1.int_regfile_writes 373708704 # number of integer regfile writes -system.cpu1.fp_regfile_reads 742781 # number of floating regfile reads -system.cpu1.fp_regfile_writes 462024 # number of floating regfile writes -system.cpu1.cc_regfile_reads 113147370 # number of cc regfile reads -system.cpu1.cc_regfile_writes 113825607 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2613251902 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14637394 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5151228 # number of replacements -system.cpu1.dcache.tags.tagsinuse 427.693854 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 143143391 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5151740 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.785445 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8478589557500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 427.693854 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.835340 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.835340 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 516984781 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12767271 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1208536006 # The number of ROB reads +system.cpu1.rob.rob_writes 1133266670 # The number of ROB writes +system.cpu1.timesIdled 962801 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 17758138 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94081707774 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 439804157 # Number of Instructions Simulated +system.cpu1.committedOps 516984781 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.567118 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.567118 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.638114 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.638114 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 649922276 # number of integer regfile reads +system.cpu1.int_regfile_writes 385926927 # number of integer regfile writes +system.cpu1.fp_regfile_reads 666608 # number of floating regfile reads +system.cpu1.fp_regfile_writes 325148 # number of floating regfile writes +system.cpu1.cc_regfile_reads 119080359 # number of cc regfile reads +system.cpu1.cc_regfile_writes 119756232 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2706897787 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15455536 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5466279 # number of replacements +system.cpu1.dcache.tags.tagsinuse 430.006906 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 146874051 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5466791 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 26.866593 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8478589492000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.006906 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.839857 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.839857 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 318663535 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 318663535 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 75155961 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 75155961 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 63737585 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 63737585 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 169811 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 169811 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 58007 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 58007 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1657429 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1657429 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1683439 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1683439 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 138893546 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 138893546 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 139063357 # number of overall hits -system.cpu1.dcache.overall_hits::total 139063357 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6025315 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6025315 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6706823 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6706823 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 630176 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 630176 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 421123 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 421123 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 264252 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 264252 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195781 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 195781 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 12732138 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 12732138 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 13362314 # number of overall misses -system.cpu1.dcache.overall_misses::total 13362314 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 87326420147 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 87326420147 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 117804291686 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 117804291686 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13004978477 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 13004978477 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3882326694 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3882326694 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4150746008 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4150746008 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4758000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4758000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 205130711833 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 205130711833 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 205130711833 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 205130711833 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 81181276 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 81181276 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 70444408 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 70444408 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 799987 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 799987 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 479130 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 479130 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1921681 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1921681 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1879220 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1879220 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 151625684 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 151625684 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 152425671 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 152425671 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074221 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.074221 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.095207 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.095207 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787733 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787733 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.878933 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.878933 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104182 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104182 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083971 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.083971 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087664 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.087664 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14493.253904 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14493.253904 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17564.842801 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17564.842801 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 30881.662785 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 30881.662785 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14691.758980 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14691.758980 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21200.964384 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21200.964384 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 328243838 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 328243838 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 77663514 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 77663514 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 64795157 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 64795157 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170774 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 170774 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 62879 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 62879 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1733317 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1733317 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1753267 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1753267 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 142458671 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 142458671 # 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number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195367 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 195367 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13582484 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13582484 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 14254443 # number of overall misses +system.cpu1.dcache.overall_misses::total 14254443 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96129677540 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 96129677540 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 127902484654 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 127902484654 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 14399209171 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 14399209171 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3810993278 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3810993278 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4142660469 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4142660469 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3781500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3781500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 224032162194 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 224032162194 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 224032162194 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 224032162194 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 84104357 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 84104357 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 71936798 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 71936798 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 842733 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 842733 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 511872 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 511872 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1993100 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1993100 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1948634 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1948634 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 156041155 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 156041155 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 156883888 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 156883888 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.076582 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.076582 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.099277 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.099277 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.797357 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.797357 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.877159 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.877159 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130341 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130341 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100258 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100258 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.087044 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.087044 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090860 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.090860 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14925.014868 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14925.014868 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17909.397106 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17909.397106 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 32070.008154 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 32070.008154 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14669.910187 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14669.910187 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21204.504696 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21204.504696 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16111.254200 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16111.254200 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15351.436273 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15351.436273 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 3328310 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18296285 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 353421 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 675053 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.417409 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 27.103479 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16494.196658 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16494.196658 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15716.654954 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15716.654954 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 3725007 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 19991584 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 377661 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 721598 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.863362 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 27.704600 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3264704 # number of writebacks -system.cpu1.dcache.writebacks::total 3264704 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3035971 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3035971 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5416489 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5416489 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3258 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3258 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 136728 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 136728 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8452460 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8452460 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8452460 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8452460 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2989344 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2989344 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1290334 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1290334 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630111 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 630111 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 417865 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 417865 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127524 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127524 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195781 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 195781 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4279678 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4279678 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4909789 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4909789 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39357294362 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39357294362 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22683763866 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22683763866 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12612160940 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12612160940 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12265252837 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12265252837 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1674709739 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1674709739 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3848237992 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3848237992 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4609500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4609500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62041058228 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 62041058228 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 74653219168 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 74653219168 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 688989750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 688989750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 785556502 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 785556502 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1474546252 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1474546252 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036823 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036823 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018317 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018317 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787652 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787652 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.872133 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.872133 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066361 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066361 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104182 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104182 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028225 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028225 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032211 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032211 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13165.863267 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13165.863267 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17579.761415 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17579.761415 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20015.776490 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20015.776490 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 29352.189911 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29352.189911 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13132.506344 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13132.506344 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19655.829687 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19655.829687 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3504875 # number of writebacks +system.cpu1.dcache.writebacks::total 3504875 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3270021 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3270021 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5779466 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5779466 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3415 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3415 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 132178 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 132178 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 9049487 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 9049487 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 9049487 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 9049487 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3170822 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3170822 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1362175 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1362175 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 671771 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 671771 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 445578 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 445578 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127605 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127605 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195366 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 195366 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4532997 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4532997 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5204768 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5204768 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7126 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7126 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7600 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7600 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14726 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14726 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42364690330 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42364690330 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24508372089 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24508372089 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14203530799 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14203530799 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 13616215076 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 13616215076 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1679833771 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1679833771 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3840214031 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3840214031 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3660000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3660000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 66873062419 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 66873062419 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 81076593218 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 81076593218 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 831425000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 831425000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 995372500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 995372500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1826797500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1826797500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037701 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037701 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018936 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018936 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.797134 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.797134 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.870487 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.870487 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064023 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064023 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100258 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100258 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029050 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029050 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033176 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033176 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13360.791091 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13360.791091 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17992.087719 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17992.087719 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21143.411667 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21143.411667 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30558.544354 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 30558.544354 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13164.325622 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13164.325622 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19656.511527 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19656.511527 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14496.664989 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14496.664989 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15204.975034 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15204.975034 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14752.505333 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14752.505333 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15577.369293 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15577.369293 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116674.852652 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 116674.852652 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 130970.065789 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 130970.065789 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124052.526144 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124052.526144 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5667991 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.848972 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 190104103 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5668503 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 33.536915 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8518313865250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.848972 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980174 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.980174 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5740789 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.866118 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 196754052 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5741301 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 34.269942 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8518317120500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.866118 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980207 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980207 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 334 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 397835903 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 397835903 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 190104103 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 190104103 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 190104103 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 190104103 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 190104103 # number of overall hits -system.cpu1.icache.overall_hits::total 190104103 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5979587 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5979587 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5979587 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5979587 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5979587 # number of overall misses -system.cpu1.icache.overall_misses::total 5979587 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61433525378 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 61433525378 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 61433525378 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 61433525378 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 61433525378 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 61433525378 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 196083690 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 196083690 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 196083690 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 196083690 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 196083690 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 196083690 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030495 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030495 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030495 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030495 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030495 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030495 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10273.874329 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10273.874329 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10273.874329 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10273.874329 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10273.874329 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10273.874329 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 8139519 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 675212 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.054761 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 411371773 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 411371773 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 196754052 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 196754052 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 196754052 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 196754052 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 196754052 # number of overall hits +system.cpu1.icache.overall_hits::total 196754052 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 6061167 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 6061167 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 6061167 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 6061167 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 6061167 # number of overall misses +system.cpu1.icache.overall_misses::total 6061167 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 63767181305 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 63767181305 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 63767181305 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 63767181305 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 63767181305 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 63767181305 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 202815219 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 202815219 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 202815219 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 202815219 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 202815219 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 202815219 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029885 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029885 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029885 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029885 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029885 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029885 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10520.611180 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10520.611180 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10520.611180 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10520.611180 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10520.611180 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10520.611180 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 8678948 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 76 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 693947 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.506644 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 38 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 311064 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 311064 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 311064 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 311064 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 311064 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 311064 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5668523 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5668523 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5668523 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5668523 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5668523 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5668523 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 52921398555 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 52921398555 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 52921398555 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 52921398555 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 52921398555 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 52921398555 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6131248 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6131248 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6131248 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6131248 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028909 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.028909 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.028909 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9336.011966 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9336.011966 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9336.011966 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 319831 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 319831 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 319831 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 319831 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 319831 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 319831 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5741336 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5741336 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5741336 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5741336 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5741336 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5741336 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 54923658725 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 54923658725 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 54923658725 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 54923658725 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 54923658725 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 54923658725 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6151998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6151998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6151998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6151998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028308 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028308 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028308 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.028308 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028308 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.028308 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9566.355065 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9566.355065 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9566.355065 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91820.865672 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91820.865672 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91820.865672 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91820.865672 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6924956 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7115948 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 165163 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7332494 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7535643 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 175627 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 889052 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2136964 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13504.433199 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 11477625 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2153158 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.330600 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9723406338993 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5663.402040 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.532496 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 97.953204 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3050.006780 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3697.963934 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 913.574746 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.345667 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004976 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005979 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.186158 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225706 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055760 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.824245 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1347 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14805 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 237 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 720 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 360 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1369 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5255 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5224 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2823 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.082214 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903625 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 249290678 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 249290678 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 527309 # 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average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14730.557686 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14730.557686 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 257666.400000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 257666.400000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34385.119811 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34385.119811 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25897.791789 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.847871 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33559.952085 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.226495 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22884.448482 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27637.652435 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25922.507717 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60161.370764 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 60161.370764 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 34318.724829 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34318.724829 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19975.708850 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19975.708850 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14840.199000 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14840.199000 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 234769.153846 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 234769.153846 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37282.960584 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37282.960584 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22884.448482 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29431.704298 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27300.861376 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22884.448482 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29431.704298 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60161.370764 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36501.357184 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83970.149254 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108672.046029 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 108441.957459 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123469.078947 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 123469.078947 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83970.149254 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116308.705691 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 116162.238897 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 12589327 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10390309 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6277 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6277 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3264703 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 969369 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1138126 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 416714 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 449544 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355754 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 472453 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 124 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1246255 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1097731 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11337166 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14775069 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 416528 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1186159 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27714922 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 362785648 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 551966772 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1534872 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4319536 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 920606828 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4866324 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 20006897 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.227379 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.419140 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 13189135 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10749038 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7600 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3504874 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1040151 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 17 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1162830 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 444302 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 468816 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 354419 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 478843 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1323230 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1164313 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11482776 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15667685 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 405853 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1309392 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 28865706 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 367444720 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 587773064 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1487376 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4788296 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 961493456 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5242184 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 21082310 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.277260 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.447646 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 15457744 77.26% 77.26% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 4549153 22.74% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 15237020 72.27% 72.27% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 5845290 27.73% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 20006897 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11420254845 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 21082310 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 12037419620 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 196151972 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 200301486 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8513145317 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8624197196 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7729223292 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8185098674 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 225599484 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 220844820 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 647309419 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 711986885 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40298 # Transaction distribution -system.iobus.trans_dist::ReadResp 40298 # Transaction distribution -system.iobus.trans_dist::WriteReq 136633 # Transaction distribution -system.iobus.trans_dist::WriteResp 29905 # Transaction distribution +system.iobus.trans_dist::ReadReq 40346 # Transaction distribution +system.iobus.trans_dist::ReadResp 40346 # Transaction distribution +system.iobus.trans_dist::WriteReq 136632 # Transaction distribution +system.iobus.trans_dist::WriteResp 29904 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47726 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47732 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2863,13 +2900,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122608 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231174 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231174 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122614 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353862 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47746 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47752 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2884,13 +2921,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338712 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36251000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496894 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36253000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2918,71 +2955,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 607686128 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607574888 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92706000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148478785 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148591827 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115568 # number of replacements -system.iocache.tags.tagsinuse 11.294495 # Cycle average of tags in use +system.iocache.tags.replacements 115612 # number of replacements +system.iocache.tags.tagsinuse 11.304105 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115584 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9116942023000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.849176 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.445319 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240573 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465332 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705906 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9116941730000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.838498 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.465607 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239906 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466600 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706507 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040640 # Number of tag accesses -system.iocache.tags.data_accesses 1040640 # Number of data accesses +system.iocache.tags.tag_accesses 1041036 # Number of tag accesses +system.iocache.tags.data_accesses 1041036 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8859 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8896 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8859 # number of demand (read+write) misses -system.iocache.demand_misses::total 8899 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8903 # number of demand (read+write) misses +system.iocache.demand_misses::total 8943 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8859 # number of overall misses -system.iocache.overall_misses::total 8899 # number of overall misses +system.iocache.overall_misses::realview.ide 8903 # number of overall misses +system.iocache.overall_misses::total 8943 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1636729691 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1641925191 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1642618319 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1647813819 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19864825652 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19864825652 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19871992742 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19871992742 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1636729691 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1642294191 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1642618319 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1648182819 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1636729691 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1642294191 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1642618319 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1648182819 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8859 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8896 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8859 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8899 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8903 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8943 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8859 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8899 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8903 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8943 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2997,54 +3034,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184753.323287 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 184568.928844 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184501.664495 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 184319.219128 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186125.718200 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 186125.718200 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186192.871055 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186192.871055 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 184753.323287 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 184548.172941 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 184501.664495 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 184298.649111 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 184753.323287 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 184548.172941 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 112586 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 184501.664495 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 184298.649111 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 111619 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16234 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.935198 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.909682 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8859 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8903 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8940 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8859 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8899 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8903 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8943 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8859 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8899 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8903 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8943 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1174861151 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1178131651 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1178449871 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1181720371 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14314859762 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14314859762 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14322034844 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14322034844 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1174861151 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1178344651 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1178449871 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1181933371 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1174861151 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1178344651 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1178449871 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1181933371 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3059,632 +3096,639 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132617.806863 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 132433.863647 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132365.480288 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 132183.486689 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134124.688573 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134124.688573 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134191.916311 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134191.916311 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 132617.806863 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 132413.153276 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 132365.480288 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 132162.962205 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 132617.806863 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 132413.153276 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 132365.480288 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 132162.962205 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1377424 # number of replacements -system.l2c.tags.tagsinuse 64428.474571 # Cycle average of tags in use -system.l2c.tags.total_refs 4496154 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1437791 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.127126 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 3245891000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17415.702003 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.555673 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 13.071281 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4037.254225 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5874.753333 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3721.003209 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 357.239386 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 523.990627 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2776.282665 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11847.144423 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17848.477746 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.265743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000199 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061604 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.089642 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.056778 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005451 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.007995 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042363 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.180773 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.272346 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983101 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10320 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 289 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49758 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 260 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9845 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 285 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2371 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4137 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 42888 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.157471 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004410 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.759247 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 59850638 # Number of tag accesses -system.l2c.tags.data_accesses 59850638 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6609 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5089 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 570808 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 585040 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 302541 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6014 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4366 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 555272 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 535796 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 269863 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2841398 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2358990 # number of Writeback hits -system.l2c.Writeback_hits::total 2358990 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 147857 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 120344 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 268201 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 33100 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 25345 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 58445 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6120 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5439 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11559 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 54193 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 49865 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 104058 # 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average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83688.360665 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 81639.295954 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 104987.673799 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83688.360665 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 81639.295954 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 104987.673799 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9229572290 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4289000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1431871000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11951355290 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.279221 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.336277 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.100365 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.202363 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.497355 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.290407 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.378745 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.075700 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.188378 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.488956 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.247661 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762804 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.515411 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.684542 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.584949 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.642273 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.611806 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.599268 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.607950 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.603655 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.602942 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.537618 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.574321 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.279221 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.336277 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100365 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.261913 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.497355 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.290407 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.378745 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075700 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.234919 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.488956 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.266822 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.279221 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.336277 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100365 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.261913 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.497355 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.290407 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.378745 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075700 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.234919 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.488956 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.266822 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 87169.627673 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 86751.636095 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 113670.819035 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39633.758490 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32967.837039 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38046.017555 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17843.229524 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.065753 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17831.836625 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17802.173178 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17806.479891 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17804.365073 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80406.356563 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80557.040745 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80468.156601 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84855.079113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84862.417955 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 109478.788986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84855.079113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84862.417955 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 109478.788986 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60374.894336 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 149269.737495 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64014.925373 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 89069.623807 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 110640.240175 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143934.075467 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 104913.026316 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 136286.638103 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60374.894336 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 146626.827598 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64014.925373 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 97247.419180 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 120682.970888 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 855568 # Transaction distribution -system.membus.trans_dist::ReadResp 855568 # Transaction distribution -system.membus.trans_dist::WriteReq 38542 # Transaction distribution -system.membus.trans_dist::WriteResp 38542 # Transaction distribution -system.membus.trans_dist::Writeback 1173701 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 661649 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 661649 # Transaction distribution -system.membus.trans_dist::UpgradeReq 438223 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 309934 # Transaction distribution -system.membus.trans_dist::UpgradeResp 117397 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution -system.membus.trans_dist::ReadExReq 139893 # Transaction distribution -system.membus.trans_dist::ReadExResp 122444 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122608 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1049844 # Transaction distribution +system.membus.trans_dist::ReadResp 1049844 # Transaction distribution +system.membus.trans_dist::WriteReq 38779 # Transaction distribution +system.membus.trans_dist::WriteResp 38779 # Transaction distribution +system.membus.trans_dist::Writeback 1370148 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 687460 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 687460 # Transaction distribution +system.membus.trans_dist::UpgradeReq 443336 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 306800 # Transaction distribution +system.membus.trans_dist::UpgradeResp 120479 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.membus.trans_dist::ReadExReq 155568 # Transaction distribution +system.membus.trans_dist::ReadExResp 137698 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122614 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4925384 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5074464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5410374 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155738 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5597252 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5747450 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335773 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335773 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6083223 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155744 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52788 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 162304200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 162513298 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14098112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14098112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 176611410 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 651055 # Total snoops (count) -system.membus.snoop_fanout::samples 3600660 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 189917440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 190128768 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14086528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14086528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 204215296 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 650589 # Total snoops (count) +system.membus.snoop_fanout::samples 4133180 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3600660 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4133180 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3600660 # Request fanout histogram -system.membus.reqLayer0.occupancy 98274497 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4133180 # Request fanout histogram +system.membus.reqLayer0.occupancy 98178497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22081484 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22861986 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 10699049257 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 12090027529 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5725496770 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6852398799 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151866715 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 152088673 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3728,49 +3772,49 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 4566673 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4559437 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38542 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38542 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2358990 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 933261 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 826411 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 489333 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 321493 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 810826 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 208 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 288168 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 288168 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7677415 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6169065 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 13846480 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255017262 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 196496484 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 451513746 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1675443 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8934179 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012956 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.113084 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4896771 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4889534 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38779 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2596817 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 959438 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 852557 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 496684 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 319053 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 815737 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 143 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 305200 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 305200 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8223954 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6618870 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 14842824 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 276507544 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 214143912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 490651456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1673717 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9649223 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012003 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.108901 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 8818430 98.70% 98.70% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115749 1.30% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9533399 98.80% 98.80% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115824 1.20% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8934179 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 7984163233 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9649223 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8593373447 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2491500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2556000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4301185209 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4622045284 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3898685571 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4138277748 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13668 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 13964 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5222 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5482 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |