diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
| commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
| tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual | |
| parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
| download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual')
5 files changed, 3864 insertions, 3490 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini index 11768aa62..5e79cd0cc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -121,6 +134,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -159,6 +173,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -198,8 +216,15 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 numThreads=1 +useIndirect=true [system.cpu0.dcache] type=Cache @@ -208,13 +233,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -233,8 +262,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -257,9 +291,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -273,9 +312,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[3] @@ -551,13 +595,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -576,8 +624,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -635,9 +688,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -651,9 +709,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[2] @@ -664,13 +727,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu0.l2cache.prefetcher response_latency=12 @@ -688,6 +755,7 @@ mem_side=system.toL2Bus.slave[0] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -698,6 +766,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -714,8 +786,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -723,9 +800,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 @@ -770,6 +853,7 @@ cpu_id=1 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -808,6 +892,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -847,8 +935,15 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 numThreads=1 +useIndirect=true [system.cpu1.dcache] type=Cache @@ -857,13 +952,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -882,8 +981,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -906,9 +1010,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -922,9 +1031,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[3] @@ -1200,13 +1314,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -1225,8 +1343,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -1284,9 +1407,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -1300,9 +1428,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[2] @@ -1313,13 +1446,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu1.l2cache.prefetcher response_latency=12 @@ -1337,6 +1474,7 @@ mem_side=system.toL2Bus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -1347,6 +1485,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -1363,8 +1505,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -1372,9 +1519,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 @@ -1419,9 +1572,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -1435,13 +1593,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -1460,8 +1622,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -1472,13 +1639,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -1497,20 +1668,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -1522,11 +1704,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1537,6 +1724,13 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl IDD0=0.075000 @@ -1571,6 +1765,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1582,7 +1777,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1625,10 +1824,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1709,14 +1913,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1725,13 +1934,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1741,6 +1955,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1811,10 +2026,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1894,17 +2114,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1930,12 +2155,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1943,14 +2174,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -2036,14 +2272,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -2052,13 +2293,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -2067,13 +2313,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -2081,11 +2332,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2099,11 +2355,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2117,19 +2378,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -2175,14 +2442,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -2191,11 +2473,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -2205,21 +2492,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -2229,12 +2526,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -2243,10 +2545,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -2256,12 +2563,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -2271,26 +2583,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -2299,10 +2621,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -2310,10 +2637,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -2321,21 +2653,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2349,11 +2691,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -2364,11 +2711,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -2376,10 +2728,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -2395,9 +2752,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr index 4c70e8d66..ab526e302 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr @@ -3,6 +3,8 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist @@ -11,3 +13,4 @@ warn: allocating bonus target for snoop warn: allocating bonus target for snoop warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: allocating bonus target for snoop diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout index cc1e1c387..83022ad25 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 13:59:02 -gem5 executing on e104799-lin, pid 13304 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:49:48 +gem5 executing on e108600-lin, pid 23303 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47393980707000 because m5_exit instruction encountered +Exiting @ tick 47384351300000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index bdfed319a..374e48ec0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.384315 # Number of seconds simulated -sim_ticks 47384315163000 # Number of ticks simulated -final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.384351 # Number of seconds simulated +sim_ticks 47384351300000 # Number of ticks simulated +final_tick 47384351300000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151085 # Simulator instruction rate (inst/s) -host_op_rate 177673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7925620115 # Simulator tick rate (ticks/s) -host_mem_usage 773240 # Number of bytes of host memory used -host_seconds 5978.63 # Real time elapsed on the host -sim_insts 903281747 # Number of instructions simulated -sim_ops 1062243320 # Number of ops (including micro ops) simulated +host_inst_rate 172914 # Simulator instruction rate (inst/s) +host_op_rate 195786 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6718052359 # Simulator tick rate (ticks/s) +host_mem_usage 777068 # Number of bytes of host memory used +host_seconds 7053.29 # Real time elapsed on the host +sim_insts 1219610005 # Number of instructions simulated +sim_ops 1380933056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 12825352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 13896960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 201536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 189312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2647264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 11439440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 16431296 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory -system.physmem.bytes_read::total 62456088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4233376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2647264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6880640 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79489088 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 205248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 202880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4270112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 16788488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 21729728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 123968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 83584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3109600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 10061712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12393536 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 438400 # Number of bytes read from this memory +system.physmem.bytes_read::total 69407256 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4270112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3109600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7379712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 85545984 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 79509672 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1380 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 911 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 82099 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 200409 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 217140 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3149 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2958 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 41407 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 178754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 256739 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory -system.physmem.num_reads::total 991898 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1242017 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 85566568 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3207 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3170 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 82673 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 262333 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 339527 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1937 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1306 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 48631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 157227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 193649 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6850 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1100510 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1336656 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1244591 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 89341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 270667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 293282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 55868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 241418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 346767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1318075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 89341 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 55868 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 145209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1677540 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1339230 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 90117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 354304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 458584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 65625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 212343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 261553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1464772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 90117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 65625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155742 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1805364 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1677974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1677540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 89341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 271101 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 293282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 55868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 241418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 346767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2996050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 991898 # Number of read requests accepted -system.physmem.writeReqs 1244591 # Number of write requests accepted -system.physmem.readBursts 991898 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1244591 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 63457600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue -system.physmem.bytesWritten 79508544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62456088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 79509672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1805798 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1805364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 90117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 354739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 458584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 65625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 212343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 261553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3270570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1100510 # Number of read requests accepted +system.physmem.writeReqs 1339230 # Number of write requests accepted +system.physmem.readBursts 1100510 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1339230 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 70408640 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue +system.physmem.bytesWritten 85564992 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 69407256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 85566568 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 57534 # Per bank write bursts -system.physmem.perBankRdBursts::1 67322 # Per bank write bursts -system.physmem.perBankRdBursts::2 57239 # Per bank write bursts -system.physmem.perBankRdBursts::3 59640 # Per bank write bursts -system.physmem.perBankRdBursts::4 58543 # Per bank write bursts -system.physmem.perBankRdBursts::5 68655 # Per bank write bursts -system.physmem.perBankRdBursts::6 57471 # Per bank write bursts -system.physmem.perBankRdBursts::7 60839 # Per bank write bursts -system.physmem.perBankRdBursts::8 60208 # Per bank write bursts -system.physmem.perBankRdBursts::9 81942 # Per bank write bursts -system.physmem.perBankRdBursts::10 59318 # Per bank write bursts -system.physmem.perBankRdBursts::11 61436 # Per bank write bursts -system.physmem.perBankRdBursts::12 60309 # Per bank write bursts -system.physmem.perBankRdBursts::13 62906 # Per bank write bursts -system.physmem.perBankRdBursts::14 58748 # Per bank write bursts -system.physmem.perBankRdBursts::15 59415 # Per bank write bursts -system.physmem.perBankWrBursts::0 74024 # Per bank write bursts -system.physmem.perBankWrBursts::1 81724 # Per bank write bursts -system.physmem.perBankWrBursts::2 74878 # Per bank write bursts -system.physmem.perBankWrBursts::3 76858 # Per bank write bursts -system.physmem.perBankWrBursts::4 76593 # Per bank write bursts -system.physmem.perBankWrBursts::5 82864 # Per bank write bursts -system.physmem.perBankWrBursts::6 74278 # Per bank write bursts -system.physmem.perBankWrBursts::7 78173 # Per bank write bursts -system.physmem.perBankWrBursts::8 76626 # Per bank write bursts -system.physmem.perBankWrBursts::9 80136 # Per bank write bursts -system.physmem.perBankWrBursts::10 77163 # Per bank write bursts -system.physmem.perBankWrBursts::11 80655 # Per bank write bursts -system.physmem.perBankWrBursts::12 76245 # Per bank write bursts -system.physmem.perBankWrBursts::13 79687 # Per bank write bursts -system.physmem.perBankWrBursts::14 75064 # Per bank write bursts -system.physmem.perBankWrBursts::15 77353 # Per bank write bursts +system.physmem.perBankRdBursts::0 70416 # Per bank write bursts +system.physmem.perBankRdBursts::1 75191 # Per bank write bursts +system.physmem.perBankRdBursts::2 64063 # Per bank write bursts +system.physmem.perBankRdBursts::3 69912 # Per bank write bursts +system.physmem.perBankRdBursts::4 59812 # Per bank write bursts +system.physmem.perBankRdBursts::5 69643 # Per bank write bursts +system.physmem.perBankRdBursts::6 65430 # Per bank write bursts +system.physmem.perBankRdBursts::7 68144 # Per bank write bursts +system.physmem.perBankRdBursts::8 61950 # Per bank write bursts +system.physmem.perBankRdBursts::9 89644 # Per bank write bursts +system.physmem.perBankRdBursts::10 68037 # Per bank write bursts +system.physmem.perBankRdBursts::11 70586 # Per bank write bursts +system.physmem.perBankRdBursts::12 61163 # Per bank write bursts +system.physmem.perBankRdBursts::13 71056 # Per bank write bursts +system.physmem.perBankRdBursts::14 65094 # Per bank write bursts +system.physmem.perBankRdBursts::15 69994 # Per bank write bursts +system.physmem.perBankWrBursts::0 85481 # Per bank write bursts +system.physmem.perBankWrBursts::1 90029 # Per bank write bursts +system.physmem.perBankWrBursts::2 81966 # Per bank write bursts +system.physmem.perBankWrBursts::3 85433 # Per bank write bursts +system.physmem.perBankWrBursts::4 77921 # Per bank write bursts +system.physmem.perBankWrBursts::5 84076 # Per bank write bursts +system.physmem.perBankWrBursts::6 83054 # Per bank write bursts +system.physmem.perBankWrBursts::7 85039 # Per bank write bursts +system.physmem.perBankWrBursts::8 78873 # Per bank write bursts +system.physmem.perBankWrBursts::9 84297 # Per bank write bursts +system.physmem.perBankWrBursts::10 83224 # Per bank write bursts +system.physmem.perBankWrBursts::11 86586 # Per bank write bursts +system.physmem.perBankWrBursts::12 79852 # Per bank write bursts +system.physmem.perBankWrBursts::13 85124 # Per bank write bursts +system.physmem.perBankWrBursts::14 80745 # Per bank write bursts +system.physmem.perBankWrBursts::15 85253 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 51477 # Number of times write queue was full causing retry -system.physmem.totGap 47384313590500 # Total gap between requests +system.physmem.numWrRetry 51215 # Number of times write queue was full causing retry +system.physmem.totGap 47384349786500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 970540 # Read request sizes (log2) +system.physmem.readPktSize::6 1079152 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1242017 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 445378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 243433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 76996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 56880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 37150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 31949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 29173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 27068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 25124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 6848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3836 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 708 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1336656 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 480448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 272774 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 88894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 67384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 42690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 36411 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7595 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 684 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 590 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -189,137 +189,136 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 36083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 41131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 48159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 53054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 57269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 63720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 68707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 72599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 69938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 72538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 82492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 73770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 67397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 2021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 6136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 120872 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 982131 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 145.566960 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.657532 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 193.069606 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 654413 66.63% 66.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 194527 19.81% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50477 5.14% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21176 2.16% 93.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16419 1.67% 95.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9395 0.96% 96.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6596 0.67% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5289 0.54% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23839 2.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 982131 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 56922 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.418608 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 74.895923 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 56917 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 24574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 38198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 43791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 48248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 52275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 57744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 67593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 69901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 75312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 79272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 77429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 90816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 80863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 73646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 69003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 6200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 120342 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1069816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 145.794462 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.799028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 192.755385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 712470 66.60% 66.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 211048 19.73% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 55044 5.15% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23596 2.21% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18557 1.73% 95.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10547 0.99% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7452 0.70% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5550 0.52% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25552 2.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1069816 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62458 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.613853 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 71.325725 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 62454 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 56922 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 56922 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.824971 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.750218 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 638.100533 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-4095 56920 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 62458 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62458 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.405633 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.660061 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 609.107080 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-4095 62456 100.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::45056-49151 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 56922 # Writes before turning the bus around for reads -system.physmem.totQLat 43578574020 # Total ticks spent queuing -system.physmem.totMemAccLat 62169667770 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4957625000 # Total ticks spent in databus transfers -system.physmem.avgQLat 43951.06 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 62458 # Writes before turning the bus around for reads +system.physmem.totQLat 48895390505 # Total ticks spent queuing +system.physmem.totMemAccLat 69522921755 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5500675000 # Total ticks spent in databus transfers +system.physmem.avgQLat 44444.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 62701.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.34 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 63194.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.75 # Average write queue length when enqueuing -system.physmem.readRowHits 750886 # Number of row buffer hits during reads -system.physmem.writeRowHits 500828 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.31 # Row buffer hit rate for writes -system.physmem.avgGap 21186920.03 # Average gap between requests -system.physmem.pageHitRate 56.03 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3717395640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2028340875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3800456400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4013660160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1158326321940 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27414513105000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31681312358415 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.603367 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45606511009457 # Time in different power states -system.physmem_0.memoryStateTime::REF 1582266400000 # Time in different power states +system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.21 # Average write queue length when enqueuing +system.physmem.readRowHits 830166 # Number of row buffer hits during reads +system.physmem.writeRowHits 537104 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.17 # Row buffer hit rate for writes +system.physmem.avgGap 19421885.03 # Average gap between requests +system.physmem.pageHitRate 56.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4087639080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2230358625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4232326800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4361033520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3094915112640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1166279241240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27407555547000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31683661258905 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.652499 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45594888254330 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582267440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 195537314293 # Time in different power states +system.physmem_0.memoryStateTime::ACT 207195159170 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3707514720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2022949500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3933399600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4036579920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1156667621085 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27415968105750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31681249248975 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.602035 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45608919765384 # Time in different power states -system.physmem_1.memoryStateTime::REF 1582266400000 # Time in different power states +system.physmem_1.actEnergy 4000169880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2182632375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4348679400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4302421920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3094915112640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1168435080135 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27405664460250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31683848556600 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.656452 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45591701065782 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582267440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 193128558366 # Time in different power states +system.physmem_1.memoryStateTime::ACT 210382633218 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -346,30 +345,30 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 138091637 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91311717 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6789940 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 97223509 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 59866310 # Number of BTB hits +system.cpu0.branchPred.lookups 199183431 # Number of BP lookups +system.cpu0.branchPred.condPredicted 140489040 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7036065 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 156342542 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 99990575 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 61.575961 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 18644167 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 188685 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4389066 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2747803 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1641263 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 409141 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 63.956089 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20013017 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 198399 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4618183 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2919648 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1698535 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 412858 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,90 +398,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 530338 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 530338 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10426 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79784 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 241995 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 288343 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2099.123266 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 12230.418976 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 286535 99.37% 99.37% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1269 0.44% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 337 0.12% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.05% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 37 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 607513 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 607513 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13877 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 97395 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 289192 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 318321 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2219.643065 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 12711.673990 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 315923 99.25% 99.25% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1786 0.56% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 409 0.13% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 127 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 41 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 31 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 288343 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 261783 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 19021.382214 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 16878.246550 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 10891.763559 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 246122 94.02% 94.02% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 14409 5.50% 99.52% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 656 0.25% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 427 0.16% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 44 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 47 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 25 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 22 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 261783 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 513336492752 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.609866 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.537961 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 512309669252 99.80% 99.80% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 522001000 0.10% 99.90% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 221126000 0.04% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 109873500 0.02% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 86703000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 51185000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 14405500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 21121500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 397500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 10500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 513336492752 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 79785 88.44% 88.44% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10426 11.56% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 90211 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 530338 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 318321 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 324666 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 20482.457356 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17703.017560 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16938.599592 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 320665 98.77% 98.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2783 0.86% 99.62% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 369 0.11% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 625 0.19% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 139 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 57 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 324666 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 513372677252 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.571567 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.552695 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 512028975252 99.74% 99.74% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 726675000 0.14% 99.88% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 290458500 0.06% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 129299000 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 102361000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 55725500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 16517000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 21785000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 858500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 22500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 513372677252 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 97395 87.53% 87.53% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 13877 12.47% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 111272 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 607513 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 530338 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90211 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 607513 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111272 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90211 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 620549 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111272 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 718785 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 99690232 # DTB read hits -system.cpu0.dtb.read_misses 367422 # DTB read misses -system.cpu0.dtb.write_hits 83046551 # DTB write hits -system.cpu0.dtb.write_misses 162916 # DTB write misses +system.cpu0.dtb.read_hits 141538315 # DTB read hits +system.cpu0.dtb.read_misses 437252 # DTB read misses +system.cpu0.dtb.write_hits 86796370 # DTB write hits +system.cpu0.dtb.write_misses 170261 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35477 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 482 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 6442 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 43183 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 271 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 6902 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 39704 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 100057654 # DTB read accesses -system.cpu0.dtb.write_accesses 83209467 # DTB write accesses +system.cpu0.dtb.perms_faults 42288 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 141975567 # DTB read accesses +system.cpu0.dtb.write_accesses 86966631 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 182736783 # DTB hits -system.cpu0.dtb.misses 530338 # DTB misses -system.cpu0.dtb.accesses 183267121 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 228334685 # DTB hits +system.cpu0.dtb.misses 607513 # DTB misses +system.cpu0.dtb.accesses 228942198 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -512,1195 +507,1194 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 81834 # Table walker walks requested -system.cpu0.itb.walker.walksLong 81834 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1030 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58824 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 9805 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 72029 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 864.033931 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 6165.525550 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 71606 99.41% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 296 0.41% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 49 0.07% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 70 0.10% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 72029 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 69659 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 23684.893553 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21955.996989 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 12765.700584 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 63811 91.60% 91.60% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 5242 7.53% 99.13% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 100 0.14% 99.27% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 402 0.58% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 69659 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 375894589280 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.860066 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.347066 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 52618427692 14.00% 14.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 323259257588 86.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 15893500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 943500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 54500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 12500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 375894589280 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 58824 98.28% 98.28% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1030 1.72% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 59854 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 87943 # Table walker walks requested +system.cpu0.itb.walker.walksLong 87943 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1130 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 62851 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10253 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 77690 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1458.353713 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 10159.922633 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 76707 98.73% 98.73% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 405 0.52% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 337 0.43% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 198 0.25% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 14 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 77690 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 74234 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26234.178409 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23080.051735 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 21732.027543 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 71871 96.82% 96.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1986 2.68% 99.49% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 153 0.21% 99.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 128 0.17% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 62 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 21 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 74234 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 410290287148 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.846605 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.360675 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 62979367364 15.35% 15.35% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 347270506784 84.64% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 38246000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1931000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 236000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 410290287148 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 62851 98.23% 98.23% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1130 1.77% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 63981 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81834 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81834 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 87943 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 87943 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59854 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59854 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 141688 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 216521473 # ITB inst hits -system.cpu0.itb.inst_misses 81834 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 63981 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 63981 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 151924 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 282848559 # ITB inst hits +system.cpu0.itb.inst_misses 87943 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25278 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 30949 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 198402 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 212727 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 216603307 # ITB inst accesses -system.cpu0.itb.hits 216521473 # DTB hits -system.cpu0.itb.misses 81834 # DTB misses -system.cpu0.itb.accesses 216603307 # DTB accesses -system.cpu0.numPwrStateTransitions 26480 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13240 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3550703383.143278 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 88629328460.442917 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3078 23.25% 23.25% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 10135 76.55% 99.80% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.83% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7390881192332 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13240 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 373002370183 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 47011312792817 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 746014900 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 282936502 # ITB inst accesses +system.cpu0.itb.hits 282848559 # DTB hits +system.cpu0.itb.misses 87943 # DTB misses +system.cpu0.itb.accesses 282936502 # DTB accesses +system.cpu0.numPwrStateTransitions 28168 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 14084 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3333377849.836978 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 92382687873.308472 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 4020 28.54% 28.54% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 10033 71.24% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 13 0.09% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 6914082605000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 14084 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 437057662896 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46947293637104 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 874125395 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 90433879 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 610172736 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 138091637 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81258280 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 615398287 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14620490 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1715297 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 295776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 5589619 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 711520 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 813110 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 216323861 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1696724 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 26704 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 722267733 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.989116 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.222569 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 92275983 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 768900237 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 199183431 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 122923240 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 738928784 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15190816 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2037144 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 294842 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6072240 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 792344 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 839757 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 282635522 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1737700 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 28623 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 848836502 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.034930 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.208968 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 380266002 52.65% 52.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 133082578 18.43% 71.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 45433566 6.29% 77.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 163485587 22.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 416377385 49.05% 49.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 176079063 20.74% 69.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 66732959 7.86% 77.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 189647095 22.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 722267733 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.185106 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.817910 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 106050198 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 344087060 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 231125881 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 35774912 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5229682 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19752919 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2120005 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 632519077 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23747295 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5229682 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 140879480 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 46445701 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 235545365 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 231642525 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 62524980 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 614970268 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6274841 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 9683853 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 239254 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 254272 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 29219197 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11058 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 585821211 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 944611426 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 725501320 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 860588 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 527918401 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 57902804 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 14873386 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 12932012 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 72326353 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 100125445 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 86327833 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 8833111 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 7713299 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 593239093 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 14925406 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 596650262 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2740149 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 54305512 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 35087941 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 259840 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 722267733 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.826079 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.071801 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 848836502 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.227866 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.879622 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 110330106 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 381856903 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 311429263 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 39757521 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5462709 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 29836532 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2173523 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 791623702 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 24444549 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5462709 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 147675961 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 53914284 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 258297798 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 313275075 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 70210675 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 773227105 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6509157 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 10689754 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 377832 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 811571 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 32991272 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11799 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 742885425 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1169549966 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 880889153 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 700737 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 682115784 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 60769635 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16576266 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14423738 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 79729853 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 141637487 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90242008 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9692958 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8374311 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 749539213 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16620515 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 754385019 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2849937 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 57154900 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 36998097 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 294454 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 848836502 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.888728 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.088535 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 398653423 55.19% 55.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 132668388 18.37% 73.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 116695962 16.16% 89.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 66414173 9.20% 98.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7831504 1.08% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 4283 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 442949824 52.18% 52.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 161566736 19.03% 71.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 148384909 17.48% 88.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 87697049 10.33% 99.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8232602 0.97% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5382 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 722267733 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 848836502 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 62572261 45.86% 45.86% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 47637 0.03% 45.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 27538 0.02% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 12 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 35025206 25.67% 71.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 38780691 28.42% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 74538342 48.88% 48.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 62447 0.04% 48.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 15099 0.01% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 9 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 37581602 24.64% 73.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 40298347 26.43% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 37 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 408003074 68.38% 68.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1391206 0.23% 68.62% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 75246 0.01% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 5 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 75513 0.01% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 102801955 17.23% 85.87% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 84303178 14.13% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 519755806 68.90% 68.90% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1543884 0.20% 69.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 77211 0.01% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 64 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 42719 0.01% 69.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 144854124 19.20% 88.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88111156 11.68% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 596650262 # Type of FU issued -system.cpu0.iq.rate 0.799783 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 136453345 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228699 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2053360508 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 662051351 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 579495604 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1401241 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 556367 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 521179 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 732235238 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 868332 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2674563 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 754385019 # Type of FU issued +system.cpu0.iq.rate 0.863017 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 152495846 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.202146 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2511823586 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 823027375 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 736101219 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1128735 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 443604 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 415332 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 906176667 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 704147 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2868207 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12322480 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 16225 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 138716 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5498195 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13104832 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17724 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 157642 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5794849 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2627025 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4349073 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2875718 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4918474 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5229682 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6015766 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1577054 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 608291813 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5462709 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7926079 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1884320 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 766295642 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 100125445 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 86327833 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 12661031 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 57348 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1462300 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 138716 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 1920652 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3139987 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5060639 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 588583301 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 99681195 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7546532 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 141637487 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90242008 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 14144816 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 61216 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1749510 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 157642 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2035907 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3235941 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5271848 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 745963336 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 141529970 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7821454 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 127314 # number of nop insts executed -system.cpu0.iew.exec_refs 182727665 # number of memory reference insts executed -system.cpu0.iew.exec_branches 110905985 # Number of branches executed -system.cpu0.iew.exec_stores 83046470 # Number of stores executed -system.cpu0.iew.exec_rate 0.788970 # Inst execution rate -system.cpu0.iew.wb_sent 580785082 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 580016783 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 281571835 # num instructions producing a value -system.cpu0.iew.wb_consumers 462036259 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.777487 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609415 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 47239068 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14665566 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4709377 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 713265593 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.776512 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.575400 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 135914 # number of nop insts executed +system.cpu0.iew.exec_refs 228324326 # number of memory reference insts executed +system.cpu0.iew.exec_branches 170531782 # Number of branches executed +system.cpu0.iew.exec_stores 86794356 # Number of stores executed +system.cpu0.iew.exec_rate 0.853383 # Inst execution rate +system.cpu0.iew.wb_sent 737330155 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 736516551 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 351214969 # num instructions producing a value +system.cpu0.iew.wb_consumers 595098705 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.842575 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.590179 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 49835507 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 16326061 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4903366 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 839368834 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.844688 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.533259 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 472345396 66.22% 66.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 122854697 17.22% 83.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 54352038 7.62% 91.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 18530727 2.60% 93.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13156863 1.84% 95.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8843989 1.24% 96.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5973723 0.84% 97.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3646989 0.51% 98.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 13561171 1.90% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 512658006 61.08% 61.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 158759517 18.91% 79.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 92536082 11.02% 91.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 27862473 3.32% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13576189 1.62% 95.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9358920 1.11% 97.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6289735 0.75% 97.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3875341 0.46% 98.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14452571 1.72% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 713265593 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 471410910 # Number of instructions committed -system.cpu0.commit.committedOps 553858980 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 839368834 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 622433451 # Number of instructions committed +system.cpu0.commit.committedOps 709004821 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 168632602 # Number of memory references committed -system.cpu0.commit.loads 87802964 # Number of loads committed -system.cpu0.commit.membars 3653468 # Number of memory barriers committed -system.cpu0.commit.branches 105429162 # Number of branches committed -system.cpu0.commit.fp_insts 512997 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 508174699 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13889214 # Number of function calls committed. +system.cpu0.commit.refs 212979813 # Number of memory references committed +system.cpu0.commit.loads 128532654 # Number of loads committed +system.cpu0.commit.membars 3921678 # Number of memory barriers committed +system.cpu0.commit.branches 164749224 # Number of branches committed +system.cpu0.commit.fp_insts 407380 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 634275437 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14942203 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 383941234 69.32% 69.32% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1156077 0.21% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 59954 0.01% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 69071 0.01% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 87802964 15.85% 85.41% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 80829638 14.59% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 494636379 69.76% 69.76% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1291078 0.18% 69.95% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 60530 0.01% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 37021 0.01% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 128532654 18.13% 88.09% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 84447159 11.91% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 553858980 # Class of committed instruction -system.cpu0.commit.bw_lim_events 13561171 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1296549352 # The number of ROB reads -system.cpu0.rob.rob_writes 1211163120 # The number of ROB writes -system.cpu0.timesIdled 982435 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 23747167 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 94022615466 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 471410910 # Number of Instructions Simulated -system.cpu0.committedOps 553858980 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.582515 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.582515 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.631905 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.631905 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 694459704 # number of integer regfile reads -system.cpu0.int_regfile_writes 413089219 # number of integer regfile writes -system.cpu0.fp_regfile_reads 846069 # number of floating regfile reads -system.cpu0.fp_regfile_writes 429660 # number of floating regfile writes -system.cpu0.cc_regfile_reads 127998327 # number of cc regfile reads -system.cpu0.cc_regfile_writes 128742208 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1288788249 # number of misc regfile reads -system.cpu0.misc_regfile_writes 14832406 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5793916 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.305765 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 157106373 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5794427 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.113358 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 709004821 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14452571 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1579278211 # The number of ROB reads +system.cpu0.rob.rob_writes 1527109253 # The number of ROB writes +system.cpu0.timesIdled 1033857 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25288893 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93894577230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 622433451 # Number of Instructions Simulated +system.cpu0.committedOps 709004821 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.404368 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.404368 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.712064 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.712064 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 848778973 # number of integer regfile reads +system.cpu0.int_regfile_writes 506977822 # number of integer regfile writes +system.cpu0.fp_regfile_reads 685984 # number of floating regfile reads +system.cpu0.fp_regfile_writes 317032 # number of floating regfile writes +system.cpu0.cc_regfile_reads 188384037 # number of cc regfile reads +system.cpu0.cc_regfile_writes 189031095 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1590236345 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16401028 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6409966 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.619482 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 199938758 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6410478 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 31.189368 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.305765 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986925 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986925 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 349540400 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 349540400 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 81616032 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 81616032 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 70522769 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 70522769 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213045 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 213045 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259663 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 259663 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1810689 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1810689 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1836259 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1836259 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 152398464 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 152398464 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 152611509 # number of overall hits -system.cpu0.dcache.overall_hits::total 152611509 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6448823 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6448823 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7191873 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7191873 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 676181 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 676181 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 810826 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 810826 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 247493 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 247493 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187335 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 187335 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 14451522 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 14451522 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15127703 # number of overall misses -system.cpu0.dcache.overall_misses::total 15127703 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 92981912000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 92981912000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 133998931168 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 133998931168 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29936196189 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 29936196189 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3415607500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3415607500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4687136000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4687136000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3788500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3788500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 256917039357 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 256917039357 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 256917039357 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 256917039357 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88064855 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 88064855 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77714642 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77714642 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 889226 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 889226 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1070489 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1070489 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2058182 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2058182 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2023594 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2023594 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 166849986 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 166849986 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 167739212 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 167739212 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073228 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.073228 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.092542 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.092542 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760415 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760415 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.757435 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.757435 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.120248 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.120248 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092575 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092575 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086614 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.086614 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.090186 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.090186 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14418.431394 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14418.431394 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18631.993525 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18631.993525 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36920.616987 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36920.616987 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13800.824670 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13800.824670 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25020.076334 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25020.076334 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.619482 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938710 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.938710 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 439216738 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 439216738 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 121629785 # 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number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 195968 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 16003734 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 16003734 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 16780103 # number of overall misses +system.cpu0.dcache.overall_misses::total 16780103 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 108528058000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 108528058000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 153779451872 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 153779451872 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 31763636892 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 31763636892 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4317295000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4317295000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4927286000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4927286000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3123500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3123500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 294071146764 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 294071146764 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 294071146764 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 294071146764 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 128770220 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 128770220 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81278747 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81278747 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1002323 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1002323 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1033701 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1033701 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2154950 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2154950 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2115422 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2115422 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 211082668 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 211082668 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 212084991 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 212084991 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.055451 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.055451 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.098731 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.098731 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.774570 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.774570 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.811251 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.811251 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.134325 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.134325 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092638 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092638 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.075817 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.075817 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.079120 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.079120 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15199.082129 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15199.082129 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19163.245799 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19163.245799 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37877.388252 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37877.388252 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14914.790786 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14914.790786 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25143.319317 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25143.319317 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17777.853389 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17777.853389 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16983.215453 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16983.215453 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9060649 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 19650869 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 747322 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 698056 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.124157 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 28.150849 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5793928 # number of writebacks -system.cpu0.dcache.writebacks::total 5793928 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3323367 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3323367 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5758852 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 5758852 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4670 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4670 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 128237 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 128237 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9086889 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9086889 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9086889 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9086889 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125456 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3125456 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1433021 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1433021 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 669278 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 669278 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 806156 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 806156 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 119256 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 119256 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187331 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 187331 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5364633 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5364633 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6033911 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6033911 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32527 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32351 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64878 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43142423000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43142423000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30169010620 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30169010620 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14964455000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14964455000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28947099689 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28947099689 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564593500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564593500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4499876000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4499876000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3717500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3717500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102258533309 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 102258533309 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 117222988309 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 117222988309 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6208668000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6208668000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6208668000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6208668000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035490 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018440 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018440 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.752652 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752652 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.753073 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.753073 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057942 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057942 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092573 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092573 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032152 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032152 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035972 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.035972 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13803.561144 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13803.561144 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21052.734482 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21052.734482 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22359.101898 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22359.101898 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35907.565892 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35907.565892 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13119.620816 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13119.620816 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24020.989585 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24020.989585 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18375.158370 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18375.158370 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17524.990566 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17524.990566 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9668545 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 23532840 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 779892 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 794197 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.397287 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 29.630986 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 6410042 # number of writebacks +system.cpu0.dcache.writebacks::total 6410042 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3690786 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3690786 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6446005 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6446005 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4347 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4347 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 149571 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 149571 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 10141138 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 10141138 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 10141138 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 10141138 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3449649 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3449649 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1578703 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1578703 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 769355 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 769355 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 834244 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 834244 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139893 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139893 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195965 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 195965 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5862596 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5862596 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6631951 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6631951 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31285 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31285 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30958 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 30958 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62243 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62243 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50416416500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50416416500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 33875543231 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33875543231 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17245260500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17245260500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 30759768392 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 30759768392 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1918237000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1918237000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4731380000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4731380000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3064500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3064500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 115051728123 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 115051728123 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 132296988623 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 132296988623 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6062914000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6062914000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6062914000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6062914000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.026789 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026789 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019423 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019423 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.767572 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767572 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.807046 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.807046 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064917 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064917 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092636 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092636 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027774 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027774 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031270 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031270 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14614.940969 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14614.940969 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21457.831670 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21457.831670 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22415.218592 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22415.218592 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36871.428973 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36871.428973 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13712.172875 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13712.172875 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24144.005307 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24144.005307 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19061.608373 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19061.608373 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19427.364492 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19427.364492 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190877.363421 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190877.363421 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95697.586239 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95697.586239 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 6136519 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.962391 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 209807209 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6137031 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.187086 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12886295000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962391 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19624.706891 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19624.706891 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19948.426733 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19948.426733 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193796.196260 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193796.196260 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97407.162251 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97407.162251 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 6234341 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.962382 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 276007197 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6234853 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 44.268437 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 12884658000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962382 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 438728804 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 438728804 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 209807209 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 209807209 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 209807209 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 209807209 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 209807209 # number of overall hits -system.cpu0.icache.overall_hits::total 209807209 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6488653 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6488653 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6488653 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6488653 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6488653 # number of overall misses -system.cpu0.icache.overall_misses::total 6488653 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 69596700450 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 69596700450 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 69596700450 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 69596700450 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 69596700450 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 69596700450 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 216295862 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 216295862 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 216295862 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 216295862 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 216295862 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 216295862 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029999 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029999 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029999 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029999 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029999 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029999 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10725.908821 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10725.908821 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10725.908821 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10725.908821 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10132412 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 737599 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.737020 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 48.444444 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 6136519 # number of writebacks -system.cpu0.icache.writebacks::total 6136519 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351573 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 351573 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 351573 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 351573 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 351573 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 351573 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6137080 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6137080 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6137080 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6137080 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6137080 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6137080 # number of overall MSHR misses +system.cpu0.icache.tags.tag_accesses 571449747 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 571449747 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 276007197 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 276007197 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 276007197 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 276007197 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 276007197 # number of overall hits +system.cpu0.icache.overall_hits::total 276007197 # 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number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1885677498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1885677498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028374 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028374 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028374 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10263.003193 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.022063 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.022063 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.022063 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10379.994443 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10379.994443 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10379.994443 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7743703 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7754051 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 9277 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8818791 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8829534 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 9675 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1008365 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2565485 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15956.741738 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 17408441 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2581334 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.743971 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1134314 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2939155 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16147.226336 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 18219506 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2955258 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.165115 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 2212473000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14849.648482 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 36.124813 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 23.448036 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000032 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1047.520376 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.906351 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002205 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001431 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 15244.220202 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.043386 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 62.165258 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000002 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 782.797489 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.930433 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003543 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003794 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063936 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.973922 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1203 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14569 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.047778 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.985548 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1151 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14871 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 211 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 564 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 414 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1288 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4722 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4695 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3741 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.073425 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.889221 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 408243228 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 408243228 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539952 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 183800 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 723752 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3863126 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3863126 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 8065215 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 8065215 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 386 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 386 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 895474 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 895474 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5563145 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5563145 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2937118 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2937118 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 202987 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 202987 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 539952 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 183800 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5563145 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3832592 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10119489 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 539952 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 183800 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5563145 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3832592 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1385 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6005 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4408 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2945 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.070251 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004944 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.907654 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 433411639 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 433411639 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # 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average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28953.724719 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28953.724719 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36518.816670 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36518.816670 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30644.561078 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46845.335420 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35447.837007 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230754 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38987.144877 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56590.929630 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20556.048168 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20556.048168 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16627.774157 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16627.774157 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 655374.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 655374.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 44819.023202 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 44819.023202 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28775.786737 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31374.295958 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31374.295958 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36606.229223 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36606.229223 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34126.392569 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32554.736432 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34126.392569 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40136.035953 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182858.994066 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142583.305463 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185781.620585 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143370.934611 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91677.525509 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89053.550498 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 24754475 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12719207 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1997962 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1997498 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 885324 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11040535 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 32352 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32351 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5471965 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8067317 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2568559 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 991385 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 475065 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 341372 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 522361 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 76 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1216718 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1192935 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6137080 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4901216 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 866556 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 803970 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18453192 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18807742 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 402695 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1170958 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 38834587 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 785846352 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 704525389 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1531416 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4405792 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1496308949 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6903738 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 20024554 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.116908 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.321383 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93378.821715 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90238.424152 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 26220064 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13479100 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2657 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2182451 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2181920 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 531 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 979416 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11666319 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 30958 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 30958 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 6060800 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8438347 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2860883 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1184490 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 488552 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348527 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 533031 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1347603 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1325056 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6235149 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5307790 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 891051 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 832317 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18746760 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20650560 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 436622 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1328978 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 41162920 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 798358288 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 780155262 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1670248 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5039864 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1585223662 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7567060 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 126041936 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 21529267 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.118569 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.323357 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 17683990 88.31% 88.31% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2340100 11.69% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 464 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 18977100 88.15% 88.15% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2551636 11.85% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 531 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 20024554 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 24612511939 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 21529267 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 26091722433 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 212521499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 187623310 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9233457820 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9380939070 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8324768239 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9216328089 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 211573883 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 228203766 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 620908635 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 699632706 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 127244460 # Number of BP lookups -system.cpu1.branchPred.condPredicted 83927531 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6411720 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 89791062 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 55539581 # Number of BTB hits +system.cpu1.branchPred.lookups 194671556 # Number of BP lookups +system.cpu1.branchPred.condPredicted 153305610 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6254288 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 157865267 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 88709282 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 61.854242 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17406269 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 177185 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4036084 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2495247 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1540837 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 386993 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 56.193033 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16475486 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 172497 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3896881 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2381021 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1515860 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 389837 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1730,85 +1724,93 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 579824 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 579824 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12232 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93540 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 278610 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 301214 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2385.289196 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 13264.000730 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 298702 99.17% 99.17% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1877 0.62% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 425 0.14% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 126 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 47 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 301214 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 311038 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20491.173104 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17661.433181 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 17134.136599 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 306887 98.67% 98.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3006 0.97% 99.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 404 0.13% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 531 0.17% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 109 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 60 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 29 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 311038 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 427436234332 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.596252 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.559035 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 426093627832 99.69% 99.69% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 733360500 0.17% 99.86% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 289523500 0.07% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 124054000 0.03% 99.95% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 101131500 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 55199000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 17877500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 20812500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 638500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 427436234332 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 93540 88.44% 88.44% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 12232 11.56% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 105772 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 579824 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 533309 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 533309 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10503 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 81680 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 248509 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 284800 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2470.932233 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 13518.648671 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-32767 279405 98.11% 98.11% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-65535 3083 1.08% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-98303 908 0.32% 99.51% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-131071 713 0.25% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-163839 284 0.10% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::163840-196607 163 0.06% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-229375 124 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::229376-262143 32 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-294911 13 0.00% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::294912-327679 40 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-360447 32 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 284800 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 268382 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19517.668845 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17136.373439 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13227.910444 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 250971 93.51% 93.51% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 15361 5.72% 99.24% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 757 0.28% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 835 0.31% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 87 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 116 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 116 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 51 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 29 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 31 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 7 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 15 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 268382 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 466126532996 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.617043 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.546089 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 464998520496 99.76% 99.76% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 569195000 0.12% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 249472000 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 122508000 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 91886000 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 55274500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 15901500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 23390500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 385000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 466126532996 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 81681 88.61% 88.61% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10503 11.39% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 92184 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 533309 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 579824 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105772 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 533309 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92184 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105772 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 685596 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92184 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 625493 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 94100008 # DTB read hits -system.cpu1.dtb.read_misses 416726 # DTB read misses -system.cpu1.dtb.write_hits 75732153 # DTB write hits -system.cpu1.dtb.write_misses 163098 # DTB write misses +system.cpu1.dtb.read_hits 161844710 # DTB read hits +system.cpu1.dtb.read_misses 366883 # DTB read misses +system.cpu1.dtb.write_hits 74184112 # DTB write hits +system.cpu1.dtb.write_misses 166426 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 40885 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 397 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6052 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 34599 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 386 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6272 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 38110 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 94516734 # DTB read accesses -system.cpu1.dtb.write_accesses 75895251 # DTB write accesses +system.cpu1.dtb.perms_faults 37354 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 162211593 # DTB read accesses +system.cpu1.dtb.write_accesses 74350538 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 169832161 # DTB hits -system.cpu1.dtb.misses 579824 # DTB misses -system.cpu1.dtb.accesses 170411985 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 236028822 # DTB hits +system.cpu1.dtb.misses 533309 # DTB misses +system.cpu1.dtb.accesses 236562131 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1838,1179 +1840,1178 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 86146 # Table walker walks requested -system.cpu1.itb.walker.walksLong 86146 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 983 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61109 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 10267 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 75879 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1365.727013 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 9905.301438 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 74992 98.83% 98.83% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 442 0.58% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 265 0.35% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 132 0.17% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 11 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 75879 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 72359 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25927.458920 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22905.536509 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 21012.178040 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 70191 97.00% 97.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1833 2.53% 99.54% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 132 0.18% 99.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 128 0.18% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 41 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 21 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 72359 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 388687033168 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.860499 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.346749 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 54258161808 13.96% 13.96% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 334394621860 86.03% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 32560000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1626500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 63000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 388687033168 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61109 98.42% 98.42% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 983 1.58% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 62092 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 80718 # Table walker walks requested +system.cpu1.itb.walker.walksLong 80718 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 768 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57037 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 10137 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 70581 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 996.309205 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 6981.449622 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 70036 99.23% 99.23% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 380 0.54% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 60 0.09% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 83 0.12% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 70581 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 67942 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24162.219246 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22142.693859 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 15015.121608 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 66991 98.60% 98.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 778 1.15% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 100 0.15% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 45 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 67942 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 397380257260 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.877039 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.328570 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 48883602860 12.30% 12.30% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 348476867900 87.69% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 18158500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1572000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 56000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 397380257260 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 57037 98.67% 98.67% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 768 1.33% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 57805 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 86146 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 86146 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 80718 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 80718 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62092 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62092 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 148238 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 200179962 # ITB inst hits -system.cpu1.itb.inst_misses 86146 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57805 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 57805 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 138523 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 264777096 # ITB inst hits +system.cpu1.itb.inst_misses 80718 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 29927 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 24684 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 205105 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 195163 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 200266108 # ITB inst accesses -system.cpu1.itb.hits 200179962 # DTB hits -system.cpu1.itb.misses 86146 # DTB misses -system.cpu1.itb.accesses 200266108 # DTB accesses -system.cpu1.numPwrStateTransitions 11252 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 5626 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 8361647359.894774 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 196584250353.907135 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 4008 71.24% 71.24% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1597 28.39% 99.63% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.73% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 10 0.18% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11813562713000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 5626 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 341687116232 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47042628046768 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 683375860 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 264857814 # ITB inst accesses +system.cpu1.itb.hits 264777096 # DTB hits +system.cpu1.itb.misses 80718 # DTB misses +system.cpu1.itb.accesses 264857814 # DTB accesses +system.cpu1.numPwrStateTransitions 9670 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 4835 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 9724953244.725336 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 147881742434.863098 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3183 65.83% 65.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1626 33.63% 99.46% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.04% 99.50% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.10% 99.61% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.04% 99.65% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.67% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.71% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.29% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 7390881470984 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 4835 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 364202361753 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47020148938247 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 728406370 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 83886783 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 563469851 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 127244460 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 75441097 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 564344995 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13807906 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2007349 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 258832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 5872913 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 777107 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 768148 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 199953853 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1622392 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 27919 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 664820080 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.994147 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.223667 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 83192103 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 724269312 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 194671556 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 107565789 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 610871186 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13439122 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1719504 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 273339 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 5608482 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 704978 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 774415 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 264561727 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1602178 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 26700 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 709863568 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.153991 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.257090 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 348468390 52.42% 52.42% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 123001690 18.50% 70.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 42123132 6.34% 77.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 151226868 22.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 331851103 46.75% 46.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 119648081 16.86% 63.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 75565351 10.65% 74.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 182799033 25.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 664820080 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.186200 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.824539 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 100313259 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 315334519 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 208757120 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 35486026 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4929156 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17976704 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2012194 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 582722672 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22029645 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4929156 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 133756265 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 43242401 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 214462360 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 210347945 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 58081953 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 566482483 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5736321 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9739688 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 342221 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 843279 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 24527700 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 11906 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 538415916 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 871757488 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 668460678 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 644937 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 483561743 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 54854172 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15093428 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13190698 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 71341154 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 94469141 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 78816060 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 9208116 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7878049 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 544809829 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15364466 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 549398452 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2550658 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 51789954 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 33366441 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 282362 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 664820080 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.826387 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.065764 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 709863568 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.267257 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.994320 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 98062054 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 297890044 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 275618841 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 33512378 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4780251 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17247911 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1977266 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 743961992 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21656856 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4780251 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 130238128 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 40363481 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 204147620 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 276602035 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 53732053 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 728176206 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5626727 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9082967 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 240191 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 268836 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 22296515 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 11543 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 630286495 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 1024905330 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 827525539 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 801877 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 577128327 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 53158158 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14384532 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 12638476 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 67737488 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 162372694 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 77181222 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8520193 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7294637 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 707349171 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 14663402 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 711466322 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2509310 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 50084332 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 32217686 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 252969 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 709863568 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.002258 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.141899 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 363096071 54.62% 54.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 129026402 19.41% 74.02% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 104942160 15.79% 89.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 60539163 9.11% 98.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7211179 1.08% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 5105 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 346424684 48.80% 48.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 123916139 17.46% 66.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 138092978 19.45% 85.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 94358537 13.29% 99.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7067534 1.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3696 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 664820080 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 709863568 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 54936992 44.00% 44.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 69872 0.06% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 6570 0.01% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 34367116 27.52% 71.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 35481157 28.42% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 53419887 27.72% 27.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 53191 0.03% 27.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 19037 0.01% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 15 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 103986379 53.96% 81.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 35231745 18.28% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 56 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 373883416 68.05% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1335155 0.24% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 74884 0.01% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 48854 0.01% 68.32% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 97153433 17.68% 86.00% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 76902643 14.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 25 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 469996066 66.06% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1210560 0.17% 66.23% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 70927 0.01% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 81598 0.01% 66.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 164776620 23.16% 89.41% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 75330478 10.59% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 549398452 # Type of FU issued -system.cpu1.iq.rate 0.803948 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 124861724 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.227270 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1889962970 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 611689245 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 533047508 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1066396 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 424008 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 393622 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 673596915 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 663205 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2524444 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 711466322 # Type of FU issued +system.cpu1.iq.rate 0.976744 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 192710254 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.270863 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 2326678945 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 771690256 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 695698465 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1336829 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 536159 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 497637 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 903350253 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 826298 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2394067 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 12144847 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16403 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 149896 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5262071 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11654320 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 15948 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 130447 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5130974 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2572719 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4009144 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2399995 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3738162 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4929156 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7182655 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1646879 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 560304926 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4780251 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5901245 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1355404 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 722138785 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 94469141 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 78816060 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12974148 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 56258 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1524659 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 149896 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1843431 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2924818 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4768249 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 541845400 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 94094962 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6980663 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 162372694 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 77181222 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12419825 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 58724 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1239916 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 130447 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1767111 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2862185 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4629296 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 704121990 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 161840669 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6820718 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 130631 # number of nop insts executed -system.cpu1.iew.exec_refs 169824676 # number of memory reference insts executed -system.cpu1.iew.exec_branches 101510793 # Number of branches executed -system.cpu1.iew.exec_stores 75729714 # Number of stores executed -system.cpu1.iew.exec_rate 0.792895 # Inst execution rate -system.cpu1.iew.wb_sent 534152020 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 533441130 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 258912640 # num instructions producing a value -system.cpu1.iew.wb_consumers 423656459 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.780597 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.611138 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 45293147 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15082103 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4436923 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 656213363 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.774724 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.573400 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 126212 # number of nop insts executed +system.cpu1.iew.exec_refs 236024480 # number of memory reference insts executed +system.cpu1.iew.exec_branches 169760384 # Number of branches executed +system.cpu1.iew.exec_stores 74183811 # Number of stores executed +system.cpu1.iew.exec_rate 0.966661 # Inst execution rate +system.cpu1.iew.wb_sent 696881354 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 696196102 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 357262878 # num instructions producing a value +system.cpu1.iew.wb_consumers 517340824 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.955780 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.690575 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 43732145 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14410433 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4314978 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 701540457 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.957790 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.589997 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 432598016 65.92% 65.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 117091486 17.84% 83.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 49126445 7.49% 91.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 16229930 2.47% 93.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11628277 1.77% 95.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8033144 1.22% 96.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5546832 0.85% 97.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3283510 0.50% 98.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12675723 1.93% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 413092247 58.88% 58.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 113176092 16.13% 75.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 83530992 11.91% 86.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 51841229 7.39% 94.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11508500 1.64% 95.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7726725 1.10% 97.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5343630 0.76% 97.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3131269 0.45% 98.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12189773 1.74% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 656213363 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 431870837 # Number of instructions committed -system.cpu1.commit.committedOps 508384340 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 701540457 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 597176554 # Number of instructions committed +system.cpu1.commit.committedOps 671928235 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 155878283 # Number of memory references committed -system.cpu1.commit.loads 82324294 # Number of loads committed -system.cpu1.commit.membars 3722309 # Number of memory barriers committed -system.cpu1.commit.branches 96290107 # Number of branches committed -system.cpu1.commit.fp_insts 384716 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 467163355 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12903273 # Number of function calls committed. +system.cpu1.commit.refs 222768619 # Number of memory references committed +system.cpu1.commit.loads 150718371 # Number of loads committed +system.cpu1.commit.membars 39196572 # Number of memory barriers committed +system.cpu1.commit.branches 164739467 # Number of branches committed +system.cpu1.commit.fp_insts 488627 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 631392614 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12167965 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 351312000 69.10% 69.10% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1092238 0.21% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 59391 0.01% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 42428 0.01% 69.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 82324294 16.19% 85.53% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 73553989 14.47% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 448043617 66.68% 66.68% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 985154 0.15% 66.83% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 56630 0.01% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 74173 0.01% 66.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 150718371 22.43% 89.28% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 72050248 10.72% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 508384340 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12675723 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1193390155 # The number of ROB reads -system.cpu1.rob.rob_writes 1115923607 # The number of ROB writes -system.cpu1.timesIdled 934929 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 18555780 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94085254498 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 431870837 # Number of Instructions Simulated -system.cpu1.committedOps 508384340 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.582362 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.582362 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.631967 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.631967 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 639570382 # number of integer regfile reads -system.cpu1.int_regfile_writes 380109427 # number of integer regfile writes -system.cpu1.fp_regfile_reads 631427 # number of floating regfile reads -system.cpu1.fp_regfile_writes 338972 # number of floating regfile writes -system.cpu1.cc_regfile_reads 115255782 # number of cc regfile reads -system.cpu1.cc_regfile_writes 115917819 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1185795918 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15045931 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5420466 # number of replacements -system.cpu1.dcache.tags.tagsinuse 437.277482 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 144971712 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5420977 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 26.742728 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8477404255000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 437.277482 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.854058 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.854058 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 671928235 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12189773 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1401264531 # The number of ROB reads +system.cpu1.rob.rob_writes 1439606443 # The number of ROB writes +system.cpu1.timesIdled 902579 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 18542802 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94040296263 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 597176554 # Number of Instructions Simulated +system.cpu1.committedOps 671928235 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.219750 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.219750 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.819840 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.819840 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 799341399 # number of integer regfile reads +system.cpu1.int_regfile_writes 475575163 # number of integer regfile writes +system.cpu1.fp_regfile_reads 787030 # number of floating regfile reads +system.cpu1.fp_regfile_writes 454812 # number of floating regfile writes +system.cpu1.cc_regfile_reads 112918659 # number of cc regfile reads +system.cpu1.cc_regfile_writes 113685571 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1427881847 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14489141 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5047432 # number of replacements +system.cpu1.dcache.tags.tagsinuse 457.905792 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 212666270 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5047943 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 42.129293 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8477400492000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.905792 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.894347 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.894347 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 323922794 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 323922794 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 76466425 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 76466425 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 64110613 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 64110613 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170428 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 170428 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 51164 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 51164 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1700918 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1700918 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1741756 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1741756 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 140628202 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 140628202 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 140798630 # number of overall hits -system.cpu1.dcache.overall_hits::total 140798630 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6372316 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6372316 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7014697 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7014697 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 658076 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 658076 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 445973 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 445973 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 278553 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 278553 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193453 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 193453 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13832986 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13832986 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14491062 # number of overall misses -system.cpu1.dcache.overall_misses::total 14491062 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 93736923500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 93736923500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 131113304741 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 131113304741 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11858807099 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 11858807099 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4107251000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 4107251000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4806521000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4806521000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3714500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3714500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 236709035340 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 236709035340 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 236709035340 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 236709035340 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82838741 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82838741 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 71125310 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 71125310 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828504 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 828504 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 497137 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 497137 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1979471 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1979471 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1935209 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1935209 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 154461188 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 154461188 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 155289692 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 155289692 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.076924 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.076924 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098624 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.098624 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794294 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794294 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.897083 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.897083 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140721 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140721 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099965 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099965 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.089556 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.089556 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.093316 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.093316 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14710.024346 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14710.024346 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18691.228536 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18691.228536 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 26590.863346 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 26590.863346 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14744.953384 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14744.953384 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24845.936739 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24845.936739 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 457080025 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 457080025 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 145190780 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 145190780 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 62993534 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 62993534 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 167629 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 167629 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 116242 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 116242 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1721505 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1721505 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1728884 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1728884 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 208300556 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 208300556 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 208468185 # number of overall hits +system.cpu1.dcache.overall_hits::total 208468185 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 5993321 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 5993321 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6604202 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6604202 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 607895 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 607895 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 421696 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 421696 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 237246 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 237246 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187668 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 187668 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13019219 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13019219 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13627114 # number of overall misses +system.cpu1.dcache.overall_misses::total 13627114 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 89379669000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 89379669000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119695443135 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 119695443135 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10488678921 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10488678921 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3322992000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3322992000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4669078500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4669078500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3521000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3521000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 219563791056 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 219563791056 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 219563791056 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 219563791056 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 151184101 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 151184101 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 69597736 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 69597736 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 775524 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 775524 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 537938 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 537938 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1958751 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1958751 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1916552 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1916552 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 221319775 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 221319775 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 222095299 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 222095299 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039643 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.039643 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094891 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.094891 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.783851 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.783851 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.783912 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.783912 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121121 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121121 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097920 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097920 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.058825 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.058825 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.061357 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.061357 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14913.212391 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14913.212391 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18124.134170 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18124.134170 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24872.607094 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24872.607094 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14006.524873 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14006.524873 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24879.460004 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24879.460004 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17111.926184 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17111.926184 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16334.830072 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16334.830072 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 3137293 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 21285332 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 376632 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 706469 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.329863 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 30.129180 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5420571 # number of writebacks -system.cpu1.dcache.writebacks::total 5420571 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3225514 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3225514 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5658563 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5658563 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3397 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3397 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 142581 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 142581 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8887474 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8887474 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8887474 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8887474 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3146802 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3146802 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1356134 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1356134 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 657988 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 657988 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 442576 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 442576 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 135972 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 135972 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193443 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 193443 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4945512 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4945512 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5603500 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5603500 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6183 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 12301 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 12301 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43613350000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43613350000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26794309953 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26794309953 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14059014500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14059014500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11316204599 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11316204599 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1866790500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1866790500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4613147000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4613147000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3645500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3645500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 81723864552 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 81723864552 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 95782879052 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 95782879052 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 749898500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 749898500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749898500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749898500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037987 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037987 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019067 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019067 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794188 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794188 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.890250 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.890250 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068691 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068691 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099960 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099960 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032018 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032018 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036084 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.036084 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13859.578709 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13859.578709 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19757.863126 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19757.863126 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21366.673100 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21366.673100 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 25568.952223 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 25568.952223 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13729.227341 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13729.227341 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23847.577839 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23847.577839 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16864.590038 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16864.590038 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16112.273740 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16112.273740 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 2706631 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18960106 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 351175 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 660083 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.707357 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 28.723821 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 5047462 # number of writebacks +system.cpu1.dcache.writebacks::total 5047462 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3052290 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3052290 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5325465 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5325465 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3276 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3276 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 122610 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 122610 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8381031 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8381031 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8381031 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8381031 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2941031 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2941031 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1278737 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1278737 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 607807 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 607807 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 418420 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 418420 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 114636 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 114636 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187667 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 187667 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4638188 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4638188 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5245995 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5245995 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7218 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7218 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7480 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7480 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14698 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14698 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39704145500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39704145500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24666220214 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24666220214 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14600377000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14600377000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9957787421 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9957787421 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1521960000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1521960000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4481476500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4481476500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3456000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3456000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74328153135 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 74328153135 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 88928530135 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 88928530135 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 880126000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 880126000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 880126000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 880126000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.019453 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.019453 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018373 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018373 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.783737 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.783737 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.777822 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.777822 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058525 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058525 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097919 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097919 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.020957 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.020957 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.023620 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.023620 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13500.077184 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13500.077184 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19289.517871 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19289.517871 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24021.403176 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24021.403176 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23798.545531 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23798.545531 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.457657 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.457657 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23879.938934 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23879.938934 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16524.854161 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16524.854161 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17093.402169 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17093.402169 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122572.491010 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 122572.491010 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 60962.401431 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 60962.401431 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 5742782 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.536552 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 193871102 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5743294 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 33.756082 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8517126060000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.536552 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979564 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.979564 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16025.256659 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16025.256659 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16951.699370 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16951.699370 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 121934.885010 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 121934.885010 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59880.664036 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59880.664036 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 5706197 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.707809 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 258521982 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5706709 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 45.301413 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8517122288000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.707809 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979898 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.979898 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 396 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 307 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 405638078 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 405638078 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 193871102 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 193871102 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 193871102 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 193871102 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 193871102 # number of overall hits -system.cpu1.icache.overall_hits::total 193871102 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6076268 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6076268 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6076268 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6076268 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6076268 # number of overall misses -system.cpu1.icache.overall_misses::total 6076268 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64119298557 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 64119298557 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 64119298557 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 64119298557 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 64119298557 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 64119298557 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 199947370 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 199947370 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 199947370 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 199947370 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 199947370 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 199947370 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030389 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030389 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030389 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030389 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030389 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030389 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10552.414501 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10552.414501 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10552.414501 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10552.414501 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10552.414501 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10552.414501 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 9320412 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 212 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 713481 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.063294 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 70.666667 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 5742782 # number of writebacks -system.cpu1.icache.writebacks::total 5742782 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 332930 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 332930 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 332930 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 332930 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 332930 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 332930 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5743338 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5743338 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5743338 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5743338 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5743338 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5743338 # number of overall MSHR misses +system.cpu1.icache.tags.tag_accesses 534817167 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 534817167 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 258521982 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 258521982 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 258521982 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 258521982 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 258521982 # number of overall hits +system.cpu1.icache.overall_hits::total 258521982 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 6033199 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 6033199 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 6033199 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 6033199 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 6033199 # number of overall misses +system.cpu1.icache.overall_misses::total 6033199 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64071626251 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 64071626251 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 64071626251 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 64071626251 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 64071626251 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 64071626251 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 264555181 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 264555181 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 264555181 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 264555181 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 264555181 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 264555181 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022805 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022805 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022805 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022805 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022805 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022805 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10619.843014 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10619.843014 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10619.843014 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10619.843014 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10619.843014 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10619.843014 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 9429094 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 244 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 708482 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.308869 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 5706197 # number of writebacks +system.cpu1.icache.writebacks::total 5706197 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 326394 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 326394 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 326394 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 326394 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 326394 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 326394 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5706805 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5706805 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5706805 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5706805 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5706805 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5706805 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58166889552 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 58166889552 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58166889552 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 58166889552 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58166889552 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 58166889552 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6789498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6789498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6789498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6789498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028724 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10127.714850 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101335.791045 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101335.791045 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7416585 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7422175 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 5069 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58058775330 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 58058775330 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58058775330 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 58058775330 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58058775330 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 58058775330 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6679498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6679498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6679498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6679498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021571 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.021571 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.021571 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10173.604202 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10173.604202 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10173.604202 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99694 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99694 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99694 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99694 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6901811 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6907587 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 5314 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 930081 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2216875 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13443.573819 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 16807540 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2232789 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.527599 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9871196159000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12560.451650 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.875087 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 63.205555 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 757.041527 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.766629 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003838 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003858 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.046206 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.820531 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1320 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14527 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 25 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 72 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 681 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 425 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1030 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5623 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4561 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3143 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.886658 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 383680582 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 383680582 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 591753 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 193382 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 785135 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3353025 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3353025 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 7809020 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 7809020 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 779 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 779 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 872441 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 872441 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5195235 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 5195235 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2967964 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2967964 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 177430 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 177430 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 591753 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 193382 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5195235 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3840405 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9820775 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 591753 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 193382 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5195235 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3840405 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9820775 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13125 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9784 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 22909 # number of ReadReq misses -system.cpu1.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses -system.cpu1.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses +system.cpu1.l2cache.prefetcher.pfSpanPage 821749 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2026075 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13356.542127 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 16274118 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2041771 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 7.970589 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9992426830500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 12440.422172 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 43.172118 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 33.879322 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000015 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 839.068499 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.759303 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002635 # 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average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36110.304736 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26962.650321 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28763.842481 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28763.842481 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 28069.480634 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 28069.480634 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29359.627093 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52588.772093 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36378.343549 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 114548.545276 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114324.009701 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 56971.628323 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57171.248383 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 23197310 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11940096 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1942556 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1942287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 900600 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10671947 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6183 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6183 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4554023 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 7810324 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2589255 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 981692 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 441382 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 342905 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 485827 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1162425 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1140502 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5743338 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4866994 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 495411 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 441012 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17229566 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17476902 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 425595 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1276864 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 36408927 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 735111088 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 677743701 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1625328 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4839024 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1419319141 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6390553 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 18731260 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.122712 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.328150 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.216738 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30698.366424 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44779.098624 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21123.913810 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21123.913810 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16366.066612 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16366.066612 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247208.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247208.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33772.345856 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33772.345856 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28015.333267 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28790.171126 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28790.171126 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26887.644192 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26887.644192 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29817.820889 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29263.608095 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29817.820889 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33864.848983 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 113906.275977 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113706.451613 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55937.916723 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56102.370471 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 22350657 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11505244 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1543 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1883368 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1883027 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 341 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 842183 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10302833 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 7480 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7480 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4215889 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7583095 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2514473 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 909607 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 430035 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 341692 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 476439 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1090279 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1068076 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5706805 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4656106 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 474602 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 416607 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17119850 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16343111 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 395526 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1186164 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 35044651 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 730427376 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 631688689 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1504072 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4470264 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1368090401 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6163170 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 73999248 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 18018661 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.123449 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.329009 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 16432977 87.73% 87.73% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2298014 12.27% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 269 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 15794619 87.66% 87.66% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2223701 12.34% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 341 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 18731260 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 23041315974 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 18018661 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 22188055468 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 175324271 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 182014003 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8621166733 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8566090793 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8059431425 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7517136176 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 222762323 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 207825380 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 672656647 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 628033176 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40341 # Transaction distribution -system.iobus.trans_dist::ReadResp 40341 # Transaction distribution -system.iobus.trans_dist::WriteReq 136646 # Transaction distribution -system.iobus.trans_dist::WriteResp 136646 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47790 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40328 # Transaction distribution +system.iobus.trans_dist::ReadResp 40328 # Transaction distribution +system.iobus.trans_dist::WriteReq 136631 # Transaction distribution +system.iobus.trans_dist::WriteResp 136631 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47646 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -3021,15 +3022,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122580 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231258 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353974 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47810 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47666 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3040,21 +3041,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155802 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155687 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339048 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37061004 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496821 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36938002 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 332000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -3066,79 +3067,79 @@ system.iobus.reqLayer14.occupancy 10500 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 13500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24283001 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24205503 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36403501 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36443500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569028004 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569408550 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92757000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92680000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147954000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115592 # number of replacements -system.iocache.tags.tagsinuse 11.302694 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115626 # number of replacements +system.iocache.tags.tagsinuse 11.305309 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115642 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9115775800000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.842796 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.459898 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240175 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466244 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706418 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9115830406000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.413187 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.892123 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463324 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.243258 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706582 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040856 # Number of tag accesses -system.iocache.tags.data_accesses 1040856 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1041018 # Number of tag accesses +system.iocache.tags.data_accesses 1041018 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8901 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8938 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses -system.iocache.demand_misses::total 115651 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115629 # number of demand (read+write) misses +system.iocache.demand_misses::total 115669 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115611 # number of overall misses -system.iocache.overall_misses::total 115651 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5246000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1667860010 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1673106010 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115629 # number of overall misses +system.iocache.overall_misses::total 115669 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5198500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1667264523 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1672463023 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12956345994 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12956345994 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5615000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14624206004 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14629821004 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5615000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14624206004 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14629821004 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12925157527 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12925157527 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5567500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14592422050 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14597989550 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5567500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14592422050 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14597989550 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8901 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8938 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115611 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115651 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115629 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115669 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115611 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115629 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115669 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3152,53 +3153,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141783.783784 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 187758.641225 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 187567.938341 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140500 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 187312.046175 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 187118.261692 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121395.941028 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 121395.941028 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 140375 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126499.736310 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 140375 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126499.736310 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33436 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121103.717178 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 121103.717178 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 126200.365393 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126204.856530 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 126200.365393 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126204.856530 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33241 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3541 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3524 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.442530 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.432747 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106695 # number of writebacks +system.iocache.writebacks::total 106695 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8901 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8938 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115611 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115651 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115629 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115669 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115611 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115651 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3396000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1223710010 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1227106010 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115629 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115669 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1222214523 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1225563023 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7611309187 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7611309187 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3615000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8835019197 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8838634197 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3615000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8835019197 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8838634197 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7580015931 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7580015931 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3567500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8802230454 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8805797954 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3567500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8802230454 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8805797954 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3212,660 +3213,664 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91783.783784 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137758.641225 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 137567.938341 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90500 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137312.046175 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 137118.261692 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71315.017493 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71315.017493 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1423185 # number of replacements -system.l2c.tags.tagsinuse 63448.336905 # Cycle average of tags in use -system.l2c.tags.total_refs 6060449 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1482600 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.087717 # Average number of references to valid blocks. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71021.811811 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71021.811811 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76124.765016 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76129.282297 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76124.765016 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76129.282297 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1557710 # number of replacements +system.l2c.tags.tagsinuse 63573.891854 # Cycle average of tags in use +system.l2c.tags.total_refs 6243665 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1617388 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.860338 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 3022937500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 20826.975184 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.832374 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 12.742051 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3854.622142 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3569.542843 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 2315.690288 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 335.622211 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 552.279614 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2996.807733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11095.009846 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17872.212619 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.317794 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000257 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000194 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.058817 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.054467 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.035335 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.008427 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.045728 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.169296 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.272708 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.968145 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10702 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 222 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48491 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 21119.731437 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 317.083055 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 501.157048 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4189.705266 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 12756.928607 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 18825.078792 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 29.382680 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 33.853586 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2676.679680 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1884.367858 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1239.923843 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.322262 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004838 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.007647 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.063930 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.194655 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.287248 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000448 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000517 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040843 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.028753 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.018920 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.970061 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 11464 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 277 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 47937 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::2 1377 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 482 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 8826 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5614 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 39761 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.163300 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 76659871 # Number of tag accesses -system.l2c.tags.data_accesses 76659871 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2799563 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2799563 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 175772 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 127713 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 303485 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 39800 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 41169 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 80969 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55176 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52470 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107646 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6441 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4632 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 512914 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 602529 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 321191 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6205 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4222 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 506602 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 564191 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 285940 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2814867 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 134470 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 123510 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 257980 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6441 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4632 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 512914 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 657705 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 321191 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6205 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4222 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 506602 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 616661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 285940 # number of demand (read+write) hits -system.l2c.demand_hits::total 2922513 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6441 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4632 # number of overall hits -system.l2c.overall_hits::cpu0.inst 512914 # number of overall hits -system.l2c.overall_hits::cpu0.data 657705 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 321191 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6205 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4222 # number of overall hits -system.l2c.overall_hits::cpu1.inst 506602 # number of overall hits -system.l2c.overall_hits::cpu1.data 616661 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 285940 # number of overall hits -system.l2c.overall_hits::total 2922513 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 65800 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 60076 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 125876 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 12292 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 11651 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 23943 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76423 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 57499 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133922 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1380 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 911 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 60940 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 127468 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 217255 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3149 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2958 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 41472 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 123752 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 256869 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 836154 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 453643 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 128024 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 581667 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1380 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 911 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 60940 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 203891 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 217255 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3149 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2958 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 41472 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 181251 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 256869 # 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average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24165.559172 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81260.835984 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79545.899685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 78527.795024 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84962.739511 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127321.987159 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 84841.766649 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77758.231343 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86688.086112 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128844.489781 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 105739.396778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81260.835984 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79545.899685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 78527.795024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84962.739511 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127321.987159 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 84841.766649 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77758.231343 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86688.086112 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128844.489781 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 105739.396778 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164853.967627 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 96561.069817 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121669.858307 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167775.627329 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 95912.972007 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121759.442826 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82650.590416 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48017.521994 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74089.494383 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3952559 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2414080 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84328.526919 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 47094.992243 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74147.671970 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 4190264 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2528993 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3019 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 60003 # Transaction distribution -system.membus.trans_dist::ReadResp 904829 # Transaction distribution -system.membus.trans_dist::WriteReq 38534 # Transaction distribution -system.membus.trans_dist::WriteResp 38534 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1242017 # Transaction distribution -system.membus.trans_dist::CleanEvict 238236 # Transaction distribution -system.membus.trans_dist::UpgradeReq 446737 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 299659 # Transaction distribution -system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 144708 # Transaction distribution -system.membus.trans_dist::ReadExResp 128413 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 844826 # Transaction distribution -system.membus.trans_dist::InvalidateReq 684897 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122672 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 59861 # Transaction distribution +system.membus.trans_dist::ReadResp 1006452 # Transaction distribution +system.membus.trans_dist::WriteReq 38438 # Transaction distribution +system.membus.trans_dist::WriteResp 38438 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1336656 # Transaction distribution +system.membus.trans_dist::CleanEvict 266935 # Transaction distribution +system.membus.trans_dist::UpgradeReq 438975 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 302731 # Transaction distribution +system.membus.trans_dist::UpgradeResp 22 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 150471 # Transaction distribution +system.membus.trans_dist::ReadExResp 135365 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 946591 # Transaction distribution +system.membus.trans_dist::InvalidateReq 696687 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122580 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4681290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4830500 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5068695 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155802 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26078 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5027920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5176654 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238145 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238145 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5414799 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155687 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52924 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 134692416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 134901698 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7273344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7273344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 142175042 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 606585 # Total snoops (count) -system.membus.snoop_fanout::samples 2519367 # Request fanout histogram -system.membus.snoop_fanout::mean 0.015113 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.122002 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52156 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147706944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 147915343 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7266880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 155182223 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 597489 # Total snoops (count) +system.membus.snoopTraffic 179456 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2633759 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013061 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.113535 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2481292 98.49% 98.49% # Request fanout histogram -system.membus.snoop_fanout::1 38075 1.51% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2599360 98.69% 98.69% # Request fanout histogram +system.membus.snoop_fanout::1 34399 1.31% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2519367 # Request fanout histogram -system.membus.reqLayer0.occupancy 98170994 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2633759 # Request fanout histogram +system.membus.reqLayer0.occupancy 98019495 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22248500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21931994 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8723892621 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9377704107 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5223815230 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5794716587 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45514707 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45616715 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3908,82 +3913,83 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 11842018 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6441759 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1913591 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 133722 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 121814 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11908 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 60005 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4492996 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38534 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38534 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3934886 # Transaction distribution +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 12205642 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6628070 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1941255 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 157740 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 142803 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 14937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 59863 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4654836 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38438 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38438 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4118892 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2625367 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 741215 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 380628 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1121842 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 140 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295903 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295903 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4433512 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 874748 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 839647 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9358904 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7932274 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17291178 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 230390413 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198586357 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 428976770 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2884507 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8248846 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.358423 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.482538 # Request fanout histogram +system.toL2Bus.trans_dist::CleanEvict 2762121 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 740907 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 383504 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1124411 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 124 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 298356 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298356 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4595571 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 881263 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 849910 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10458732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7383011 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17841743 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 265418110 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179948433 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 445366543 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3005080 # Total snoops (count) +system.toL2Bus.snoopTraffic 132103248 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 8556754 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.351410 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.481053 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5304178 64.30% 64.30% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2932760 35.55% 99.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11908 0.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5564766 65.03% 65.03% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2977051 34.79% 99.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 14937 0.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8248846 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9216694138 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8556754 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9506782087 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2593163 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2628899 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4234968582 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4728944566 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3934186551 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3692981173 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13240 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 14084 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5626 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 4835 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal index 8e5190276..cbe8d6472 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000018] Console: colour dummy device 80x25
-[ 0.000020] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000021] pid_max: default: 32768 minimum: 301
-[ 0.000029] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000030] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000132] hw perfevents: no hardware support available
-[ 0.060034] CPU1: Booted secondary processor
-[ 1.080058] CPU2: failed to come online
-[ 2.100109] CPU3: failed to come online
-[ 2.100111] Brought up 2 CPUs
-[ 2.100112] SMP: Total of 2 processors activated.
-[ 2.100158] devtmpfs: initialized
-[ 2.100486] atomic64_test: passed
-[ 2.100520] regulator-dummy: no parameters
-[ 2.100764] NET: Registered protocol family 16
-[ 2.100855] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 2.100862] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 2.101406] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 2.101409] Serial: AMBA PL011 UART driver
-[ 2.101542] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 2.101569] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 2.102150] console [ttyAMA0] enabled
-[ 2.102255] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 2.102304] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 2.102356] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 2.102402] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 2.140243] 3V3: 3300 mV
-[ 2.140289] vgaarb: loaded
-[ 2.140336] SCSI subsystem initialized
-[ 2.140372] libata version 3.00 loaded.
-[ 2.140432] usbcore: registered new interface driver usbfs
-[ 2.140452] usbcore: registered new interface driver hub
-[ 2.140475] usbcore: registered new device driver usb
-[ 2.140509] pps_core: LinuxPPS API ver. 1 registered
-[ 2.140519] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 2.140540] PTP clock support registered
-[ 2.140668] Switched to clocksource arch_sys_counter
-[ 2.141701] NET: Registered protocol family 2
-[ 2.141770] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 2.141785] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 2.141801] TCP: Hash tables configured (established 2048 bind 2048)
-[ 2.141824] TCP: reno registered
-[ 2.141831] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.141842] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.141872] NET: Registered protocol family 1
-[ 2.141906] RPC: Registered named UNIX socket transport module.
-[ 2.141917] RPC: Registered udp transport module.
-[ 2.141925] RPC: Registered tcp transport module.
-[ 2.141933] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 2.141946] PCI: CLS 0 bytes, default 64
-[ 2.142111] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 2.142194] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 2.143636] fuse init (API version 7.23)
-[ 2.143718] msgmni has been set to 469
-[ 2.143799] io scheduler noop registered
-[ 2.143835] io scheduler cfq registered (default)
-[ 2.144137] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 2.144150] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 2.144161] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.144173] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 2.144183] pci_bus 0000:00: scanning bus
-[ 2.144193] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 2.144206] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 2.144220] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.144247] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 2.144259] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 2.144269] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 2.144280] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.144290] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 2.144301] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 2.144312] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.144339] pci_bus 0000:00: fixups for bus
-[ 2.144347] pci_bus 0000:00: bus scan returning with max=00
-[ 2.144358] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 2.144376] pci 0000:00:00.0: fixup irq: got 33
-[ 2.144384] pci 0000:00:00.0: assigning IRQ 33
-[ 2.144394] pci 0000:00:01.0: fixup irq: got 34
-[ 2.144402] pci 0000:00:01.0: assigning IRQ 34
-[ 2.144413] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 2.144426] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.144438] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 2.144451] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 2.144462] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.144473] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 2.144485] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 2.144496] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 2.144948] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.145137] ata_piix 0000:00:01.0: version 2.13
-[ 2.145148] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.145169] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.145354] scsi0 : ata_piix
-[ 2.145413] scsi1 : ata_piix
-[ 2.145434] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.145446] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.145522] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 2.145534] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 2.145547] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.145559] e1000 0000:00:00.0: enabling bus mastering
-[ 2.290704] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.290714] ata1.00: 2096640 sectors, multi 0: LBA
-[ 2.290739] ata1.00: configured for UDMA/33
-[ 2.290784] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.290883] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.290917] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.290926] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.290943] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.290996] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 2.291064] sda: sda1
-[ 2.291152] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 2.410949] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 2.410962] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 2.410980] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 2.410990] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 2.411008] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 2.411020] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 2.411070] usbcore: registered new interface driver usb-storage
-[ 2.411118] mousedev: PS/2 mouse device common for all mice
-[ 2.411225] usbcore: registered new interface driver usbhid
-[ 2.411235] usbhid: USB HID core driver
-[ 2.411260] TCP: cubic registered
-[ 2.411267] NET: Registered protocol family 17
- -[ 2.411619] devtmpfs: mounted
-[ 2.411656] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000015] Console: colour dummy device 80x25
+[ 0.000016] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000017] pid_max: default: 32768 minimum: 301
+[ 0.000024] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000025] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000098] hw perfevents: no hardware support available
+[ 0.060026] CPU1: Booted secondary processor
+[ 1.080051] CPU2: failed to come online
+[ 2.100096] CPU3: failed to come online
+[ 2.100099] Brought up 2 CPUs
+[ 2.100099] SMP: Total of 2 processors activated.
+[ 2.100138] devtmpfs: initialized
+[ 2.100443] atomic64_test: passed
+[ 2.100470] regulator-dummy: no parameters
+[ 2.100693] NET: Registered protocol family 16
+[ 2.100775] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.100781] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.100925] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.100928] Serial: AMBA PL011 UART driver
+[ 2.101044] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.101067] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.101650] console [ttyAMA0] enabled
+[ 2.101714] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.101743] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.101771] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.101798] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.140207] 3V3: 3300 mV
+[ 2.140239] vgaarb: loaded
+[ 2.140270] SCSI subsystem initialized
+[ 2.140299] libata version 3.00 loaded.
+[ 2.140331] usbcore: registered new interface driver usbfs
+[ 2.140346] usbcore: registered new interface driver hub
+[ 2.140370] usbcore: registered new device driver usb
+[ 2.140390] pps_core: LinuxPPS API ver. 1 registered
+[ 2.140399] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.140417] PTP clock support registered
+[ 2.140503] Switched to clocksource arch_sys_counter
+[ 2.141444] NET: Registered protocol family 2
+[ 2.141497] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.141512] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.141527] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.141543] TCP: reno registered
+[ 2.141550] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.141561] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.141588] NET: Registered protocol family 1
+[ 2.141628] RPC: Registered named UNIX socket transport module.
+[ 2.141638] RPC: Registered udp transport module.
+[ 2.141647] RPC: Registered tcp transport module.
+[ 2.141655] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.141667] PCI: CLS 0 bytes, default 64
+[ 2.141771] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.141835] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.142859] fuse init (API version 7.23)
+[ 2.142916] msgmni has been set to 469
+[ 2.143149] io scheduler noop registered
+[ 2.143186] io scheduler cfq registered (default)
+[ 2.143405] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.143418] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.143429] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.143442] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.143451] pci_bus 0000:00: scanning bus
+[ 2.143461] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.143473] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.143487] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.143514] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.143526] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.143536] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.143547] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.143557] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.143567] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.143578] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.143604] pci_bus 0000:00: fixups for bus
+[ 2.143612] pci_bus 0000:00: bus scan returning with max=00
+[ 2.143623] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.143640] pci 0000:00:00.0: fixup irq: got 33
+[ 2.143648] pci 0000:00:00.0: assigning IRQ 33
+[ 2.143658] pci 0000:00:01.0: fixup irq: got 34
+[ 2.143666] pci 0000:00:01.0: assigning IRQ 34
+[ 2.143676] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.143689] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.143702] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.143715] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.143726] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.143737] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.143748] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.143759] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.144053] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.144214] ata_piix 0000:00:01.0: version 2.13
+[ 2.144224] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.144241] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.144410] scsi0 : ata_piix
+[ 2.144458] scsi1 : ata_piix
+[ 2.144479] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.144492] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.144562] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.144575] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.144587] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.144599] e1000 0000:00:00.0: enabling bus mastering
+[ 2.290528] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.290538] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.290562] ata1.00: configured for UDMA/33
+[ 2.290599] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.290672] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.290676] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.290693] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.290693] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.290701] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.290789] sda: sda1
+[ 2.290864] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.410776] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.410789] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.410807] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.410817] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.410834] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.410846] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.410894] usbcore: registered new interface driver usb-storage
+[ 2.410940] mousedev: PS/2 mouse device common for all mice
+[ 2.411046] usbcore: registered new interface driver usbhid
+[ 2.411056] usbhid: USB HID core driver
+[ 2.411079] TCP: cubic registered
+[ 2.411086] NET: Registered protocol family 17
+ +[ 2.411396] devtmpfs: mounted
+[ 2.411414] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.447817] udevd[609]: starting version 182
+[ 2.447448] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.532679] random: dd urandom read with 18 bits of entropy available
+[ 2.532422] random: dd urandom read with 18 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.640899] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.640730] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
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