diff options
author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
---|---|---|
committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3 | |
parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz |
stats: update references
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3')
5 files changed, 1782 insertions, 1514 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini index 2ab6e4e82..945f8e486 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -121,6 +134,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -159,6 +173,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -198,8 +216,15 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache @@ -208,13 +233,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -233,8 +262,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -257,9 +291,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -273,9 +312,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -551,13 +595,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -576,8 +624,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -635,9 +688,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -651,9 +709,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -664,13 +727,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -689,8 +756,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -698,9 +770,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -745,9 +823,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -761,13 +844,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -786,8 +873,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -795,9 +887,15 @@ size=1024 type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -811,11 +909,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -860,6 +963,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -871,7 +975,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -914,10 +1022,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -998,14 +1111,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1014,13 +1132,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1030,6 +1153,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1100,10 +1224,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1183,17 +1312,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1219,12 +1353,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1232,14 +1372,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1325,14 +1470,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1341,13 +1491,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1356,13 +1511,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1370,11 +1530,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1388,11 +1553,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1406,19 +1576,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1464,14 +1640,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1480,11 +1671,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1494,21 +1690,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1518,12 +1724,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1532,10 +1743,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1545,12 +1761,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1560,26 +1781,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1588,10 +1819,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1599,10 +1835,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1610,21 +1851,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1638,11 +1889,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1653,11 +1909,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1665,10 +1926,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simerr index 3c2cf37c0..082803b1b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simerr @@ -3,6 +3,7 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout index 596287bde..25ac82c4f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 11:54:11 -gem5 executing on e104799-lin, pid 641 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:40:47 +gem5 executing on e108600-lin, pid 23116 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3 Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51291805611000 because m5_exit instruction encountered +Exiting @ tick 51327142820000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 3c37d97cb..7cac85e04 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.327140 # Number of seconds simulated -sim_ticks 51327139864000 # Number of ticks simulated -final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.327143 # Number of seconds simulated +sim_ticks 51327142820000 # Number of ticks simulated +final_tick 51327142820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 138298 # Simulator instruction rate (inst/s) -host_op_rate 162502 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8369157499 # Simulator tick rate (ticks/s) -host_mem_usage 688884 # Number of bytes of host memory used -host_seconds 6132.89 # Real time elapsed on the host -sim_insts 848164321 # Number of instructions simulated -sim_ops 996610207 # Number of ops (including micro ops) simulated +host_inst_rate 147527 # Simulator instruction rate (inst/s) +host_op_rate 173346 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8926963197 # Simulator tick rate (ticks/s) +host_mem_usage 681308 # Number of bytes of host memory used +host_seconds 5749.68 # Real time elapsed on the host +sim_insts 848230502 # Number of instructions simulated +sim_ops 996685945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 41583048 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 443008 # Number of bytes read from this memory -system.physmem.bytes_read::total 48132008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5661728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5661728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68386496 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.itb.walker 212864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5673056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 41642312 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory +system.physmem.bytes_read::total 48200872 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5673056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5673056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 68445056 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 68407076 # Number of bytes written to this memory +system.physmem.bytes_written::total 68465636 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 3558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3383 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 104417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 649748 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6922 # Number of read requests responded to by this memory -system.physmem.num_reads::total 768028 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1068539 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3326 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 104594 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 650674 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory +system.physmem.num_reads::total 769104 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1069454 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1071112 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1072027 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 4436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 110307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 810157 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 937750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 110307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 110307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1332365 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 110527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 811312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 939091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 110527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 110527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1333506 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1332766 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1332365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 1333907 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1333506 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 4436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 110307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 810558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2270516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 768028 # Number of read requests accepted -system.physmem.writeReqs 1071112 # Number of write requests accepted -system.physmem.readBursts 768028 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1071112 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 49106944 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 46848 # Total number of bytes read from write queue -system.physmem.bytesWritten 68406272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 48132008 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 68407076 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 732 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu.itb.walker 4147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 110527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 811713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2272998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 769104 # Number of read requests accepted +system.physmem.writeReqs 1072027 # Number of write requests accepted +system.physmem.readBursts 769104 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1072027 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 49176064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 46592 # Total number of bytes read from write queue +system.physmem.bytesWritten 68464384 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 48200872 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 68465636 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 728 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 45073 # Per bank write bursts -system.physmem.perBankRdBursts::1 51507 # Per bank write bursts -system.physmem.perBankRdBursts::2 47331 # Per bank write bursts -system.physmem.perBankRdBursts::3 43047 # Per bank write bursts -system.physmem.perBankRdBursts::4 45469 # Per bank write bursts -system.physmem.perBankRdBursts::5 51901 # Per bank write bursts -system.physmem.perBankRdBursts::6 46387 # Per bank write bursts -system.physmem.perBankRdBursts::7 47163 # Per bank write bursts -system.physmem.perBankRdBursts::8 43832 # Per bank write bursts -system.physmem.perBankRdBursts::9 71407 # Per bank write bursts -system.physmem.perBankRdBursts::10 44269 # Per bank write bursts -system.physmem.perBankRdBursts::11 52269 # Per bank write bursts -system.physmem.perBankRdBursts::12 42900 # Per bank write bursts -system.physmem.perBankRdBursts::13 46591 # Per bank write bursts -system.physmem.perBankRdBursts::14 43222 # Per bank write bursts -system.physmem.perBankRdBursts::15 44928 # Per bank write bursts -system.physmem.perBankWrBursts::0 64149 # Per bank write bursts -system.physmem.perBankWrBursts::1 68917 # Per bank write bursts -system.physmem.perBankWrBursts::2 66979 # Per bank write bursts -system.physmem.perBankWrBursts::3 64863 # Per bank write bursts -system.physmem.perBankWrBursts::4 67442 # Per bank write bursts -system.physmem.perBankWrBursts::5 70404 # Per bank write bursts -system.physmem.perBankWrBursts::6 66306 # Per bank write bursts -system.physmem.perBankWrBursts::7 67867 # Per bank write bursts -system.physmem.perBankWrBursts::8 65614 # Per bank write bursts -system.physmem.perBankWrBursts::9 70732 # Per bank write bursts -system.physmem.perBankWrBursts::10 65165 # Per bank write bursts -system.physmem.perBankWrBursts::11 71475 # Per bank write bursts -system.physmem.perBankWrBursts::12 63578 # Per bank write bursts -system.physmem.perBankWrBursts::13 66114 # Per bank write bursts -system.physmem.perBankWrBursts::14 64356 # Per bank write bursts -system.physmem.perBankWrBursts::15 64887 # Per bank write bursts +system.physmem.perBankRdBursts::0 44564 # Per bank write bursts +system.physmem.perBankRdBursts::1 52315 # Per bank write bursts +system.physmem.perBankRdBursts::2 47721 # Per bank write bursts +system.physmem.perBankRdBursts::3 44538 # Per bank write bursts +system.physmem.perBankRdBursts::4 44659 # Per bank write bursts +system.physmem.perBankRdBursts::5 50872 # Per bank write bursts +system.physmem.perBankRdBursts::6 46439 # Per bank write bursts +system.physmem.perBankRdBursts::7 47959 # Per bank write bursts +system.physmem.perBankRdBursts::8 44018 # Per bank write bursts +system.physmem.perBankRdBursts::9 71274 # Per bank write bursts +system.physmem.perBankRdBursts::10 43972 # Per bank write bursts +system.physmem.perBankRdBursts::11 51692 # Per bank write bursts +system.physmem.perBankRdBursts::12 45026 # Per bank write bursts +system.physmem.perBankRdBursts::13 46672 # Per bank write bursts +system.physmem.perBankRdBursts::14 42515 # Per bank write bursts +system.physmem.perBankRdBursts::15 44140 # Per bank write bursts +system.physmem.perBankWrBursts::0 64758 # Per bank write bursts +system.physmem.perBankWrBursts::1 69412 # Per bank write bursts +system.physmem.perBankWrBursts::2 67623 # Per bank write bursts +system.physmem.perBankWrBursts::3 66442 # Per bank write bursts +system.physmem.perBankWrBursts::4 66817 # Per bank write bursts +system.physmem.perBankWrBursts::5 69740 # Per bank write bursts +system.physmem.perBankWrBursts::6 65132 # Per bank write bursts +system.physmem.perBankWrBursts::7 69008 # Per bank write bursts +system.physmem.perBankWrBursts::8 65482 # Per bank write bursts +system.physmem.perBankWrBursts::9 70623 # Per bank write bursts +system.physmem.perBankWrBursts::10 64235 # Per bank write bursts +system.physmem.perBankWrBursts::11 70444 # Per bank write bursts +system.physmem.perBankWrBursts::12 64965 # Per bank write bursts +system.physmem.perBankWrBursts::13 66804 # Per bank write bursts +system.physmem.perBankWrBursts::14 64273 # Per bank write bursts +system.physmem.perBankWrBursts::15 63998 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 51327138450500 # Total gap between requests +system.physmem.numWrRetry 34 # Number of times write queue was full causing retry +system.physmem.totGap 51327141408500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 746743 # Read request sizes (log2) +system.physmem.readPktSize::6 747819 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1068539 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 514973 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 203448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13041 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 144 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1069454 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 515353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 203905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,126 +160,126 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 69964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 64040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 77106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 64857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 68599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 58973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 57173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 471440 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.263737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 149.464196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.749786 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 207824 44.08% 44.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 122155 25.91% 69.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 42779 9.07% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22709 4.82% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14933 3.17% 87.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9495 2.01% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7568 1.61% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6030 1.28% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 37947 8.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 471440 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 54191 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.158790 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 76.596487 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 54185 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 26806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 69842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 64006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 76985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 65026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 68511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 57192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 74 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 471870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.306089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 149.569568 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 290.567780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 207742 44.03% 44.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 122462 25.95% 69.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 42886 9.09% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22733 4.82% 83.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14982 3.18% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9606 2.04% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7566 1.60% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6003 1.27% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 37890 8.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 471870 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 54238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.166341 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 76.651597 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 54233 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 54191 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 54191 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.723718 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.774638 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.948432 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 40576 74.88% 74.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4593 8.48% 83.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 5177 9.55% 92.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1373 2.53% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 420 0.78% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 248 0.46% 96.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 301 0.56% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 130 0.24% 97.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 393 0.73% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 142 0.26% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 38 0.07% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 61 0.11% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 323 0.60% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 40 0.07% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 24 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 111 0.20% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 181 0.33% 99.89% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 54238 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 54238 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.723367 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.775784 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.950161 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 40620 74.89% 74.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4585 8.45% 83.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 5200 9.59% 92.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1381 2.55% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 413 0.76% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 235 0.43% 96.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 311 0.57% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 127 0.23% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 390 0.72% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 127 0.23% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 50 0.09% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 65 0.12% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 327 0.60% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 36 0.07% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 29 0.05% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 111 0.20% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 166 0.31% 99.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 54191 # Writes before turning the bus around for reads -system.physmem.totQLat 15195806089 # Total ticks spent queuing -system.physmem.totMemAccLat 29582606089 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3836480000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19804.36 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 12 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 54238 # Writes before turning the bus around for reads +system.physmem.totQLat 15209667379 # Total ticks spent queuing +system.physmem.totMemAccLat 29616717379 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3841880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19794.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38554.36 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38544.56 # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s @@ -288,43 +288,43 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing -system.physmem.readRowHits 579763 # Number of row buffer hits during reads -system.physmem.writeRowHits 784939 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.56 # Row buffer hit rate for reads +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.49 # Average write queue length when enqueuing +system.physmem.readRowHits 580662 # Number of row buffer hits during reads +system.physmem.writeRowHits 785598 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.44 # Row buffer hit rate for writes -system.physmem.avgGap 27908228.00 # Average gap between requests -system.physmem.pageHitRate 74.32 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1800088920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 982191375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2947417200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3479286960 # Energy for write commands per rank (pJ) +system.physmem.avgGap 27878049.64 # Average gap between requests +system.physmem.pageHitRate 74.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1803657240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 984138375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2956722600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3492279360 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1235810088180 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29712239669250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34309697958765 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.451396 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49428932348966 # Time in different power states +system.physmem_0.actBackEnergy 1235640856320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29712388110000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34309704980775 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.451533 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49429181288166 # Time in different power states system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 184281028534 # Time in different power states +system.physmem_0.memoryStateTime::ACT 184032075584 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1763997480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 962498625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3037452600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3446848080 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 1763679960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 962325375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3036563400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3439739520 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1235330422065 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29712660420750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34309640856480 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.450284 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49429628001327 # Time in different power states +system.physmem_1.actBackEnergy 1235034526230 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29712919978500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34309596029865 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.449411 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49430060847495 # Time in different power states system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 183585648673 # Time in different power states +system.physmem_1.memoryStateTime::ACT 183155359005 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -341,30 +341,30 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 225024609 # Number of BP lookups -system.cpu.branchPred.condPredicted 149819801 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12305268 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158924221 # Number of BTB lookups -system.cpu.branchPred.BTBHits 98148969 # Number of BTB hits +system.cpu.branchPred.lookups 225047911 # Number of BP lookups +system.cpu.branchPred.condPredicted 149825196 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12305756 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158986930 # Number of BTB lookups +system.cpu.branchPred.BTBHits 98148773 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.758345 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30872234 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 343569 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6729545 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4744517 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1985028 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 766036 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 61.733863 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30878370 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 343644 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6734089 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4745857 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1988232 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 765703 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -394,89 +394,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 947007 # Table walker walks requested -system.cpu.dtb.walker.walksLong 947007 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15816 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155482 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 435407 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 511600 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2285.571736 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 14838.819778 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 508020 99.30% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 2030 0.40% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 1046 0.20% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 222 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 147 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 54 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 511600 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 486864 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 22927.774491 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 17879.583197 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20925.745088 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 475438 97.65% 97.65% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 7837 1.61% 99.26% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2530 0.52% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 265 0.05% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 545 0.11% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 113 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 104 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 16 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 486864 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 779668807876 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.725507 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.522451 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 777433889876 99.71% 99.71% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1160253500 0.15% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 513477500 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 201866500 0.03% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 152233500 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 119773500 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 32296000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 52448000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2569500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 779668807876 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 155483 90.77% 90.77% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15816 9.23% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 171299 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 947007 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 948773 # Table walker walks requested +system.cpu.dtb.walker.walksLong 948773 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15596 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155468 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 437937 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 510836 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2285.186439 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 14758.274331 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 507265 99.30% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 2025 0.40% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 1066 0.21% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 211 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 145 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 51 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 43 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 510836 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 488329 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23221.803333 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 18175.804190 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 21042.780895 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 476828 97.64% 97.64% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 7891 1.62% 99.26% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2533 0.52% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 229 0.05% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 568 0.12% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 131 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 114 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 488329 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 779668986876 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.725199 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.523523 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 777411937376 99.71% 99.71% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1169683000 0.15% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 513347500 0.07% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 208116000 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 157188000 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 121226500 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 32342000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 52541000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2605500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 779668986876 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 155469 90.88% 90.88% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15596 9.12% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 171065 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 948773 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 947007 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171299 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 948773 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171065 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171299 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1118306 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171065 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1119838 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 169398877 # DTB read hits -system.cpu.dtb.read_misses 674798 # DTB read misses -system.cpu.dtb.write_hits 147332912 # DTB write hits -system.cpu.dtb.write_misses 272209 # DTB write misses +system.cpu.dtb.read_hits 169411407 # DTB read hits +system.cpu.dtb.read_misses 675369 # DTB read misses +system.cpu.dtb.write_hits 147344334 # DTB write hits +system.cpu.dtb.write_misses 273404 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72038 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 71963 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10047 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69070 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 170073675 # DTB read accesses -system.cpu.dtb.write_accesses 147605121 # DTB write accesses +system.cpu.dtb.perms_faults 69388 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 170086776 # DTB read accesses +system.cpu.dtb.write_accesses 147617738 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 316731789 # DTB hits -system.cpu.dtb.misses 947007 # DTB misses -system.cpu.dtb.accesses 317678796 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 316755741 # DTB hits +system.cpu.dtb.misses 948773 # DTB misses +system.cpu.dtb.accesses 317704514 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -506,66 +504,66 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 162102 # Table walker walks requested -system.cpu.itb.walker.walksLong 162102 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1483 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 120022 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17916 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144186 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1142.128917 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9607.655205 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 143046 99.21% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 588 0.41% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 94 0.07% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 159 0.11% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 224 0.16% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 44 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144186 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 139421 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28788.855337 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23782.658152 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24182.866310 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 136254 97.73% 97.73% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 690 0.49% 98.22% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 2101 1.51% 99.73% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 136 0.10% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 151 0.11% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 47 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 30 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 162181 # Table walker walks requested +system.cpu.itb.walker.walksLong 162181 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1496 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 120027 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17971 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144210 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1137.740101 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9342.723838 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 143038 99.19% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 619 0.43% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 86 0.06% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 189 0.13% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 221 0.15% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 35 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144210 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 139494 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29066.088864 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24052.553358 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24213.231696 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 136396 97.78% 97.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 707 0.51% 98.29% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1985 1.42% 99.71% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 151 0.11% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 171 0.12% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 34 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 139421 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 680881393568 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.947864 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.222600 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 35543211356 5.22% 5.22% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 645294358712 94.77% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 43207500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 580000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 36000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 680881393568 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 120022 98.78% 98.78% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1483 1.22% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 121505 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 139494 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 676589720772 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.947980 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.222341 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 35236838356 5.21% 5.21% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 641313182416 94.79% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 39010000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 686000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 4000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 676589720772 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 120027 98.77% 98.77% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1496 1.23% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 121523 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162102 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 162102 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162181 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 162181 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121505 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 121505 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 283607 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 357007788 # ITB inst hits -system.cpu.itb.inst_misses 162102 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121523 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 121523 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 283704 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 357038073 # ITB inst hits +system.cpu.itb.inst_misses 162181 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -574,21 +572,21 @@ system.cpu.itb.flush_tlb 10 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52849 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52848 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 357575 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 357344 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 357169890 # ITB inst accesses -system.cpu.itb.hits 357007788 # DTB hits -system.cpu.itb.misses 162102 # DTB misses -system.cpu.itb.accesses 357169890 # DTB accesses +system.cpu.itb.inst_accesses 357200254 # ITB inst accesses +system.cpu.itb.hits 357038073 # DTB hits +system.cpu.itb.misses 162181 # DTB misses +system.cpu.itb.accesses 357200254 # DTB accesses system.cpu.numPwrStateTransitions 32228 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 16114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3134638980.534008 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 60494100077.253059 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3134631677.512784 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 60494120707.852806 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 6793 42.16% 42.16% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 9285 57.62% 99.78% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state @@ -600,139 +598,139 @@ system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 16114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 815567331675 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50511572532325 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1631144067 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 815687968559 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50511454851441 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1631385344 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 646909150 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1002667158 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225024609 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133765720 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 898024303 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26265536 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3811072 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 29306 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8704800 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1028212 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 873 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 356634442 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6247312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 47880 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1571640484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.747058 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.149321 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 646877625 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1002761410 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225047911 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133773000 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 898188451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26266186 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3841497 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 30548 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8722394 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1026877 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 1034 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 356664988 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6247416 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 47904 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1571821519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.747042 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.149310 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1013991341 64.52% 64.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 214266060 13.63% 78.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70309362 4.47% 82.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 273073721 17.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1014113227 64.52% 64.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 214297646 13.63% 78.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70312417 4.47% 82.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 273098229 17.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1571640484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.137955 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.614702 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 526349563 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 552086440 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 434104674 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49724049 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9375758 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33560071 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3814526 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1085977369 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29430616 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9375758 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 571291991 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 65924513 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 371563835 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 438965882 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 114518505 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1065686033 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6908876 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5086020 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 334343 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 634469 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 63514970 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20439 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1013378727 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1640198295 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1259502849 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1473679 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 947186300 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 66192424 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26900223 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23242764 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 101754923 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173828486 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 150818351 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9879664 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8976205 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1030662331 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27200654 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1045735608 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3378731 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 61252774 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 34075299 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 309098 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1571640484 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.665378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.919633 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1571821519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.137949 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.614669 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 526332322 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 552246914 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 434136742 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49729183 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9376358 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33563941 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3814299 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1086052117 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29449193 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9376358 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 571289803 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 66024800 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 371545208 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 438989582 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 114595768 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1065754363 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6907795 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5097238 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 334375 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 639506 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 63573833 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20465 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1013430764 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1640279788 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1259572075 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1474026 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 947250209 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 66180552 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26901106 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23243208 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 101784051 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 173837388 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 150829276 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9883117 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9014861 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1030729252 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27201158 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1045808358 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3377405 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 61244461 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 34071399 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 308913 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1571821519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.665348 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.919634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 924076917 58.80% 58.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 334351644 21.27% 80.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234725096 14.94% 95.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72033056 4.58% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6434251 0.41% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19520 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 924230442 58.80% 58.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 334342298 21.27% 80.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234750151 14.93% 95.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72048277 4.58% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6430828 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19523 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1571640484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1571821519 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57663018 35.01% 35.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100158 0.06% 35.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26751 0.02% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 667 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44277065 26.88% 61.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62625013 38.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57691324 35.03% 35.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 100152 0.06% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26730 0.02% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 622 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44285841 26.89% 62.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62576075 38.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 720295550 68.88% 68.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2531326 0.24% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122856 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 720343690 68.88% 68.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2530628 0.24% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122776 0.01% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 375 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.13% # Type of FU issued @@ -755,100 +753,100 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.13% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 119220 0.01% 69.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 119191 0.01% 69.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 173477536 16.59% 85.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 149188688 14.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 173490543 16.59% 85.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 149201098 14.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1045735608 # Type of FU issued -system.cpu.iq.rate 0.641106 # Inst issue rate -system.cpu.iq.fu_busy_cnt 164692672 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157490 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3828710820 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1118319185 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1027391540 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2472282 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 938392 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909608 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1208873256 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1555013 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4278408 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1045808358 # Type of FU issued +system.cpu.iq.rate 0.641055 # Inst issue rate +system.cpu.iq.fu_busy_cnt 164680744 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157467 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3829023509 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1118377930 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1027460456 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2472874 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 938610 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 909796 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1208933693 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1555398 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4274316 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14178366 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14475 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143083 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6061186 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14173969 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14495 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 142953 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6059351 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2527357 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1438756 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2526453 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1440750 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9375758 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6990377 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6913711 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1058098003 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9376358 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7004216 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6913167 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1058165202 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173828486 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 150818351 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22818732 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 57696 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6782714 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143083 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3464744 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5492402 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8957146 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1034225316 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169386893 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10574140 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 173837388 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 150829276 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22819114 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 57849 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6781828 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 142953 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3462734 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5495013 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8957747 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1034296660 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 169399584 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10573772 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 235018 # number of nop insts executed -system.cpu.iew.exec_refs 316715121 # number of memory reference insts executed -system.cpu.iew.exec_branches 196182084 # Number of branches executed -system.cpu.iew.exec_stores 147328228 # Number of stores executed -system.cpu.iew.exec_rate 0.634049 # Inst execution rate -system.cpu.iew.wb_sent 1029119140 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1028301148 # cumulative count of insts written-back -system.cpu.iew.wb_producers 437817967 # num instructions producing a value -system.cpu.iew.wb_consumers 708345311 # num instructions consuming a value -system.cpu.iew.wb_rate 0.630417 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618086 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 51892888 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 26891556 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8548258 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1559580657 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.639024 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273898 # Number of insts commited each cycle +system.cpu.iew.exec_nop 234792 # number of nop insts executed +system.cpu.iew.exec_refs 316739180 # number of memory reference insts executed +system.cpu.iew.exec_branches 196198672 # Number of branches executed +system.cpu.iew.exec_stores 147339596 # Number of stores executed +system.cpu.iew.exec_rate 0.633999 # Inst execution rate +system.cpu.iew.wb_sent 1029187818 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1028370252 # cumulative count of insts written-back +system.cpu.iew.wb_producers 437853372 # num instructions producing a value +system.cpu.iew.wb_consumers 708400240 # num instructions consuming a value +system.cpu.iew.wb_rate 0.630366 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618088 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 51884426 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 26892245 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8549021 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1559762540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.638999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.273827 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1047836774 67.19% 67.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288037345 18.47% 85.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120098323 7.70% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36644408 2.35% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28496008 1.83% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13936779 0.89% 98.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8648827 0.55% 98.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4175441 0.27% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11706752 0.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1047991029 67.19% 67.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288035307 18.47% 85.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120100080 7.70% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36659789 2.35% 95.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28506606 1.83% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13942789 0.89% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8651847 0.55% 98.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4181084 0.27% 99.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11694009 0.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1559580657 # Number of insts commited each cycle -system.cpu.commit.committedInsts 848164321 # Number of instructions committed -system.cpu.commit.committedOps 996610207 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1559762540 # Number of insts commited each cycle +system.cpu.commit.committedInsts 848230502 # Number of instructions committed +system.cpu.commit.committedOps 996685945 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 304407284 # Number of memory references committed -system.cpu.commit.loads 159650119 # Number of loads committed -system.cpu.commit.membars 6926917 # Number of memory barriers committed -system.cpu.commit.branches 189306416 # Number of branches committed -system.cpu.commit.fp_insts 898488 # Number of committed floating point instructions. -system.cpu.commit.int_insts 915651510 # Number of committed integer instructions. -system.cpu.commit.function_calls 25281717 # Number of function calls committed. +system.cpu.commit.refs 304433343 # Number of memory references committed +system.cpu.commit.loads 159663418 # Number of loads committed +system.cpu.commit.membars 6927415 # Number of memory barriers committed +system.cpu.commit.branches 189324067 # Number of branches committed +system.cpu.commit.fp_insts 898712 # Number of committed floating point instructions. +system.cpu.commit.int_insts 915721971 # Number of committed integer instructions. +system.cpu.commit.function_calls 25285288 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 689843263 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2149527 0.22% 69.43% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98159 0.01% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 689893101 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2149376 0.22% 69.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98151 0.01% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction @@ -875,541 +873,540 @@ system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 159650119 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 144757165 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 159663418 16.02% 85.47% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 144769925 14.53% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 996610207 # Class of committed instruction -system.cpu.commit.bw_lim_events 11706752 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2588836134 # The number of ROB reads -system.cpu.rob.rob_writes 2108972650 # The number of ROB writes -system.cpu.timesIdled 8176249 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59503583 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101023135782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 848164321 # Number of Instructions Simulated -system.cpu.committedOps 996610207 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.923146 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.923146 # CPI: Total CPI of All Threads -system.cpu.ipc 0.519981 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.519981 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1223740669 # number of integer regfile reads -system.cpu.int_regfile_writes 731349757 # number of integer regfile writes -system.cpu.fp_regfile_reads 1462624 # number of floating regfile reads -system.cpu.fp_regfile_writes 780384 # number of floating regfile writes -system.cpu.cc_regfile_reads 225040074 # number of cc regfile reads -system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes -system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads -system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9706309 # number of replacements +system.cpu.commit.op_class_0::total 996685945 # Class of committed instruction +system.cpu.commit.bw_lim_events 11694009 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2589097882 # The number of ROB reads +system.cpu.rob.rob_writes 2109106528 # The number of ROB writes +system.cpu.timesIdled 8171713 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59563825 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101022900419 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 848230502 # Number of Instructions Simulated +system.cpu.committedOps 996685945 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.923281 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.923281 # CPI: Total CPI of All Threads +system.cpu.ipc 0.519945 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.519945 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1223820104 # number of integer regfile reads +system.cpu.int_regfile_writes 731394790 # number of integer regfile writes +system.cpu.fp_regfile_reads 1462803 # number of floating regfile reads +system.cpu.fp_regfile_writes 780644 # number of floating regfile writes +system.cpu.cc_regfile_reads 225050166 # number of cc regfile reads +system.cpu.cc_regfile_writes 225684828 # number of cc regfile writes +system.cpu.misc_regfile_reads 2558325337 # number of misc regfile reads +system.cpu.misc_regfile_writes 26931155 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9701158 # number of replacements system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9706821 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.171088 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 283187639 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9701670 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.189577 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1236907465 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1236907465 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 147182281 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147182281 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128244124 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128244124 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 377753 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 377753 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 323466 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 323466 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295516 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3295516 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3691142 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3691142 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 275749871 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 275749871 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 276127624 # number of overall hits -system.cpu.dcache.overall_hits::total 276127624 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9582006 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9582006 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11252664 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11252664 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1170750 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1170750 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1233990 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1233990 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 446459 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 446459 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 22068660 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 22068660 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 23239410 # number of overall misses -system.cpu.dcache.overall_misses::total 23239410 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 168553352000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 168553352000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 444283559827 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 444283559827 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52343559973 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 52343559973 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6881905000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6881905000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 299500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 299500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 665180471800 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 665180471800 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 665180471800 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 665180471800 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 156764287 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 156764287 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 139496788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 139496788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548503 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1548503 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557456 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1557456 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3741975 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3741975 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691149 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3691149 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 297818531 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 297818531 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 299367034 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 299367034 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061124 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061124 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080666 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080666 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756053 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.756053 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792311 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.792311 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119311 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119311 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1237018765 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1237018765 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 147199934 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147199934 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128255410 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128255410 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 377663 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 377663 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 323814 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 323814 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295431 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3295431 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3691256 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3691256 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 275779158 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 275779158 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 276156821 # number of overall hits +system.cpu.dcache.overall_hits::total 276156821 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9580915 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9580915 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11254027 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11254027 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1170464 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1170464 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1233639 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1233639 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 446709 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 446709 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 22068581 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 22068581 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 23239045 # number of overall misses +system.cpu.dcache.overall_misses::total 23239045 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 168767240000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 168767240000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 444298934810 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 444298934810 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52375248289 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 52375248289 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6883962000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6883962000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 380500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 380500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 665441423099 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 665441423099 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 665441423099 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 665441423099 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 156780849 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 156780849 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 139509437 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 139509437 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548127 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1548127 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557453 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1557453 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3742140 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3742140 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691264 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3691264 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 297847739 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 297847739 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 299395866 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 299395866 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061110 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061110 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080669 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080669 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756052 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.756052 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792087 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.792087 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119373 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119373 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074101 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074101 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.077628 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.077628 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17590.612237 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17590.612237 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39482.522523 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39482.522523 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42418.139509 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42418.139509 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15414.416553 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15414.416553 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42785.714286 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42785.714286 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30141.407399 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30141.407399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28622.950058 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28622.950058 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32180640 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.074093 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074093 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.077620 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.077620 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17614.939700 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17614.939700 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39479.106884 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39479.106884 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42455.895354 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42455.895354 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15410.394686 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15410.394686 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47562.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47562.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30153.339859 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30153.339859 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28634.628622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28634.628622 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32224409 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1601871 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1601607 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089408 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.120048 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7511281 # number of writebacks -system.cpu.dcache.writebacks::total 7511281 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4454269 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4454269 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9249122 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9249122 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7130 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 7130 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218050 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 218050 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13710521 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13710521 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13710521 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13710521 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5127737 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5127737 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003542 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2003542 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163937 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1163937 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226860 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1226860 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 228409 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 228409 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8358139 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8358139 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9522076 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9522076 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7504086 # number of writebacks +system.cpu.dcache.writebacks::total 7504086 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4456599 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4456599 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9250788 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9250788 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7056 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 7056 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219268 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 219268 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13714443 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 13714443 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 13714443 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 13714443 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5124316 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5124316 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003239 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2003239 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163648 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1163648 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226583 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1226583 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227441 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 227441 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 8354138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8354138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9517786 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9517786 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84965736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 84965736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77538140437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77538140437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23685156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23685156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50670413473 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50670413473 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3210622500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3210622500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 292500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 292500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213174289910 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 213174289910 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236859446410 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 236859446410 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192022000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192022000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192022000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192022000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032710 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032710 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014363 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014363 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751653 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751653 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787733 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787733 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061040 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061040 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84959954500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 84959954500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77558080846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77558080846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23723735000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23723735000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50708992789 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50708992789 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3202218000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3202218000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 372500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 372500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213227028135 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 213227028135 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236950763135 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 236950763135 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192056000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192056000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192056000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192056000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032685 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032685 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751649 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751649 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787557 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787557 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060778 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060778 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028065 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028065 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031807 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031807 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38700.531577 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38700.531577 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20349.173967 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20349.173967 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41300.892908 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41300.892908 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14056.462311 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25504.994582 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25504.994582 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24874.769579 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24874.769579 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 15141033 # number of replacements -system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15141545 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.502248 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028048 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028048 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031790 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031790 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16579.764890 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16579.764890 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38716.339311 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38716.339311 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20387.380892 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20387.380892 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41341.672589 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41341.672589 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14079.334860 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14079.334860 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46562.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46562.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25523.522371 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25523.522371 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24895.575834 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24895.575834 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183860.561791 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183860.561791 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.720308 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.720308 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 15134592 # number of replacements +system.cpu.icache.tags.tagsinuse 511.928988 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 340756209 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15135104 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.514296 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.928986 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.928988 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 371754919 # Number of tag accesses -system.cpu.icache.tags.data_accesses 371754919 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 340718799 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 340718799 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 340718799 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 340718799 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 340718799 # number of overall hits -system.cpu.icache.overall_hits::total 340718799 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15894345 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15894345 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15894345 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15894345 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15894345 # number of overall misses -system.cpu.icache.overall_misses::total 15894345 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 214960438379 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 214960438379 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 214960438379 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 214960438379 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 214960438379 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 214960438379 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 356613144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 356613144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 356613144 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 356613144 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 356613144 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 356613144 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044570 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044570 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044570 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044570 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044570 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044570 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13524.334496 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13524.334496 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13524.334496 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13524.334496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13524.334496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13524.334496 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 23721 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 371779021 # Number of tag accesses +system.cpu.icache.tags.data_accesses 371779021 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 340756209 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 340756209 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 340756209 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 340756209 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 340756209 # number of overall hits +system.cpu.icache.overall_hits::total 340756209 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15887482 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15887482 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15887482 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15887482 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15887482 # number of overall misses +system.cpu.icache.overall_misses::total 15887482 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 214918228873 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 214918228873 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 214918228873 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 214918228873 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 214918228873 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 214918228873 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 356643691 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 356643691 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 356643691 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 356643691 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 356643691 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 356643691 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044547 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.044547 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.044547 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.044547 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.044547 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.044547 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13527.519897 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13527.519897 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13527.519897 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13527.519897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13527.519897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13527.519897 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 24649 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1460 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1517 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.247260 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.248517 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 15141033 # number of writebacks -system.cpu.icache.writebacks::total 15141033 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 752570 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 752570 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 752570 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 752570 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 752570 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 752570 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15141775 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15141775 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15141775 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15141775 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15141775 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15141775 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 15134592 # number of writebacks +system.cpu.icache.writebacks::total 15134592 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 752151 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 752151 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 752151 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 752151 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 752151 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 752151 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15135331 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15135331 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15135331 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15135331 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15135331 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15135331 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192682261392 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 192682261392 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192682261392 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 192682261392 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192682261392 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 192682261392 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192625378387 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 192625378387 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192625378387 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 192625378387 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192625378387 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 192625378387 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684938500 # 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average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12725.209653 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12725.209653 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12725.209653 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12725.209653 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12725.209653 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042438 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042438 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042438 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.042438 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.042438 # 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Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1211379 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 38.211996 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 4512200500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37206.816589 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 299.826567 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 486.948403 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7815.294504 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19533.346332 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.567731 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004575 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007430 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119252 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.298055 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997043 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 294 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62053 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 293 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 573 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2710 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5168 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53538 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004486 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946854 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 410454205 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 410454205 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 776137 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 292808 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1068945 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 7511281 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 7511281 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 15138290 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 15138290 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.298182 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996428 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 234 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62523 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 234 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 564 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2712 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5162 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54018 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003571 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.954025 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 410396361 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 410396361 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 787478 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 297374 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1084852 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 7504086 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 7504086 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 15131991 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 15131991 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 9360 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 9360 # 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number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 15058402 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7828949 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 23956296 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 776137 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 292808 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 15058402 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7828949 # number of overall hits -system.cpu.l2cache.overall_hits::total 23956296 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1568311 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1568311 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15051780 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 15051780 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6254855 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6254855 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 727039 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 727039 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 787478 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 297374 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 15051780 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7823166 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 23959798 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 787478 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 297374 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 15051780 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7823166 # number of overall hits +system.cpu.l2cache.overall_hits::total 23959798 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3559 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3383 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 6942 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 34253 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 34253 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 394920 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 394920 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83161 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 83161 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 256104 # 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number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5770895500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8189659000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004563 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.011422 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006451 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5770936000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8189699500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006306 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784612 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784612 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.201141 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.201141 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005492 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005492 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039297 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039297 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.406658 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.406658 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004563 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.011422 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005492 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.076769 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030007 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004563 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.011422 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005492 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.076769 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030007 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127418.457139 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.852976 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.852976 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69666.666667 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69666.666667 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129277.111734 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129277.111734 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124885.825844 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124885.825844 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129580.272072 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129580.272072 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69893.357947 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69893.357947 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785050 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785050 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.201159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.201159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005506 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039465 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039465 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.407265 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.407265 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.076921 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030044 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.076921 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030044 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128624.275131 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68019.072693 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68019.072693 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129347.114780 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129347.114780 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124865.765533 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124865.765533 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129442.828646 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129442.828646 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69894.144460 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69894.144460 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171356.256310 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148979.471367 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85654.636804 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.186268 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 50432401 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 25583822 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85655.237926 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.643028 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 50407203 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 25570213 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2115 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2115 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1618708 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23266675 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8579850 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 15141033 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2388844 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43666 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1963403 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1963403 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15141775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6525421 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1333524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1226860 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45466959 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29342845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 722067 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1919121 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 77450992 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1938426848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023681310 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2369528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6237568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2970715254 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1868325 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 27924144 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025024 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.156198 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8573574 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 15134592 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2391693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43548 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43556 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1963232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1963232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15135331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6520715 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1333247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1226583 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45447628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29327152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 726647 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1928826 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 77430253 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1937602080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1022907422 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2405600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6328296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2969243398 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1852603 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 72285944 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 27912596 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.024958 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.155996 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 27225372 97.50% 97.50% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 698772 2.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 27215961 97.50% 97.50% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 696635 2.50% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 27924144 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 48365955497 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 27912596 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 48339894491 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1497386 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1459384 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22743143976 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22733591738 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13408724401 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13401353655 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 426213261 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 426266814 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1139764793 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1138134788 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40299 # Transaction distribution -system.iobus.trans_dist::ReadResp 40299 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40293 # Transaction distribution +system.iobus.trans_dist::ReadResp 40293 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1620,11 +1618,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230944 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1639,16 +1637,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334208 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41885000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492128 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41884500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 342500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 345000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1666,75 +1664,75 @@ system.iobus.reqLayer16.occupancy 14500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25104500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25117000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36501000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567373998 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567323274 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147716000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147704000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115459 # number of replacements -system.iocache.tags.tagsinuse 10.423130 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115453 # number of replacements +system.iocache.tags.tagsinuse 10.423128 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13098783117000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 13098782503000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.544201 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.878929 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.878927 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.651446 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039659 # Number of tag accesses -system.iocache.tags.data_accesses 1039659 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039605 # Number of tag accesses +system.iocache.tags.data_accesses 1039605 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8808 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8845 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115478 # number of demand (read+write) misses -system.iocache.demand_misses::total 115518 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115472 # number of demand (read+write) misses +system.iocache.demand_misses::total 115512 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115478 # number of overall misses -system.iocache.overall_misses::total 115518 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1678338975 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1683410975 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115472 # number of overall misses +system.iocache.overall_misses::total 115512 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5076000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1670063987 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1675139987 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13416126023 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13416126023 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5423000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15094464998 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15099887998 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5423000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15094464998 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15099887998 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13414774287 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13414774287 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5427000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15084838274 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15090265274 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5427000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15084838274 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15090265274 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8808 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8845 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115478 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115518 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115472 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115512 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115478 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115518 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115472 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115512 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1748,53 +1746,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 190417.401293 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190194.438482 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137189.189189 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 189607.627952 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 189388.353533 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125779.325949 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135575 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130714.589917 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135575 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130714.589917 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34291 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125766.653107 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125766.653107 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135675 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130638.074607 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135675 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130638.074607 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33964 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3518 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3510 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.747300 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.676353 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8814 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8851 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8808 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8845 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115478 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115518 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115472 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115512 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115478 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115518 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3222000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237638975 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1240860975 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115472 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115512 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3226000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1229663987 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1232889987 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8077839572 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8077839572 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3423000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9315478547 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9318901547 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3423000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9315478547 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9318901547 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8076516803 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8076516803 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3427000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9306180790 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9309607790 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3427000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9306180790 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9309607790 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1808,88 +1806,89 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87081.081081 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140417.401293 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 140194.438482 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87189.189189 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139607.627952 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 139388.353533 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75719.238009 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75719.238009 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54972 # Transaction distribution -system.membus.trans_dist::ReadResp 410008 # Transaction distribution +system.membus.trans_dist::ReadResp 411033 # Transaction distribution system.membus.trans_dist::WriteReq 33696 # Transaction distribution system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1068539 # Transaction distribution -system.membus.trans_dist::CleanEvict 192763 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34977 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1069454 # Transaction distribution +system.membus.trans_dist::CleanEvict 193565 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34895 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 394295 # Transaction distribution -system.membus.trans_dist::ReadExResp 394295 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 355036 # Transaction distribution -system.membus.trans_dist::InvalidateReq 605480 # Transaction distribution +system.membus.trans_dist::ReadExReq 394310 # Transaction distribution +system.membus.trans_dist::ReadExResp 394310 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 356061 # Transaction distribution +system.membus.trans_dist::InvalidateReq 606112 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3207653 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3337273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237899 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237899 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3575172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3212019 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3341639 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237917 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237917 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3579556 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109271756 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109441726 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7267328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7267328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 116709054 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2596 # Total snoops (count) -system.membus.snoop_fanout::samples 2739791 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109397260 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109567230 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7269248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7269248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 116836478 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2560 # Total snoops (count) +system.membus.snoopTraffic 163328 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2743103 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2739791 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2743103 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2739791 # Request fanout histogram -system.membus.reqLayer0.occupancy 103925500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2743103 # Request fanout histogram +system.membus.reqLayer0.occupancy 103939500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5571500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5573000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7165123486 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7172212711 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4069623687 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4075256665 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44789891 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1932,29 +1931,29 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal index 1b50f034a..3c0eb417b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal @@ -31,136 +31,136 @@ [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000022] Console: colour dummy device 80x25
+[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[ 0.000021] Console: colour dummy device 80x25
[ 0.000024] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000025] pid_max: default: 32768 minimum: 301
[ 0.000036] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000037] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000160] hw perfevents: no hardware support available
-[ 1.060067] CPU1: failed to come online
-[ 2.080129] CPU2: failed to come online
-[ 3.100191] CPU3: failed to come online
-[ 3.100194] Brought up 1 CPUs
-[ 3.100195] SMP: Total of 1 processors activated.
-[ 3.100251] devtmpfs: initialized
-[ 3.100700] atomic64_test: passed
-[ 3.100743] regulator-dummy: no parameters
-[ 3.101166] NET: Registered protocol family 16
-[ 3.101292] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.101301] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.102003] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.102008] Serial: AMBA PL011 UART driver
-[ 3.102194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.102227] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.102794] console [ttyAMA0] enabled
-[ 3.102873] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.102904] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.102936] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.102965] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130500] 3V3: 3300 mV
-[ 3.130542] vgaarb: loaded
-[ 3.130589] SCSI subsystem initialized
-[ 3.130626] libata version 3.00 loaded.
-[ 3.130670] usbcore: registered new interface driver usbfs
-[ 3.130688] usbcore: registered new interface driver hub
-[ 3.130719] usbcore: registered new device driver usb
-[ 3.130744] pps_core: LinuxPPS API ver. 1 registered
-[ 3.130753] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.130772] PTP clock support registered
-[ 3.130888] Switched to clocksource arch_sys_counter
-[ 3.131885] NET: Registered protocol family 2
-[ 3.131959] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.131977] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.131999] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.132014] TCP: reno registered
-[ 3.132021] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132036] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132076] NET: Registered protocol family 1
-[ 3.132127] RPC: Registered named UNIX socket transport module.
-[ 3.132137] RPC: Registered udp transport module.
-[ 3.132145] RPC: Registered tcp transport module.
-[ 3.132153] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.132165] PCI: CLS 0 bytes, default 64
-[ 3.132312] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.132411] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.133969] fuse init (API version 7.23)
-[ 3.134047] msgmni has been set to 469
-[ 3.136178] io scheduler noop registered
-[ 3.136228] io scheduler cfq registered (default)
-[ 3.136665] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.136678] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.136689] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.136702] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.136712] pci_bus 0000:00: scanning bus
-[ 3.136722] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.136735] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.136749] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136786] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.136798] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.136809] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.136819] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.136830] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.136841] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.136852] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136885] pci_bus 0000:00: fixups for bus
-[ 3.136893] pci_bus 0000:00: bus scan returning with max=00
-[ 3.136906] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.136925] pci 0000:00:00.0: fixup irq: got 33
-[ 3.136933] pci 0000:00:00.0: assigning IRQ 33
-[ 3.136944] pci 0000:00:01.0: fixup irq: got 34
-[ 3.136952] pci 0000:00:01.0: assigning IRQ 34
-[ 3.136963] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.136976] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.136989] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.137002] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.137014] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.137025] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.137036] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.137048] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.137493] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.137735] ata_piix 0000:00:01.0: version 2.13
-[ 3.137746] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.137770] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.138035] scsi0 : ata_piix
-[ 3.138128] scsi1 : ata_piix
-[ 3.138156] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.138168] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.138267] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.138279] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.138294] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.138306] e1000 0000:00:00.0: enabling bus mastering
-[ 3.290915] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.290924] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.290951] ata1.00: configured for UDMA/33
-[ 3.291001] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.291104] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.291128] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.291165] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.291174] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.291193] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.291307] sda: sda1
-[ 3.291413] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.411182] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.411195] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.411215] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.411225] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.411245] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.411257] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.411320] usbcore: registered new interface driver usb-storage
-[ 3.411372] mousedev: PS/2 mouse device common for all mice
-[ 3.411510] usbcore: registered new interface driver usbhid
-[ 3.411519] usbhid: USB HID core driver
-[ 3.411550] TCP: cubic registered
-[ 3.411558] NET: Registered protocol family 17
- -[ 3.411924] devtmpfs: mounted
-[ 3.411972] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000147] hw perfevents: no hardware support available
+[ 1.060066] CPU1: failed to come online
+[ 2.080127] CPU2: failed to come online
+[ 3.100188] CPU3: failed to come online
+[ 3.100191] Brought up 1 CPUs
+[ 3.100192] SMP: Total of 1 processors activated.
+[ 3.100247] devtmpfs: initialized
+[ 3.100685] atomic64_test: passed
+[ 3.100727] regulator-dummy: no parameters
+[ 3.101141] NET: Registered protocol family 16
+[ 3.101262] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.101271] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.101633] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.101638] Serial: AMBA PL011 UART driver
+[ 3.101817] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.101850] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.102416] console [ttyAMA0] enabled
+[ 3.102495] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.102526] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.102557] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.102587] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130494] 3V3: 3300 mV
+[ 3.130534] vgaarb: loaded
+[ 3.130580] SCSI subsystem initialized
+[ 3.130617] libata version 3.00 loaded.
+[ 3.130659] usbcore: registered new interface driver usbfs
+[ 3.130676] usbcore: registered new interface driver hub
+[ 3.130707] usbcore: registered new device driver usb
+[ 3.130732] pps_core: LinuxPPS API ver. 1 registered
+[ 3.130740] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.130759] PTP clock support registered
+[ 3.130873] Switched to clocksource arch_sys_counter
+[ 3.131846] NET: Registered protocol family 2
+[ 3.131920] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.131938] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.131960] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.131975] TCP: reno registered
+[ 3.131982] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131997] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.132036] NET: Registered protocol family 1
+[ 3.132085] RPC: Registered named UNIX socket transport module.
+[ 3.132095] RPC: Registered udp transport module.
+[ 3.132103] RPC: Registered tcp transport module.
+[ 3.132111] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.132123] PCI: CLS 0 bytes, default 64
+[ 3.132266] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.132363] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.133901] fuse init (API version 7.23)
+[ 3.133978] msgmni has been set to 469
+[ 3.136097] io scheduler noop registered
+[ 3.136147] io scheduler cfq registered (default)
+[ 3.136516] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.136528] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.136540] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.136552] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.136562] pci_bus 0000:00: scanning bus
+[ 3.136573] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.136586] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.136600] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.136636] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.136647] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.136658] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.136669] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.136679] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.136690] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.136701] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.136734] pci_bus 0000:00: fixups for bus
+[ 3.136742] pci_bus 0000:00: bus scan returning with max=00
+[ 3.136755] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.136774] pci 0000:00:00.0: fixup irq: got 33
+[ 3.136782] pci 0000:00:00.0: assigning IRQ 33
+[ 3.136793] pci 0000:00:01.0: fixup irq: got 34
+[ 3.136801] pci 0000:00:01.0: assigning IRQ 34
+[ 3.136812] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.136825] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.136838] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.136851] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.136862] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.136874] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.136885] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.136896] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.137335] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.137572] ata_piix 0000:00:01.0: version 2.13
+[ 3.137583] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.137604] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.137866] scsi0 : ata_piix
+[ 3.137956] scsi1 : ata_piix
+[ 3.137984] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.137996] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.138093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.138105] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.138120] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.138131] e1000 0000:00:00.0: enabling bus mastering
+[ 3.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.290909] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.290935] ata1.00: configured for UDMA/33
+[ 3.290984] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.291086] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.291109] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.291146] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.291155] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.291174] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.291287] sda: sda1
+[ 3.291392] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.411166] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.411179] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.411199] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.411209] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.411240] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.411304] usbcore: registered new interface driver usb-storage
+[ 3.411354] mousedev: PS/2 mouse device common for all mice
+[ 3.411491] usbcore: registered new interface driver usbhid
+[ 3.411501] usbhid: USB HID core driver
+[ 3.411531] TCP: cubic registered
+[ 3.411538] NET: Registered protocol family 17
+ +[ 3.411900] devtmpfs: mounted
+[ 3.411930] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.450398] udevd[607]: starting version 182
+[ 3.450359] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.533417] random: dd urandom read with 19 bits of entropy available
+[ 3.543431] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -168,7 +168,7 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
-Configuring network interfaces... [ 3.661125] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+Configuring network interfaces... [ 3.671103] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
udhcpc (v1.21.1) started
Sending discover...
Sending discover...
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