diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
| commit | c87b717dbdf36f4b0ebef1df4592f1ebabad15a5 (patch) | |
| tree | e8dab9b58aef6394538af96fd1c7f1f2ffaf5775 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3 | |
| parent | 78dd152a0d5e55e26cd6c501dbc4f73e316937d9 (diff) | |
| download | gem5-c87b717dbdf36f4b0ebef1df4592f1ebabad15a5.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3')
4 files changed, 1622 insertions, 1606 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini index b9ad3e9e4..b4ce59a93 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -229,7 +229,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -723,7 +723,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -840,7 +840,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -885,7 +885,7 @@ size=1024 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -897,7 +897,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -929,29 +929,36 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -971,6 +978,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -980,7 +988,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1002,9 +1010,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1357,7 +1365,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -1670,10 +1678,11 @@ pio=system.iobus.master[21] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain -conf_table_reported=true +conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1681,7 +1690,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -1912,6 +1921,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1919,7 +1929,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout index 07f342b7e..34f117433 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12234 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:05:44 +gem5 executing on e108600-lin, pid 17601 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3 Selected 64-bit ARM architecture, updating default disk image... @@ -15,4 +15,4 @@ info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51327142820000 because m5_exit instruction encountered +Exiting @ tick 51558697863000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 7623e0029..2bd86426a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.558015 # Number of seconds simulated -sim_ticks 51558014828000 # Number of ticks simulated -final_tick 51558014828000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.558698 # Number of seconds simulated +sim_ticks 51558697863000 # Number of ticks simulated +final_tick 51558697863000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133865 # Simulator instruction rate (inst/s) -host_op_rate 157345 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6235119796 # Simulator tick rate (ticks/s) -host_mem_usage 696436 # Number of bytes of host memory used -host_seconds 8268.97 # Real time elapsed on the host -sim_insts 1106923026 # Number of instructions simulated -sim_ops 1301083589 # Number of ops (including micro ops) simulated +host_inst_rate 167711 # Simulator instruction rate (inst/s) +host_op_rate 197118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7760882097 # Simulator tick rate (ticks/s) +host_mem_usage 692228 # Number of bytes of host memory used +host_seconds 6643.41 # Real time elapsed on the host +sim_insts 1114173091 # Number of instructions simulated +sim_ops 1309536110 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 667968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 559488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 6546400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112650248 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 429376 # Number of bytes read from this memory -system.physmem.bytes_read::total 120853480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6546400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6546400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 140957120 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 691712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 570944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6573600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 114559048 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428096 # Number of bytes read from this memory +system.physmem.bytes_read::total 122823400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6573600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6573600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 143392768 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 140977700 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 10437 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 8742 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 118240 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1760173 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6709 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1904301 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2202455 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 143413348 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 10808 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8921 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 118665 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1789998 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6689 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1935081 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2240512 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2205028 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 12956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 10852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 126972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2184922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2344029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 126972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 126972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2733952 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 2243085 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 13416 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 11074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 127497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2221915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2382205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 127497 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 127497 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2781156 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2734351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2733952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 10852 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 126972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2185321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8328 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5078380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1904301 # Number of read requests accepted -system.physmem.writeReqs 2205028 # Number of write requests accepted -system.physmem.readBursts 1904301 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2205028 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 121838144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue -system.physmem.bytesWritten 140976896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 120853480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 140977700 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 2781555 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2781156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 13416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 11074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 127497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2222314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5163760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1935081 # Number of read requests accepted +system.physmem.writeReqs 2243085 # Number of write requests accepted +system.physmem.readBursts 1935081 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2243085 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 123796992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 48192 # Total number of bytes read from write queue +system.physmem.bytesWritten 143410368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 122823400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 143413348 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 753 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2282 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 114327 # Per bank write bursts -system.physmem.perBankRdBursts::1 123692 # Per bank write bursts -system.physmem.perBankRdBursts::2 118245 # Per bank write bursts -system.physmem.perBankRdBursts::3 117057 # Per bank write bursts -system.physmem.perBankRdBursts::4 115229 # Per bank write bursts -system.physmem.perBankRdBursts::5 125268 # Per bank write bursts -system.physmem.perBankRdBursts::6 115683 # Per bank write bursts -system.physmem.perBankRdBursts::7 119593 # Per bank write bursts -system.physmem.perBankRdBursts::8 115543 # Per bank write bursts -system.physmem.perBankRdBursts::9 144676 # Per bank write bursts -system.physmem.perBankRdBursts::10 112600 # Per bank write bursts -system.physmem.perBankRdBursts::11 120122 # Per bank write bursts -system.physmem.perBankRdBursts::12 113965 # Per bank write bursts -system.physmem.perBankRdBursts::13 118266 # Per bank write bursts -system.physmem.perBankRdBursts::14 113146 # Per bank write bursts -system.physmem.perBankRdBursts::15 116309 # Per bank write bursts -system.physmem.perBankWrBursts::0 135142 # Per bank write bursts -system.physmem.perBankWrBursts::1 141643 # Per bank write bursts -system.physmem.perBankWrBursts::2 136917 # Per bank write bursts -system.physmem.perBankWrBursts::3 137997 # Per bank write bursts -system.physmem.perBankWrBursts::4 135684 # Per bank write bursts -system.physmem.perBankWrBursts::5 143871 # Per bank write bursts -system.physmem.perBankWrBursts::6 135153 # Per bank write bursts -system.physmem.perBankWrBursts::7 138864 # Per bank write bursts -system.physmem.perBankWrBursts::8 135935 # Per bank write bursts -system.physmem.perBankWrBursts::9 142790 # Per bank write bursts -system.physmem.perBankWrBursts::10 134947 # Per bank write bursts -system.physmem.perBankWrBursts::11 140191 # Per bank write bursts -system.physmem.perBankWrBursts::12 134987 # Per bank write bursts -system.physmem.perBankWrBursts::13 137976 # Per bank write bursts -system.physmem.perBankWrBursts::14 134592 # Per bank write bursts -system.physmem.perBankWrBursts::15 136075 # Per bank write bursts +system.physmem.perBankRdBursts::0 114857 # Per bank write bursts +system.physmem.perBankRdBursts::1 123887 # Per bank write bursts +system.physmem.perBankRdBursts::2 121380 # Per bank write bursts +system.physmem.perBankRdBursts::3 115864 # Per bank write bursts +system.physmem.perBankRdBursts::4 115150 # Per bank write bursts +system.physmem.perBankRdBursts::5 124779 # Per bank write bursts +system.physmem.perBankRdBursts::6 116343 # Per bank write bursts +system.physmem.perBankRdBursts::7 120532 # Per bank write bursts +system.physmem.perBankRdBursts::8 117169 # Per bank write bursts +system.physmem.perBankRdBursts::9 147715 # Per bank write bursts +system.physmem.perBankRdBursts::10 116324 # Per bank write bursts +system.physmem.perBankRdBursts::11 125031 # Per bank write bursts +system.physmem.perBankRdBursts::12 116553 # Per bank write bursts +system.physmem.perBankRdBursts::13 122187 # Per bank write bursts +system.physmem.perBankRdBursts::14 118707 # Per bank write bursts +system.physmem.perBankRdBursts::15 117850 # Per bank write bursts +system.physmem.perBankWrBursts::0 135590 # Per bank write bursts +system.physmem.perBankWrBursts::1 141676 # Per bank write bursts +system.physmem.perBankWrBursts::2 140587 # Per bank write bursts +system.physmem.perBankWrBursts::3 138605 # Per bank write bursts +system.physmem.perBankWrBursts::4 137623 # Per bank write bursts +system.physmem.perBankWrBursts::5 144276 # Per bank write bursts +system.physmem.perBankWrBursts::6 136529 # Per bank write bursts +system.physmem.perBankWrBursts::7 140386 # Per bank write bursts +system.physmem.perBankWrBursts::8 138327 # Per bank write bursts +system.physmem.perBankWrBursts::9 145050 # Per bank write bursts +system.physmem.perBankWrBursts::10 137213 # Per bank write bursts +system.physmem.perBankWrBursts::11 144076 # Per bank write bursts +system.physmem.perBankWrBursts::12 138694 # Per bank write bursts +system.physmem.perBankWrBursts::13 142077 # Per bank write bursts +system.physmem.perBankWrBursts::14 140963 # Per bank write bursts +system.physmem.perBankWrBursts::15 139115 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 125 # Number of times write queue was full causing retry -system.physmem.totGap 51558013451500 # Total gap between requests +system.physmem.numWrRetry 498 # Number of times write queue was full causing retry +system.physmem.totGap 51558696478500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1883016 # Read request sizes (log2) +system.physmem.readPktSize::6 1913796 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2202455 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1140639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 689076 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 609 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 126 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2240512 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1142122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 697940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 62817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 132 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 107 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,170 +160,167 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 38490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 83702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 117171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 125843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 130438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 133004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 138248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 140822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 137539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 142466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 143357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 133954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 146358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 136372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 127299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 130102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 120942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 365 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 933198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 281.628105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.352526 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.404332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 371108 39.77% 39.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 233427 25.01% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88383 9.47% 74.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 51664 5.54% 79.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 37413 4.01% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 26389 2.83% 86.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21045 2.26% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17945 1.92% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 85824 9.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 933198 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 116229 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.379053 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 52.340079 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 116223 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 28657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 36011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 84715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 118224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 127097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 131612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 133869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 139104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 141132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 137785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 140939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 143104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 134560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 133279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 134737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 146876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 129080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 132587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1141 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 951139 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 280.933676 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.585937 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.458614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 376624 39.60% 39.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 238014 25.02% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 91172 9.59% 74.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 53576 5.63% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 39458 4.15% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 27371 2.88% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21519 2.26% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17750 1.87% 90.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 85655 9.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 951139 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 118362 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.342416 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 51.876252 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 118357 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 116229 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 116228 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.951965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.478061 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.079115 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 111884 96.26% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 1770 1.52% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 397 0.34% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 626 0.54% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 488 0.42% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 246 0.21% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 362 0.31% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 120 0.10% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 64 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 59 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 51 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 11 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 17 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 10 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 37 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 24 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 14 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 5 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-623 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::624-639 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::752-767 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::976-991 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 116228 # Writes before turning the bus around for reads -system.physmem.totQLat 42075497859 # Total ticks spent queuing -system.physmem.totMemAccLat 77770266609 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9518605000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22101.71 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 118362 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 118362 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.931642 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.417353 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.979781 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 114164 96.45% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 1862 1.57% 98.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 1234 1.04% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 621 0.52% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 196 0.17% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 102 0.09% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 42 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 35 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 40 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 18 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 4 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 11 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 7 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-799 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-895 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1024-1055 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 118362 # Writes before turning the bus around for reads +system.physmem.totQLat 71570448504 # Total ticks spent queuing +system.physmem.totMemAccLat 107839098504 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9671640000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37000.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40851.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.73 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 55750.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing -system.physmem.readRowHits 1533744 # Number of row buffer hits during reads -system.physmem.writeRowHits 1639539 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes -system.physmem.avgGap 12546577.18 # Average gap between requests -system.physmem.pageHitRate 77.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3530119320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1926156375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7402894200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 7162084800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1313077918185 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29782982922000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34483600624320 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.831109 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49545451951432 # Time in different power states -system.physmem_0.memoryStateTime::REF 1721635240000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 290927248568 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3524804640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1923256500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7446082800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 7111728720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1314046606680 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29782133195250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34483704204030 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.833118 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49544014933949 # Time in different power states -system.physmem_1.memoryStateTime::REF 1721635240000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 292364518051 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.69 # Average write queue length when enqueuing +system.physmem.readRowHits 1560611 # Number of row buffer hits during reads +system.physmem.writeRowHits 1663363 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.23 # Row buffer hit rate for writes +system.physmem.avgGap 12340030.64 # Average gap between requests +system.physmem.pageHitRate 77.22 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3363189900 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1787570235 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6802934880 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5821719840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 51899586960.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 51612190140 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3200334720 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 101759183310 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 76295730720 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12252381205680 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12554961718635 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.508122 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51437094541003 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 5396479999 # Time in different power states +system.physmem_0.memoryStateTime::REF 22052840000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51015251458000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 198686963242 # Time in different power states +system.physmem_0.memoryStateTime::ACT 94153955748 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 223156166011 # Time in different power states +system.physmem_1.actEnergy 3427956840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1822002270 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7008167040 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5875188300 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 53218604400.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 52383682290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3161186880 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 106497624090 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 77662512480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12248740584255 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12559836053265 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.602662 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51435493097538 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5216830750 # Time in different power states +system.physmem_1.memoryStateTime::REF 22612324000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 50999709861500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 202245988185 # Time in different power states +system.physmem_1.memoryStateTime::ACT 95365744212 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 233547114353 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -340,30 +337,30 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 290131106 # Number of BP lookups -system.cpu.branchPred.condPredicted 198353835 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13679752 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 208494226 # Number of BTB lookups -system.cpu.branchPred.BTBHits 130534623 # Number of BTB hits +system.cpu.branchPred.lookups 292003156 # Number of BP lookups +system.cpu.branchPred.condPredicted 199825428 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13707860 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 209782047 # Number of BTB lookups +system.cpu.branchPred.BTBHits 131422635 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.608268 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 37597374 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 402079 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 8125236 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6045082 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2080154 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 800698 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 62.647227 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37743675 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 403344 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 8164760 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6089475 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2075285 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 798713 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -393,88 +390,90 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 1423094 # Table walker walks requested -system.cpu.dtb.walker.walksLong 1423094 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30587 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273540 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 668841 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 754253 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2502.822660 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 16371.142747 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 747574 99.11% 99.11% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 4739 0.63% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 871 0.12% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 433 0.06% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 327 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 64 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 235 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 754253 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 795185 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 25800.017606 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21033.129871 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 18337.040091 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 776690 97.67% 97.67% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 15553 1.96% 99.63% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1840 0.23% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 320 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 153 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 44 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 795185 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 1040609044948 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.747004 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.517062 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 1036648437448 99.62% 99.62% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 2501393000 0.24% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 710900000 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 286069000 0.03% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 201203000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 121106500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 48982500 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 87667500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 3189000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::18-19 41500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::20-21 55500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 1040609044948 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 273541 89.94% 89.94% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 30587 10.06% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 304128 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1423094 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 1433016 # Table walker walks requested +system.cpu.dtb.walker.walksLong 1433016 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 32195 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277777 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 671696 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 761320 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2826.976830 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 21785.764506 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 754204 99.07% 99.07% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 4652 0.61% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 981 0.13% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 445 0.06% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 347 0.05% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 34 0.00% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 244 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 36 0.00% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 13 0.00% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 353 0.05% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::655360-720895 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::917504-983039 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 761320 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 803371 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 26077.733077 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21137.704877 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20668.738137 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-131071 799705 99.54% 99.54% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-262143 2825 0.35% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-393215 589 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-524287 118 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-655359 123 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-786431 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::786432-917503 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::1.17965e+06-1.31072e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 803371 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1075651264316 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.736998 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.521821 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 1071482592816 99.61% 99.61% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 2636080000 0.25% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 763976000 0.07% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 297116500 0.03% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 205516000 0.02% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 123566500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 47691000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 91565500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 3134000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::20-21 23000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1075651264316 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 277778 89.61% 89.61% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 32195 10.39% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 309973 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1433016 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1423094 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304128 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1433016 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309973 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304128 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1727222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309973 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1742989 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 217549636 # DTB read hits -system.cpu.dtb.read_misses 1002675 # DTB read misses -system.cpu.dtb.write_hits 192429615 # DTB write hits -system.cpu.dtb.write_misses 420419 # DTB write misses +system.cpu.dtb.read_hits 218874380 # DTB read hits +system.cpu.dtb.read_misses 1009020 # DTB read misses +system.cpu.dtb.write_hits 193682033 # DTB write hits +system.cpu.dtb.write_misses 423996 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 84838 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 16158 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 89021 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 108 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 17262 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 86326 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 218552311 # DTB read accesses -system.cpu.dtb.write_accesses 192850034 # DTB write accesses +system.cpu.dtb.perms_faults 85593 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 219883400 # DTB read accesses +system.cpu.dtb.write_accesses 194106029 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 409979251 # DTB hits -system.cpu.dtb.misses 1423094 # DTB misses -system.cpu.dtb.accesses 411402345 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 412556413 # DTB hits +system.cpu.dtb.misses 1433016 # DTB misses +system.cpu.dtb.accesses 413989429 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -504,231 +503,234 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 177767 # Table walker walks requested -system.cpu.itb.walker.walksLong 177767 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1532 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 128663 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 19966 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 157801 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1393.783943 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9971.559116 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 155663 98.65% 98.65% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 1042 0.66% 99.31% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 672 0.43% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 333 0.21% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 30 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 157801 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 150161 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28501.914612 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23015.105793 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 23459.229673 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 144112 95.97% 95.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 5152 3.43% 99.40% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 475 0.32% 99.72% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 255 0.17% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 99 0.07% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 55 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 150161 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 911756921068 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.951043 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.216068 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 44693483152 4.90% 4.90% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 867007398416 95.09% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 55571500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 466000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 911756921068 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 128663 98.82% 98.82% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1532 1.18% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 130195 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 178466 # Table walker walks requested +system.cpu.itb.walker.walksLong 178466 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1508 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 129505 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 20095 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 158371 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1754.443680 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 17709.281636 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-65535 157140 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-131071 1047 0.66% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-196607 42 0.03% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-262143 30 0.02% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-327679 14 0.01% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-393215 7 0.00% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-458751 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::524288-589823 40 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::589824-655359 48 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 158371 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 151108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29265.005824 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23190.077140 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 30431.733671 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 145001 95.96% 95.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 5046 3.34% 99.30% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 391 0.26% 99.56% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 366 0.24% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 100 0.07% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 51 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 8 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 85 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 8 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::720896-786431 24 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::983040-1.04858e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 151108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 912439402568 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.949255 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.219812 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 46367810152 5.08% 5.08% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 866006867916 94.91% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 63907500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 568000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 249000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 912439402568 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 129505 98.85% 98.85% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1508 1.15% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 131013 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177767 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 177767 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178466 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 178466 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130195 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 130195 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 307962 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 462600046 # ITB inst hits -system.cpu.itb.inst_misses 177767 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 131013 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 131013 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 309479 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 465485773 # ITB inst hits +system.cpu.itb.inst_misses 178466 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 58185 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 62647 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 440221 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 443320 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 462777813 # ITB inst accesses -system.cpu.itb.hits 462600046 # DTB hits -system.cpu.itb.misses 177767 # DTB misses -system.cpu.itb.accesses 462777813 # DTB accesses -system.cpu.numPwrStateTransitions 34262 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 17131 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 2947433272.666569 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 58590018858.186401 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7811 45.60% 45.60% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9284 54.19% 99.79% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 465664239 # ITB inst accesses +system.cpu.itb.hits 465485773 # DTB hits +system.cpu.itb.misses 178466 # DTB misses +system.cpu.itb.accesses 465664239 # DTB accesses +system.cpu.numPwrStateTransitions 34324 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 17162 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 2940404395.507225 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 58760863847.973442 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7839 45.68% 45.68% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9288 54.12% 99.80% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::overflows 18 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 17131 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1065535433949 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50492479394051 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2131080190 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988780801904 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 17162 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1095477627305 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50463220235695 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2190964579 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 789533395 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1294232501 # Number of instructions fetch has processed -system.cpu.fetch.Branches 290131106 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174177079 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1253396684 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29442936 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4521296 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28032 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11449142 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1221670 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 685 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 462141962 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6901101 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 52491 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 2074872372 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.731015 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.142682 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 794033282 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1302230220 # Number of instructions fetch has processed +system.cpu.fetch.Branches 292003156 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 175255785 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1304336456 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29502488 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4651258 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 26755 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11711903 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1225327 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 1089 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 465024484 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6899822 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 52313 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2130737314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.716190 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.134027 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1354023092 65.26% 65.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 279633538 13.48% 78.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 86518146 4.17% 82.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 354697596 17.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1403414987 65.87% 65.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 283475853 13.30% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 89003023 4.18% 83.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 354843451 16.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2074872372 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.136143 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.607313 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 615922756 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 835719938 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 532432043 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 80077312 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10720323 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 41258933 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4059445 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1407827153 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 33008479 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10720323 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 679035070 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 79966926 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 552687037 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 549603762 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 202859254 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1383638167 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 8109162 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7348509 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 966276 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1094350 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 119568064 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 22725 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1333397174 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2200696007 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1641425227 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1433031 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1254726296 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78670875 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 43643507 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39180007 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 166278031 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 222554034 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 196867138 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12635283 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11114743 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1330840515 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 43953891 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1360477402 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4212137 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 73710813 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41934009 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 368799 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 2074872372 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.655692 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.916068 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 2130737314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.133276 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.594364 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 615599644 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 888388322 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542818505 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 73189293 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10741550 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41458105 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4067803 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1416661162 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 33069720 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10741550 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 678370602 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 94749069 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 569457122 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 557397759 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 220021212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1392357267 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 8139910 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7467928 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 990269 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1135391 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 140197147 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 22858 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1342242693 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2216016664 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1651872272 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1433815 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1263306379 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 78936311 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44081382 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39609601 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160762582 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 223936207 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 198122558 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12861166 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11120462 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1339067750 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 44403277 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1369076757 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4228585 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 73934913 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 42101353 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 368543 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2130737314 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.642537 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.913709 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 1226409345 59.11% 59.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 451307165 21.75% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 291780533 14.06% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 95920964 4.62% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9425546 0.45% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 28819 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1278640571 60.01% 60.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 452467629 21.24% 81.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 292658965 13.74% 94.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96618652 4.53% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10322243 0.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29254 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 2074872372 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2130737314 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 73561900 34.17% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 90692 0.04% 34.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26794 0.01% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 484 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 57931960 26.91% 61.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 83660297 38.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 74049078 33.84% 33.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90108 0.04% 33.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26756 0.01% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 482 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 59033401 26.97% 60.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 85651168 39.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 939889673 69.09% 69.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2936613 0.22% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 130878 0.01% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 55 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 945875031 69.09% 69.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2941932 0.21% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 129428 0.01% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.31% # Type of FU issued @@ -751,100 +753,100 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.31% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 112363 0.01% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 112221 0.01% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 222587367 16.36% 85.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194820033 14.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 223931934 16.36% 85.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 196085738 14.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1360477402 # Type of FU issued -system.cpu.iq.rate 0.638398 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215272127 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.158233 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5012901497 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1447776434 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1338315649 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2409942 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 914537 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 885572 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1574233532 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1515940 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5717597 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1369076757 # Type of FU issued +system.cpu.iq.rate 0.624874 # Inst issue rate +system.cpu.iq.fu_busy_cnt 218850993 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.159853 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5089559021 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1456673430 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1346855595 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2411384 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 915419 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 886368 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1586411072 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1516623 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5720273 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17343387 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24124 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 187368 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7978529 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17413416 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22608 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 184689 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8002869 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3596780 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1680866 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3613750 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2051788 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10720323 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12040487 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4569260 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1375079942 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 10741550 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13180703 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5272349 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1383757283 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 222554034 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 196867138 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 38644291 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 177419 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4207009 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 187368 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4048268 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6103351 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10151619 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1346834094 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 217554512 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12249639 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 223936207 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 198122558 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39070088 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 183909 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4898355 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 184689 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4057329 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6115164 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10172493 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1355379185 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 218880930 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12294353 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 285536 # number of nop insts executed -system.cpu.iew.exec_refs 409993947 # number of memory reference insts executed -system.cpu.iew.exec_branches 255680172 # Number of branches executed -system.cpu.iew.exec_stores 192439435 # Number of stores executed -system.cpu.iew.exec_rate 0.631996 # Inst execution rate -system.cpu.iew.wb_sent 1340240150 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1339201221 # cumulative count of insts written-back -system.cpu.iew.wb_producers 574929948 # num instructions producing a value -system.cpu.iew.wb_consumers 943031378 # num instructions consuming a value -system.cpu.iew.wb_rate 0.628414 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.609662 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 62850702 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 43585092 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9678607 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 2060674246 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.631387 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.270689 # Number of insts commited each cycle +system.cpu.iew.exec_nop 286256 # number of nop insts executed +system.cpu.iew.exec_refs 412572980 # number of memory reference insts executed +system.cpu.iew.exec_branches 257403074 # Number of branches executed +system.cpu.iew.exec_stores 193692050 # Number of stores executed +system.cpu.iew.exec_rate 0.618622 # Inst execution rate +system.cpu.iew.wb_sent 1348783541 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1347741963 # cumulative count of insts written-back +system.cpu.iew.wb_producers 576070929 # num instructions producing a value +system.cpu.iew.wb_consumers 948341211 # num instructions consuming a value +system.cpu.iew.wb_rate 0.615136 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.607451 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 63015193 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 44034734 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9698166 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2116507295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.618725 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.263721 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1383412740 67.13% 67.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 394991247 19.17% 86.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 150433823 7.30% 93.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 44582057 2.16% 95.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36156812 1.75% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18175173 0.88% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10964042 0.53% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5475656 0.27% 99.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16482696 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1435626131 67.83% 67.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 397528537 18.78% 86.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 150810671 7.13% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44606790 2.11% 95.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36101901 1.71% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18021060 0.85% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 11293216 0.53% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5858251 0.28% 99.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16660738 0.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 2060674246 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1106923026 # Number of instructions committed -system.cpu.commit.committedOps 1301083589 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 2116507295 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1114173091 # Number of instructions committed +system.cpu.commit.committedOps 1309536110 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 394099255 # Number of memory references committed -system.cpu.commit.loads 205210646 # Number of loads committed -system.cpu.commit.membars 9122435 # Number of memory barriers committed -system.cpu.commit.branches 247396089 # Number of branches committed -system.cpu.commit.fp_insts 873905 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1189215854 # Number of committed integer instructions. -system.cpu.commit.function_calls 30973786 # Number of function calls committed. +system.cpu.commit.refs 396642479 # Number of memory references committed +system.cpu.commit.loads 206522790 # Number of loads committed +system.cpu.commit.membars 9192719 # Number of memory barriers committed +system.cpu.commit.branches 249090207 # Number of branches committed +system.cpu.commit.fp_insts 874521 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1196753296 # Number of committed integer instructions. +system.cpu.commit.function_calls 31104441 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 904226715 69.50% 69.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2546778 0.20% 69.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 104952 0.01% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 910131481 69.50% 69.50% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2552727 0.19% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 103687 0.01% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction @@ -867,577 +869,581 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 105847 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 105694 0.01% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 205210646 15.77% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 188888609 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 206522790 15.77% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 190119689 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1301083589 # Class of committed instruction -system.cpu.commit.bw_lim_events 16482696 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3398675710 # The number of ROB reads -system.cpu.rob.rob_writes 2741957858 # The number of ROB writes -system.cpu.timesIdled 9058128 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 56207818 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100984949503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 1106923026 # Number of Instructions Simulated -system.cpu.committedOps 1301083589 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.925229 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.925229 # CPI: Total CPI of All Threads -system.cpu.ipc 0.519419 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.519419 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1599627417 # number of integer regfile reads -system.cpu.int_regfile_writes 942915680 # number of integer regfile writes -system.cpu.fp_regfile_reads 1421408 # number of floating regfile reads -system.cpu.fp_regfile_writes 762380 # number of floating regfile writes -system.cpu.cc_regfile_reads 312164706 # number of cc regfile reads -system.cpu.cc_regfile_writes 313034766 # number of cc regfile writes -system.cpu.misc_regfile_reads 3414318389 # number of misc regfile reads -system.cpu.misc_regfile_writes 44468731 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 13662519 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.983620 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 361203380 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 13663031 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 26.436548 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1659288500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.983620 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 1309536110 # Class of committed instruction +system.cpu.commit.bw_lim_events 16660738 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3462896243 # The number of ROB reads +system.cpu.rob.rob_writes 2759222856 # The number of ROB writes +system.cpu.timesIdled 9103079 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 60227265 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100926431181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1114173091 # Number of Instructions Simulated +system.cpu.committedOps 1309536110 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.966449 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.966449 # CPI: Total CPI of All Threads +system.cpu.ipc 0.508531 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.508531 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1609897597 # number of integer regfile reads +system.cpu.int_regfile_writes 948614350 # number of integer regfile writes +system.cpu.fp_regfile_reads 1422281 # number of floating regfile reads +system.cpu.fp_regfile_writes 763660 # number of floating regfile writes +system.cpu.cc_regfile_reads 314738541 # number of cc regfile reads +system.cpu.cc_regfile_writes 315610902 # number of cc regfile writes +system.cpu.misc_regfile_reads 3478507383 # number of misc regfile reads +system.cpu.misc_regfile_writes 44953668 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 13773933 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.982218 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 363424605 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 13774445 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.383974 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1801582500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.982218 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1599492126 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1599492126 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 186946586 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 186946586 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 163344159 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 163344159 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 463383 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 463383 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 333988 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 333988 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4793284 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4793284 # 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miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16095.314606 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16095.314606 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53809.325082 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53809.325082 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23587.956296 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23587.956296 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16291.062223 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16291.062223 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33388.888889 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33388.888889 # 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number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 464298 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 464298 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 335039 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 335039 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4843113 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4843113 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5333928 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5333928 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 352739883 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 352739883 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 353204181 # number of overall hits +system.cpu.dcache.overall_hits::total 353204181 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12867394 # 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average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17065.107428 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17065.107428 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35812.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35812.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41506.907075 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41506.907075 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39063.630967 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39063.630967 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29294390 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2093623 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2113869 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.663969 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.858186 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 10319802 # number of writebacks -system.cpu.dcache.writebacks::total 10319802 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5736139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5736139 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15576096 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15576096 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6849 # 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number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 2034687 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263657 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1263657 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283363 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 283363 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 9 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 11387999 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 11387999 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 13422686 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 13422686 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 10422476 # number of writebacks +system.cpu.dcache.writebacks::total 10422476 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5755479 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5755479 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15769683 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15769683 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6881 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 6881 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 266620 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 266620 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 21532043 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21532043 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21532043 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21532043 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7111915 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7111915 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3098529 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3098529 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2057605 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2057605 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263830 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1263830 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 285936 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 285936 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 11474274 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 11474274 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 13531879 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 13531879 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110827450000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 110827450000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 147154305213 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 147154305213 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32559356000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32559356000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28426038502 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28426038502 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4117736500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4117736500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 291500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 291500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286407793715 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 286407793715 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318967149715 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 318967149715 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225596500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225596500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225596500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225596500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035306 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035306 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016882 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016882 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.812301 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.812301 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787574 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787574 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053048 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053048 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029708 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029708 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15715.921135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15715.921135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47895.243884 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47895.243884 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16002.144802 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16002.144802 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22495.058787 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22495.058787 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14531.666096 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14531.666096 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32388.888889 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32388.888889 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25149.966532 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25149.966532 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23763.287744 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23763.287744 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184779.665796 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184779.665796 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92374.753320 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92374.753320 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16891256 # number of replacements -system.cpu.icache.tags.tagsinuse 511.956016 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 444441322 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16891768 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26.311119 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13164566500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.956016 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999914 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999914 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 120215948500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 120215948500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 164231979720 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 164231979720 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 35080858000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 35080858000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28539216720 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28539216720 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4259524000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4259524000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 278500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 278500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 312987144940 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 312987144940 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 348068002940 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 348068002940 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225685500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225685500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225685500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225685500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035387 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035387 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016916 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016916 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813697 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813697 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787065 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787065 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052994 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052994 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029746 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029746 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034851 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034851 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16903.456875 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16903.456875 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53003.208852 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53003.208852 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17049.364674 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17049.364674 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22581.531314 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22581.531314 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14896.774103 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14896.774103 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34812.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34812.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27277.293966 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27277.293966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25722.074735 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25722.074735 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184782.307373 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184782.307373 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92376.073893 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92376.073893 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 16962264 # number of replacements +system.cpu.icache.tags.tagsinuse 511.953467 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 447249112 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16962776 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26.366505 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13767456500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.953467 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 112 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 479012658 # Number of tag accesses -system.cpu.icache.tags.data_accesses 479012658 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 444441322 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 444441322 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 444441322 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 444441322 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 444441322 # number of overall hits -system.cpu.icache.overall_hits::total 444441322 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17679342 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17679342 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17679342 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17679342 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17679342 # number of overall misses -system.cpu.icache.overall_misses::total 17679342 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 234300237389 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 234300237389 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 234300237389 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 234300237389 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 234300237389 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 234300237389 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 462120664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 462120664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 462120664 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 462120664 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 462120664 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 462120664 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038257 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.038257 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.038257 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.038257 # 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Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 447249112 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 447249112 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 447249112 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 447249112 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 447249112 # number of overall hits +system.cpu.icache.overall_hits::total 447249112 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17754074 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17754074 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17754074 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17754074 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17754074 # number of overall misses +system.cpu.icache.overall_misses::total 17754074 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 238230546873 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6628.882550 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 49005.730985 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.143400 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.002999 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.003482 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101149 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.747768 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998799 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 222 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62867 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 222 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55850 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959274 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 505094110 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 505094110 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1274032 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 302472 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6670.865899 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48531.996533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.143952 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005881 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006355 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101789 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.740539 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 284 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 61860 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 284 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1041 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5649 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54812 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.943909 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 508249108 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 508249108 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1295823 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 305430 # 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mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045756 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045756 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.466977 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.466977 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060787 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060787 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79519.552688 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19090.240314 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19090.240314 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82894.958867 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82894.958867 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75598.356935 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75598.356935 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80471.401186 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80471.401186 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.901693 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.901693 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172274.946575 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130011.912123 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86123.414200 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 80605.655718 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 62084255 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 31529230 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3455 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.092878 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.092878 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437237 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437237 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005743 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.047479 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.047479 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.471162 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.471162 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061372 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061372 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 115042.931725 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19076.732059 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19076.732059 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45625 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45625 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94799.663632 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94799.663632 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100703.051484 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100703.051484 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 101451.929412 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 101451.929412 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20684.448732 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20684.448732 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100703.051484 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96464.053153 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96872.506072 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100703.051484 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96464.053153 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96872.506072 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.469429 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.842324 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.675421 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.038077 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 62444778 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 31707340 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2080 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2080 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 2242102 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 28488845 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 2265526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28668320 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 12415627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16891256 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3619797 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43003 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43012 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3045422 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3045422 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 16891994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 9356331 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1295806 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1263657 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50717623 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41210208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 777423 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3005376 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 95710630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2162455328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1454268658 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2489712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10275752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3629489450 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2999840 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 138927432 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 35281285 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.026592 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.160887 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 12556358 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16962264 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3627230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43361 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3071629 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3071629 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 16963000 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 9441368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1296315 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1263830 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50930633 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41545171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 782892 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3048631 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 96307327 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171543584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467959922 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2514816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10453048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3652471370 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 3035082 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 141349672 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 35524572 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.026277 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.159958 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 34343098 97.34% 97.34% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 938187 2.66% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 34591090 97.37% 97.37% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 933482 2.63% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 35281285 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 58941748976 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 35524572 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 59309730487 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1470395 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1500879 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25369728010 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25476019939 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 19308156079 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 19475244130 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 466604190 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 468898263 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1721722349 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1742663628 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40300 # Transaction distribution -system.iobus.trans_dist::ReadResp 40300 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40311 # Transaction distribution +system.iobus.trans_dist::ReadResp 40311 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1612,11 +1618,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230980 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353742 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1631,16 +1637,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334352 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334352 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492184 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41887500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41893500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 337000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 344000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1654,79 +1660,79 @@ system.iobus.reqLayer14.occupancy 9500 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25106500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25183500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36499000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568968673 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569168088 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147718000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115465 # number of replacements -system.iocache.tags.tagsinuse 10.450543 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115471 # number of replacements +system.iocache.tags.tagsinuse 10.450359 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115487 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13091229344000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.877255 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.573288 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.367328 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.285830 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653159 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13091904207000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.527977 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.922382 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220499 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432649 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653147 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039668 # Number of tag accesses -system.iocache.tags.data_accesses 1039668 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039767 # Number of tag accesses +system.iocache.tags.data_accesses 1039767 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8826 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8863 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115479 # number of demand (read+write) misses -system.iocache.demand_misses::total 115519 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115490 # number of demand (read+write) misses +system.iocache.demand_misses::total 115530 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115479 # number of overall misses -system.iocache.overall_misses::total 115519 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1629675592 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1634761592 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115490 # number of overall misses +system.iocache.overall_misses::total 115530 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1926111562 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1931197062 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12811525081 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12811525081 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14441200673 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14446637673 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14441200673 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14446637673 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13315765026 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13315765026 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15241876588 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15247313088 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15241876588 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15247313088 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8826 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8863 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115479 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115519 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115490 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115530 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115479 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115519 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115490 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115530 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1740,53 +1746,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184875.279864 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 184677.089019 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 218231.538862 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 217894.286585 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120111.050411 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120111.050411 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125058.541651 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125058.541651 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32070 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124838.418079 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 124838.418079 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131977.088964 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131977.088964 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 47583 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.390922 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.760266 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8826 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8863 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115479 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115519 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115490 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115530 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115479 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115519 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1188925592 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1192161592 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115490 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115530 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1484811562 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1488047062 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7471582182 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7471582182 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8660507774 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8663944774 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8660507774 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8663944774 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7975666597 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7975666597 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9460478159 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9463914659 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9460478159 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9463914659 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1800,95 +1806,95 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134875.279864 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 134677.089019 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168231.538862 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 167894.286585 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70047.834152 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70047.834152 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 5074419 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2524015 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3002 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74773.743690 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74773.743690 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 5147706 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2561464 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3010 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54986 # Transaction distribution -system.membus.trans_dist::ReadResp 608005 # Transaction distribution +system.membus.trans_dist::ReadResp 629139 # Transaction distribution system.membus.trans_dist::WriteReq 33703 # Transaction distribution system.membus.trans_dist::WriteResp 33703 # Transaction distribution -system.membus.trans_dist::WritebackDirty 2202455 # Transaction distribution -system.membus.trans_dist::CleanEvict 284620 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4643 # Transaction distribution +system.membus.trans_dist::WritebackDirty 2240512 # Transaction distribution +system.membus.trans_dist::CleanEvict 283345 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 1332798 # Transaction distribution -system.membus.trans_dist::ReadExResp 1332798 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 553019 # Transaction distribution -system.membus.trans_dist::InvalidateReq 696755 # Transaction distribution +system.membus.trans_dist::ReadExReq 1342476 # Transaction distribution +system.membus.trans_dist::ReadExResp 1342476 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 574153 # Transaction distribution +system.membus.trans_dist::InvalidateReq 702122 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6767333 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6896995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237693 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237693 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7134688 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6871030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7000692 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237690 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237690 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7238382 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254577484 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254747538 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7253696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 262001234 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2809 # Total snoops (count) -system.membus.snoopTraffic 179264 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2675908 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013150 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.113918 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 258984332 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 259154386 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7252416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7252416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 266406802 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2841 # Total snoops (count) +system.membus.snoopTraffic 181312 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2712040 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013104 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.113719 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2640719 98.68% 98.68% # Request fanout histogram -system.membus.snoop_fanout::1 35189 1.32% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2676502 98.69% 98.69% # Request fanout histogram +system.membus.snoop_fanout::1 35538 1.31% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2675908 # Request fanout histogram -system.membus.reqLayer0.occupancy 103923000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2712040 # Request fanout histogram +system.membus.reqLayer0.occupancy 104012000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5620000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5608000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 14223305475 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 14521699612 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10050154677 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 10216122095 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44814659 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44869281 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1931,30 +1937,30 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 17131 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 17162 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal index 3c0eb417b..b157c1f08 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal @@ -31,136 +31,136 @@ [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
-[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000021] Console: colour dummy device 80x25
-[ 0.000024] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000025] pid_max: default: 32768 minimum: 301
-[ 0.000036] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000037] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000147] hw perfevents: no hardware support available
-[ 1.060066] CPU1: failed to come online
-[ 2.080127] CPU2: failed to come online
+[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[ 0.000019] Console: colour dummy device 80x25
+[ 0.000021] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000022] pid_max: default: 32768 minimum: 301
+[ 0.000032] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000033] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000120] hw perfevents: no hardware support available
+[ 1.060065] CPU1: failed to come online
+[ 2.080126] CPU2: failed to come online
[ 3.100188] CPU3: failed to come online
-[ 3.100191] Brought up 1 CPUs
-[ 3.100192] SMP: Total of 1 processors activated.
-[ 3.100247] devtmpfs: initialized
-[ 3.100685] atomic64_test: passed
-[ 3.100727] regulator-dummy: no parameters
-[ 3.101141] NET: Registered protocol family 16
-[ 3.101262] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.101271] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.101633] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.101638] Serial: AMBA PL011 UART driver
-[ 3.101817] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.101850] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.102416] console [ttyAMA0] enabled
-[ 3.102495] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.102526] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.102557] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.102587] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130494] 3V3: 3300 mV
-[ 3.130534] vgaarb: loaded
-[ 3.130580] SCSI subsystem initialized
-[ 3.130617] libata version 3.00 loaded.
-[ 3.130659] usbcore: registered new interface driver usbfs
-[ 3.130676] usbcore: registered new interface driver hub
-[ 3.130707] usbcore: registered new device driver usb
-[ 3.130732] pps_core: LinuxPPS API ver. 1 registered
-[ 3.130740] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.130759] PTP clock support registered
-[ 3.130873] Switched to clocksource arch_sys_counter
-[ 3.131846] NET: Registered protocol family 2
-[ 3.131920] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.131938] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.131960] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.131975] TCP: reno registered
-[ 3.131982] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.131997] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132036] NET: Registered protocol family 1
-[ 3.132085] RPC: Registered named UNIX socket transport module.
-[ 3.132095] RPC: Registered udp transport module.
-[ 3.132103] RPC: Registered tcp transport module.
-[ 3.132111] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.132123] PCI: CLS 0 bytes, default 64
-[ 3.132266] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.132363] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.133901] fuse init (API version 7.23)
-[ 3.133978] msgmni has been set to 469
-[ 3.136097] io scheduler noop registered
-[ 3.136147] io scheduler cfq registered (default)
-[ 3.136516] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.136528] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.136540] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.136552] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.136562] pci_bus 0000:00: scanning bus
-[ 3.136573] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.136586] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.136600] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136636] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.136647] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.136658] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.136669] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.136679] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.136690] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.136701] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136734] pci_bus 0000:00: fixups for bus
-[ 3.136742] pci_bus 0000:00: bus scan returning with max=00
-[ 3.136755] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.136774] pci 0000:00:00.0: fixup irq: got 33
-[ 3.136782] pci 0000:00:00.0: assigning IRQ 33
-[ 3.136793] pci 0000:00:01.0: fixup irq: got 34
-[ 3.136801] pci 0000:00:01.0: assigning IRQ 34
-[ 3.136812] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.136825] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.136838] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.136851] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.136862] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.136874] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.136885] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.136896] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.137335] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.137572] ata_piix 0000:00:01.0: version 2.13
-[ 3.137583] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.137604] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.137866] scsi0 : ata_piix
-[ 3.137956] scsi1 : ata_piix
-[ 3.137984] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.137996] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.138093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.138105] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.138120] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.138131] e1000 0000:00:00.0: enabling bus mastering
-[ 3.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.290909] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.290935] ata1.00: configured for UDMA/33
-[ 3.290984] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.291086] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.291109] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.291146] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.291155] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.291174] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.291287] sda: sda1
-[ 3.291392] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.411166] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.411179] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.411199] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.411209] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.411240] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.411304] usbcore: registered new interface driver usb-storage
-[ 3.411354] mousedev: PS/2 mouse device common for all mice
-[ 3.411491] usbcore: registered new interface driver usbhid
-[ 3.411501] usbhid: USB HID core driver
-[ 3.411531] TCP: cubic registered
-[ 3.411538] NET: Registered protocol family 17
- -[ 3.411900] devtmpfs: mounted
-[ 3.411930] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 3.100190] Brought up 1 CPUs
+[ 3.100191] SMP: Total of 1 processors activated.
+[ 3.100238] devtmpfs: initialized
+[ 3.100663] atomic64_test: passed
+[ 3.100701] regulator-dummy: no parameters
+[ 3.101063] NET: Registered protocol family 16
+[ 3.101179] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.101187] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.101343] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.101347] Serial: AMBA PL011 UART driver
+[ 3.101513] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.101543] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.102115] console [ttyAMA0] enabled
+[ 3.102184] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.102216] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.102248] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.102278] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130478] 3V3: 3300 mV
+[ 3.130515] vgaarb: loaded
+[ 3.130558] SCSI subsystem initialized
+[ 3.130595] libata version 3.00 loaded.
+[ 3.130635] usbcore: registered new interface driver usbfs
+[ 3.130652] usbcore: registered new interface driver hub
+[ 3.130683] usbcore: registered new device driver usb
+[ 3.130706] pps_core: LinuxPPS API ver. 1 registered
+[ 3.130716] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.130734] PTP clock support registered
+[ 3.130840] Switched to clocksource arch_sys_counter
+[ 3.131799] NET: Registered protocol family 2
+[ 3.131866] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.131883] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.131902] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.131917] TCP: reno registered
+[ 3.131924] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131937] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131972] NET: Registered protocol family 1
+[ 3.132017] RPC: Registered named UNIX socket transport module.
+[ 3.132028] RPC: Registered udp transport module.
+[ 3.132036] RPC: Registered tcp transport module.
+[ 3.132044] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.132057] PCI: CLS 0 bytes, default 64
+[ 3.132193] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.132284] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.133790] fuse init (API version 7.23)
+[ 3.133866] msgmni has been set to 469
+[ 3.135967] io scheduler noop registered
+[ 3.136016] io scheduler cfq registered (default)
+[ 3.136336] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.136349] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.136360] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.136373] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.136383] pci_bus 0000:00: scanning bus
+[ 3.136393] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.136406] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.136420] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.136454] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.136466] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.136477] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.136488] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.136499] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.136510] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.136521] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.136554] pci_bus 0000:00: fixups for bus
+[ 3.136562] pci_bus 0000:00: bus scan returning with max=00
+[ 3.136574] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.136592] pci 0000:00:00.0: fixup irq: got 33
+[ 3.136601] pci 0000:00:00.0: assigning IRQ 33
+[ 3.136611] pci 0000:00:01.0: fixup irq: got 34
+[ 3.136620] pci 0000:00:01.0: assigning IRQ 34
+[ 3.136631] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.136644] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.136657] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.136670] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.136682] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.136693] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.136705] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.136716] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.137147] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.137373] ata_piix 0000:00:01.0: version 2.13
+[ 3.137384] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.137403] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.137653] scsi0 : ata_piix
+[ 3.137740] scsi1 : ata_piix
+[ 3.137768] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.137780] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.137872] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.137884] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.137899] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.137911] e1000 0000:00:00.0: enabling bus mastering
+[ 3.290863] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.290873] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.290899] ata1.00: configured for UDMA/33
+[ 3.290941] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.291042] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.291065] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.291102] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.291112] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.291131] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.291239] sda: sda1
+[ 3.291342] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.411129] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.411142] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.411163] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.411173] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.411193] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.411205] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.411268] usbcore: registered new interface driver usb-storage
+[ 3.411318] mousedev: PS/2 mouse device common for all mice
+[ 3.411454] usbcore: registered new interface driver usbhid
+[ 3.411464] usbhid: USB HID core driver
+[ 3.411492] TCP: cubic registered
+[ 3.411499] NET: Registered protocol family 17
+ +[ 3.411840] devtmpfs: mounted
+[ 3.411860] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.450359] udevd[607]: starting version 182
+[ 3.450256] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.543431] random: dd urandom read with 19 bits of entropy available
+[ 3.603394] random: dd urandom read with 21 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -168,8 +168,8 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
-Configuring network interfaces... [ 3.671103] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
-udhcpc (v1.21.1) started
+Configuring network interfaces... udhcpc (v1.21.1) started
+[ 3.741068] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
|