diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3 | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt | 3052 |
1 files changed, 1526 insertions, 1526 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 7e1388539..7623e0029 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.327143 # Number of seconds simulated -sim_ticks 51327142820000 # Number of ticks simulated -final_tick 51327142820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.558015 # Number of seconds simulated +sim_ticks 51558014828000 # Number of ticks simulated +final_tick 51558014828000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161850 # Simulator instruction rate (inst/s) -host_op_rate 190176 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9793667461 # Simulator tick rate (ticks/s) -host_mem_usage 681320 # Number of bytes of host memory used -host_seconds 5240.85 # Real time elapsed on the host -sim_insts 848230502 # Number of instructions simulated -sim_ops 996685945 # Number of ops (including micro ops) simulated +host_inst_rate 133865 # Simulator instruction rate (inst/s) +host_op_rate 157345 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6235119796 # Simulator tick rate (ticks/s) +host_mem_usage 696436 # Number of bytes of host memory used +host_seconds 8268.97 # Real time elapsed on the host +sim_insts 1106923026 # Number of instructions simulated +sim_ops 1301083589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 212864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5673056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 41642312 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory -system.physmem.bytes_read::total 48200872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5673056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5673056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68445056 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 667968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 559488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6546400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112650248 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 429376 # Number of bytes read from this memory +system.physmem.bytes_read::total 120853480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6546400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6546400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 140957120 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 68465636 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3326 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 104594 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 650674 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory -system.physmem.num_reads::total 769104 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1069454 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 140977700 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 10437 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 118240 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1760173 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6709 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1904301 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2202455 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1072027 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 110527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 811312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 939091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 110527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 110527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1333506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1333907 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1333506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 110527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 811713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2272998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 769104 # Number of read requests accepted -system.physmem.writeReqs 1072027 # Number of write requests accepted -system.physmem.readBursts 769104 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1072027 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 49176064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 46592 # Total number of bytes read from write queue -system.physmem.bytesWritten 68464384 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 48200872 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 68465636 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 728 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one +system.physmem.num_writes::total 2205028 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 12956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 10852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 126972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2184922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2344029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 126972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 126972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2733952 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2734351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2733952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 10852 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 126972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2185321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5078380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1904301 # Number of read requests accepted +system.physmem.writeReqs 2205028 # Number of write requests accepted +system.physmem.readBursts 1904301 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2205028 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 121838144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue +system.physmem.bytesWritten 140976896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 120853480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 140977700 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 44564 # Per bank write bursts -system.physmem.perBankRdBursts::1 52315 # Per bank write bursts -system.physmem.perBankRdBursts::2 47721 # Per bank write bursts -system.physmem.perBankRdBursts::3 44538 # Per bank write bursts -system.physmem.perBankRdBursts::4 44659 # Per bank write bursts -system.physmem.perBankRdBursts::5 50872 # Per bank write bursts -system.physmem.perBankRdBursts::6 46439 # Per bank write bursts -system.physmem.perBankRdBursts::7 47959 # Per bank write bursts -system.physmem.perBankRdBursts::8 44018 # Per bank write bursts -system.physmem.perBankRdBursts::9 71274 # Per bank write bursts -system.physmem.perBankRdBursts::10 43972 # Per bank write bursts -system.physmem.perBankRdBursts::11 51692 # Per bank write bursts -system.physmem.perBankRdBursts::12 45026 # Per bank write bursts -system.physmem.perBankRdBursts::13 46672 # Per bank write bursts -system.physmem.perBankRdBursts::14 42515 # Per bank write bursts -system.physmem.perBankRdBursts::15 44140 # Per bank write bursts -system.physmem.perBankWrBursts::0 64758 # Per bank write bursts -system.physmem.perBankWrBursts::1 69412 # Per bank write bursts -system.physmem.perBankWrBursts::2 67623 # Per bank write bursts -system.physmem.perBankWrBursts::3 66442 # Per bank write bursts -system.physmem.perBankWrBursts::4 66817 # Per bank write bursts -system.physmem.perBankWrBursts::5 69740 # Per bank write bursts -system.physmem.perBankWrBursts::6 65132 # Per bank write bursts -system.physmem.perBankWrBursts::7 69008 # Per bank write bursts -system.physmem.perBankWrBursts::8 65482 # Per bank write bursts -system.physmem.perBankWrBursts::9 70623 # Per bank write bursts -system.physmem.perBankWrBursts::10 64235 # Per bank write bursts -system.physmem.perBankWrBursts::11 70444 # Per bank write bursts -system.physmem.perBankWrBursts::12 64965 # Per bank write bursts -system.physmem.perBankWrBursts::13 66804 # Per bank write bursts -system.physmem.perBankWrBursts::14 64273 # Per bank write bursts -system.physmem.perBankWrBursts::15 63998 # Per bank write bursts +system.physmem.perBankRdBursts::0 114327 # Per bank write bursts +system.physmem.perBankRdBursts::1 123692 # Per bank write bursts +system.physmem.perBankRdBursts::2 118245 # Per bank write bursts +system.physmem.perBankRdBursts::3 117057 # Per bank write bursts +system.physmem.perBankRdBursts::4 115229 # Per bank write bursts +system.physmem.perBankRdBursts::5 125268 # Per bank write bursts +system.physmem.perBankRdBursts::6 115683 # Per bank write bursts +system.physmem.perBankRdBursts::7 119593 # Per bank write bursts +system.physmem.perBankRdBursts::8 115543 # Per bank write bursts +system.physmem.perBankRdBursts::9 144676 # Per bank write bursts +system.physmem.perBankRdBursts::10 112600 # Per bank write bursts +system.physmem.perBankRdBursts::11 120122 # Per bank write bursts +system.physmem.perBankRdBursts::12 113965 # Per bank write bursts +system.physmem.perBankRdBursts::13 118266 # Per bank write bursts +system.physmem.perBankRdBursts::14 113146 # Per bank write bursts +system.physmem.perBankRdBursts::15 116309 # Per bank write bursts +system.physmem.perBankWrBursts::0 135142 # Per bank write bursts +system.physmem.perBankWrBursts::1 141643 # Per bank write bursts +system.physmem.perBankWrBursts::2 136917 # Per bank write bursts +system.physmem.perBankWrBursts::3 137997 # Per bank write bursts +system.physmem.perBankWrBursts::4 135684 # Per bank write bursts +system.physmem.perBankWrBursts::5 143871 # Per bank write bursts +system.physmem.perBankWrBursts::6 135153 # Per bank write bursts +system.physmem.perBankWrBursts::7 138864 # Per bank write bursts +system.physmem.perBankWrBursts::8 135935 # Per bank write bursts +system.physmem.perBankWrBursts::9 142790 # Per bank write bursts +system.physmem.perBankWrBursts::10 134947 # Per bank write bursts +system.physmem.perBankWrBursts::11 140191 # Per bank write bursts +system.physmem.perBankWrBursts::12 134987 # Per bank write bursts +system.physmem.perBankWrBursts::13 137976 # Per bank write bursts +system.physmem.perBankWrBursts::14 134592 # Per bank write bursts +system.physmem.perBankWrBursts::15 136075 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 34 # Number of times write queue was full causing retry -system.physmem.totGap 51327141408500 # Total gap between requests +system.physmem.numWrRetry 125 # Number of times write queue was full causing retry +system.physmem.totGap 51558013451500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 747819 # Read request sizes (log2) +system.physmem.readPktSize::6 1883016 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1069454 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 515353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 203905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2202455 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1140639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 689076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,171 +160,170 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 69842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 64006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 76985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 65026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 68511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 57192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 74 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 471870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.306089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 149.569568 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.567780 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 207742 44.03% 44.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 122462 25.95% 69.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 42886 9.09% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22733 4.82% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14982 3.18% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9606 2.04% 89.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7566 1.60% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6003 1.27% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 37890 8.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 471870 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 54238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.166341 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 76.651597 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 54233 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 30482 # 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What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 933198 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 281.628105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.352526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.404332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 371108 39.77% 39.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 233427 25.01% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 88383 9.47% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51664 5.54% 79.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 37413 4.01% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26389 2.83% 86.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21045 2.26% 88.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17945 1.92% 90.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 85824 9.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 933198 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 116229 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.379053 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 52.340079 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 116223 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 54238 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 54238 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.723367 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.775784 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.950161 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 40620 74.89% 74.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4585 8.45% 83.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 5200 9.59% 92.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1381 2.55% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 413 0.76% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 235 0.43% 96.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 311 0.57% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 127 0.23% 97.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 390 0.72% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 127 0.23% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 50 0.09% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 65 0.12% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 327 0.60% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.07% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 29 0.05% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 111 0.20% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 166 0.31% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 54238 # Writes before turning the bus around for reads -system.physmem.totQLat 15209667379 # Total ticks spent queuing -system.physmem.totMemAccLat 29616717379 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3841880000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19794.56 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 116229 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 116228 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.951965 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.478061 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.079115 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 111884 96.26% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 1770 1.52% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 397 0.34% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 626 0.54% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 488 0.42% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 246 0.21% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 362 0.31% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 120 0.10% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 64 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 59 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 51 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 11 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 17 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 10 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 37 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 24 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 14 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 5 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::624-639 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::752-767 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::976-991 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 116228 # Writes before turning the bus around for reads +system.physmem.totQLat 42075497859 # Total ticks spent queuing +system.physmem.totMemAccLat 77770266609 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9518605000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22101.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38544.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.33 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40851.71 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.34 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.73 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.49 # Average write queue length when enqueuing -system.physmem.readRowHits 580662 # Number of row buffer hits during reads -system.physmem.writeRowHits 785598 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.44 # Row buffer hit rate for writes -system.physmem.avgGap 27878049.64 # Average gap between requests -system.physmem.pageHitRate 74.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1803657240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 984138375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2956722600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3492279360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1235640856320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29712388110000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34309704980775 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.451533 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49429181288166 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing +system.physmem.readRowHits 1533744 # Number of row buffer hits during reads +system.physmem.writeRowHits 1639539 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes +system.physmem.avgGap 12546577.18 # Average gap between requests +system.physmem.pageHitRate 77.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3530119320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1926156375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7402894200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 7162084800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1313077918185 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29782982922000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34483600624320 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.831109 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49545451951432 # Time in different power states +system.physmem_0.memoryStateTime::REF 1721635240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 184032075584 # Time in different power states +system.physmem_0.memoryStateTime::ACT 290927248568 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1763679960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 962325375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3036563400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3439739520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1235034526230 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29712919978500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34309596029865 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.449411 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49430060847495 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states +system.physmem_1.actEnergy 3524804640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1923256500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7446082800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 7111728720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1314046606680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29782133195250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34483704204030 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.833118 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49544014933949 # Time in different power states +system.physmem_1.memoryStateTime::REF 1721635240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 183155359005 # Time in different power states +system.physmem_1.memoryStateTime::ACT 292364518051 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -341,30 +340,30 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 225047911 # Number of BP lookups -system.cpu.branchPred.condPredicted 149825196 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12305756 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158986930 # Number of BTB lookups -system.cpu.branchPred.BTBHits 98148773 # Number of BTB hits +system.cpu.branchPred.lookups 290131106 # Number of BP lookups +system.cpu.branchPred.condPredicted 198353835 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13679752 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 208494226 # Number of BTB lookups +system.cpu.branchPred.BTBHits 130534623 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.733863 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30878370 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 343644 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6734089 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4745857 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1988232 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 765703 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 62.608268 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37597374 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 402079 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 8125236 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6045082 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2080154 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 800698 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -394,87 +393,88 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 948773 # Table walker walks requested -system.cpu.dtb.walker.walksLong 948773 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15596 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155468 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 437937 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 510836 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2285.186439 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 14758.274331 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 507265 99.30% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 2025 0.40% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 1066 0.21% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 211 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 145 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 51 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 43 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 1423094 # Table walker walks requested +system.cpu.dtb.walker.walksLong 1423094 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30587 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273540 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 668841 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 754253 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2502.822660 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 16371.142747 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 747574 99.11% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 4739 0.63% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 871 0.12% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 433 0.06% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 327 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 64 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 235 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 510836 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 488329 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23221.803333 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 18175.804190 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 21042.780895 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 476828 97.64% 97.64% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 7891 1.62% 99.26% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2533 0.52% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 229 0.05% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 568 0.12% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 131 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 114 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 488329 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 779668986876 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.725199 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.523523 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 777411937376 99.71% 99.71% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1169683000 0.15% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 513347500 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 208116000 0.03% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 157188000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 121226500 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 32342000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 52541000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2605500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 779668986876 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 155469 90.88% 90.88% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15596 9.12% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 171065 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 948773 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 754253 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 795185 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 25800.017606 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21033.129871 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 18337.040091 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 776690 97.67% 97.67% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 15553 1.96% 99.63% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1840 0.23% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 320 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 153 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 44 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 795185 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1040609044948 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.747004 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.517062 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 1036648437448 99.62% 99.62% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 2501393000 0.24% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 710900000 0.07% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 286069000 0.03% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 201203000 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 121106500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 48982500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 87667500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 3189000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 41500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::20-21 55500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1040609044948 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 273541 89.94% 89.94% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 30587 10.06% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 304128 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1423094 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 948773 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171065 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1423094 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304128 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171065 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1119838 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304128 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1727222 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 169411407 # DTB read hits -system.cpu.dtb.read_misses 675369 # DTB read misses -system.cpu.dtb.write_hits 147344334 # DTB write hits -system.cpu.dtb.write_misses 273404 # DTB write misses -system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed +system.cpu.dtb.read_hits 217549636 # DTB read hits +system.cpu.dtb.read_misses 1002675 # DTB read misses +system.cpu.dtb.write_hits 192429615 # DTB write hits +system.cpu.dtb.write_misses 420419 # DTB write misses +system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 71963 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10047 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 84838 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 16158 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69388 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 170086776 # DTB read accesses -system.cpu.dtb.write_accesses 147617738 # DTB write accesses +system.cpu.dtb.perms_faults 86326 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 218552311 # DTB read accesses +system.cpu.dtb.write_accesses 192850034 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 316755741 # DTB hits -system.cpu.dtb.misses 948773 # DTB misses -system.cpu.dtb.accesses 317704514 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 409979251 # DTB hits +system.cpu.dtb.misses 1423094 # DTB misses +system.cpu.dtb.accesses 411402345 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -504,1104 +504,1098 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 162181 # Table walker walks requested -system.cpu.itb.walker.walksLong 162181 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1496 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 120027 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17971 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144210 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1137.740101 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9342.723838 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 143038 99.19% 99.19% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 619 0.43% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 86 0.06% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 189 0.13% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 221 0.15% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 35 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144210 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 139494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29066.088864 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24052.553358 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24213.231696 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 136396 97.78% 97.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 707 0.51% 98.29% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1985 1.42% 99.71% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 151 0.11% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 171 0.12% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 34 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 139494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 676589720772 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.947980 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.222341 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 35236838356 5.21% 5.21% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 641313182416 94.79% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 39010000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 686000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 676589720772 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 120027 98.77% 98.77% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1496 1.23% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 121523 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 177767 # Table walker walks requested +system.cpu.itb.walker.walksLong 177767 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1532 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 128663 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 19966 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 157801 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1393.783943 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9971.559116 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 155663 98.65% 98.65% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 1042 0.66% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 672 0.43% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 333 0.21% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 30 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 157801 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 150161 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28501.914612 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23015.105793 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 23459.229673 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 144112 95.97% 95.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 5152 3.43% 99.40% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 475 0.32% 99.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 255 0.17% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 99 0.07% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 55 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 150161 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 911756921068 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.951043 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.216068 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 44693483152 4.90% 4.90% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 867007398416 95.09% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 55571500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 466000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 911756921068 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 128663 98.82% 98.82% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1532 1.18% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 130195 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162181 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 162181 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177767 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 177767 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121523 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 121523 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 283704 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 357038073 # ITB inst hits -system.cpu.itb.inst_misses 162181 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130195 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 130195 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 307962 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 462600046 # ITB inst hits +system.cpu.itb.inst_misses 177767 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52848 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 58185 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 357344 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 440221 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 357200254 # ITB inst accesses -system.cpu.itb.hits 357038073 # DTB hits -system.cpu.itb.misses 162181 # DTB misses -system.cpu.itb.accesses 357200254 # DTB accesses -system.cpu.numPwrStateTransitions 32228 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3134631677.512784 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 60494120707.852806 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 6793 42.16% 42.16% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9285 57.62% 99.78% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 462777813 # ITB inst accesses +system.cpu.itb.hits 462600046 # DTB hits +system.cpu.itb.misses 177767 # DTB misses +system.cpu.itb.accesses 462777813 # DTB accesses +system.cpu.numPwrStateTransitions 34262 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 17131 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 2947433272.666569 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 58590018858.186401 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7811 45.60% 45.60% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9284 54.19% 99.79% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 815687968559 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50511454851441 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1631385344 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 17131 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1065535433949 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50492479394051 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2131080190 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 646877625 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1002761410 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225047911 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133773000 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 898188451 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26266186 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3841497 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 30548 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8722394 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1026877 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 1034 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 356664988 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6247416 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 47904 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1571821519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.747042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.149310 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 789533395 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1294232501 # Number of instructions fetch has processed +system.cpu.fetch.Branches 290131106 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174177079 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1253396684 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29442936 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4521296 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 28032 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11449142 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1221670 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 685 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 462141962 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6901101 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 52491 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2074872372 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.731015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.142682 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1014113227 64.52% 64.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 214297646 13.63% 78.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70312417 4.47% 82.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 273098229 17.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1354023092 65.26% 65.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 279633538 13.48% 78.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 86518146 4.17% 82.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 354697596 17.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1571821519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.137949 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.614669 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 526332322 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 552246914 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 434136742 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49729183 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9376358 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33563941 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3814299 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1086052117 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29449193 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9376358 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 571289803 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 66024800 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 371545208 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 438989582 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 114595768 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1065754363 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6907795 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5097238 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 334375 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 639506 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 63573833 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20465 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1013430764 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1640279788 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1259572075 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1474026 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 947250209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 66180552 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26901106 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23243208 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 101784051 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173837388 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 150829276 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9883117 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9014861 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1030729252 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27201158 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1045808358 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3377405 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 61244461 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 34071399 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 308913 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1571821519 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.665348 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.919634 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 2074872372 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.136143 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.607313 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 615922756 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 835719938 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 532432043 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80077312 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10720323 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41258933 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4059445 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1407827153 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 33008479 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10720323 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 679035070 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 79966926 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 552687037 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 549603762 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 202859254 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1383638167 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 8109162 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7348509 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 966276 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1094350 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 119568064 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 22725 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1333397174 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2200696007 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1641425227 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1433031 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1254726296 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 78670875 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 43643507 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39180007 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 166278031 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 222554034 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 196867138 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12635283 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11114743 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1330840515 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 43953891 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1360477402 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4212137 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 73710813 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41934009 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 368799 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2074872372 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.655692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.916068 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 924230442 58.80% 58.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 334342298 21.27% 80.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234750151 14.93% 95.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72048277 4.58% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6430828 0.41% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19523 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1226409345 59.11% 59.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 451307165 21.75% 80.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 291780533 14.06% 94.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 95920964 4.62% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9425546 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 28819 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1571821519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2074872372 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57691324 35.03% 35.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100152 0.06% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26730 0.02% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 622 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44285841 26.89% 62.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62576075 38.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 73561900 34.17% 34.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90692 0.04% 34.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26794 0.01% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 484 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 57931960 26.91% 61.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 83660297 38.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 720343690 68.88% 68.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2530628 0.24% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122776 0.01% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 375 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 119191 0.01% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 173490543 16.59% 85.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 149201098 14.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 939889673 69.09% 69.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2936613 0.22% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 130878 0.01% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 112363 0.01% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 222587367 16.36% 85.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194820033 14.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1045808358 # Type of FU issued -system.cpu.iq.rate 0.641055 # Inst issue rate -system.cpu.iq.fu_busy_cnt 164680744 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157467 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3829023509 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1118377930 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1027460456 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2472874 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 938610 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909796 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1208933693 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1555398 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4274316 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1360477402 # Type of FU issued +system.cpu.iq.rate 0.638398 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215272127 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.158233 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5012901497 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1447776434 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1338315649 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2409942 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 914537 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 885572 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1574233532 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1515940 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5717597 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14173969 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14495 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 142953 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6059351 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17343387 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24124 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 187368 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7978529 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2526453 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1440750 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3596780 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1680866 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9376358 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7004216 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6913167 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1058165202 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 10720323 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12040487 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4569260 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1375079942 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173837388 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 150829276 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22819114 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 57849 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6781828 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 142953 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3462734 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5495013 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8957747 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1034296660 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169399584 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10573772 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 222554034 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 196867138 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 38644291 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 177419 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4207009 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 187368 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4048268 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6103351 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10151619 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1346834094 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 217554512 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12249639 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 234792 # number of nop insts executed -system.cpu.iew.exec_refs 316739180 # number of memory reference insts executed -system.cpu.iew.exec_branches 196198672 # Number of branches executed -system.cpu.iew.exec_stores 147339596 # Number of stores executed -system.cpu.iew.exec_rate 0.633999 # Inst execution rate -system.cpu.iew.wb_sent 1029187818 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1028370252 # cumulative count of insts written-back -system.cpu.iew.wb_producers 437853372 # num instructions producing a value -system.cpu.iew.wb_consumers 708400240 # num instructions consuming a value -system.cpu.iew.wb_rate 0.630366 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618088 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 51884426 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 26892245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8549021 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1559762540 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.638999 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273827 # Number of insts commited each cycle +system.cpu.iew.exec_nop 285536 # number of nop insts executed +system.cpu.iew.exec_refs 409993947 # number of memory reference insts executed +system.cpu.iew.exec_branches 255680172 # Number of branches executed +system.cpu.iew.exec_stores 192439435 # Number of stores executed +system.cpu.iew.exec_rate 0.631996 # Inst execution rate +system.cpu.iew.wb_sent 1340240150 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1339201221 # cumulative count of insts written-back +system.cpu.iew.wb_producers 574929948 # num instructions producing a value +system.cpu.iew.wb_consumers 943031378 # num instructions consuming a value +system.cpu.iew.wb_rate 0.628414 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.609662 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 62850702 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 43585092 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9678607 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2060674246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.631387 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.270689 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1047991029 67.19% 67.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288035307 18.47% 85.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120100080 7.70% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36659789 2.35% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28506606 1.83% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13942789 0.89% 98.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8651847 0.55% 98.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4181084 0.27% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11694009 0.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1383412740 67.13% 67.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 394991247 19.17% 86.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 150433823 7.30% 93.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44582057 2.16% 95.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36156812 1.75% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18175173 0.88% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10964042 0.53% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5475656 0.27% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16482696 0.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1559762540 # Number of insts commited each cycle -system.cpu.commit.committedInsts 848230502 # Number of instructions committed -system.cpu.commit.committedOps 996685945 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 2060674246 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1106923026 # Number of instructions committed +system.cpu.commit.committedOps 1301083589 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 304433343 # Number of memory references committed -system.cpu.commit.loads 159663418 # Number of loads committed -system.cpu.commit.membars 6927415 # Number of memory barriers committed -system.cpu.commit.branches 189324067 # Number of branches committed -system.cpu.commit.fp_insts 898712 # Number of committed floating point instructions. -system.cpu.commit.int_insts 915721971 # Number of committed integer instructions. -system.cpu.commit.function_calls 25285288 # Number of function calls committed. +system.cpu.commit.refs 394099255 # Number of memory references committed +system.cpu.commit.loads 205210646 # Number of loads committed +system.cpu.commit.membars 9122435 # Number of memory barriers committed +system.cpu.commit.branches 247396089 # Number of branches committed +system.cpu.commit.fp_insts 873905 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1189215854 # Number of committed integer instructions. +system.cpu.commit.function_calls 30973786 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 689893101 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2149376 0.22% 69.43% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98151 0.01% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 159663418 16.02% 85.47% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 144769925 14.53% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 904226715 69.50% 69.50% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2546778 0.20% 69.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 104952 0.01% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 105847 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 205210646 15.77% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 188888609 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 996685945 # Class of committed instruction -system.cpu.commit.bw_lim_events 11694009 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2589097882 # The number of ROB reads -system.cpu.rob.rob_writes 2109106528 # The number of ROB writes -system.cpu.timesIdled 8171713 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59563825 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101022900419 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 848230502 # Number of Instructions Simulated -system.cpu.committedOps 996685945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.923281 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.923281 # CPI: Total CPI of All Threads -system.cpu.ipc 0.519945 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.519945 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1223820104 # number of integer regfile reads -system.cpu.int_regfile_writes 731394790 # number of integer regfile writes -system.cpu.fp_regfile_reads 1462803 # number of floating regfile reads -system.cpu.fp_regfile_writes 780644 # number of floating regfile writes -system.cpu.cc_regfile_reads 225050166 # number of cc regfile reads -system.cpu.cc_regfile_writes 225684828 # number of cc regfile writes -system.cpu.misc_regfile_reads 2570368432 # number of misc regfile reads -system.cpu.misc_regfile_writes 26931155 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9701158 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 283187639 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9701670 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.189577 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 1301083589 # Class of committed instruction +system.cpu.commit.bw_lim_events 16482696 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3398675710 # The number of ROB reads +system.cpu.rob.rob_writes 2741957858 # The number of ROB writes +system.cpu.timesIdled 9058128 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 56207818 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100984949503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1106923026 # Number of Instructions Simulated +system.cpu.committedOps 1301083589 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.925229 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.925229 # CPI: Total CPI of All Threads +system.cpu.ipc 0.519419 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.519419 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1599627417 # number of integer regfile reads +system.cpu.int_regfile_writes 942915680 # number of integer regfile writes +system.cpu.fp_regfile_reads 1421408 # number of floating regfile reads +system.cpu.fp_regfile_writes 762380 # number of floating regfile writes +system.cpu.cc_regfile_reads 312164706 # number of cc regfile reads +system.cpu.cc_regfile_writes 313034766 # number of cc regfile writes +system.cpu.misc_regfile_reads 3414318389 # number of misc regfile reads +system.cpu.misc_regfile_writes 44468731 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 13662519 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.983620 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 361203380 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 13663031 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.436548 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1659288500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.983620 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1237018765 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1237018765 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 147199934 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147199934 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128255410 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128255410 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 377663 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 377663 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 323814 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 323814 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295431 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3295431 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3691256 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3691256 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 275779158 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 275779158 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 276156821 # number of overall hits -system.cpu.dcache.overall_hits::total 276156821 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9580915 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9580915 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11254027 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11254027 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1170464 # 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average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42455.895354 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42455.895354 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15410.394686 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15410.394686 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47562.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47562.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30153.339859 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30153.339859 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28634.628622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28634.628622 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32224409 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.085323 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.085323 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.090060 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.090060 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16095.314606 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16095.314606 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53809.325082 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53809.325082 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23587.956296 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23587.956296 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16291.062223 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16291.062223 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33388.888889 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33388.888889 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37889.669487 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37889.669487 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35663.668807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35663.668807 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24419954 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1601607 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2093623 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.120048 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.663969 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7504086 # number of writebacks -system.cpu.dcache.writebacks::total 7504086 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4456599 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4456599 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9250788 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9250788 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7056 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23723735000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23723735000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50708992789 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50708992789 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3202218000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3202218000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 372500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 372500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213227028135 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 213227028135 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236950763135 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 236950763135 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192056000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192056000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192056000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192056000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032685 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032685 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751649 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751649 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787557 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787557 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060778 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060778 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 10319802 # number of writebacks +system.cpu.dcache.writebacks::total 10319802 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5736139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5736139 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15576096 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15576096 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6849 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 6849 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265006 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 265006 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 21319084 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21319084 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21319084 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21319084 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7051922 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7051922 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3072420 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3072420 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2034687 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2034687 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263657 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1263657 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283363 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 283363 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 9 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 11387999 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 11387999 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 13422686 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 13422686 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110827450000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 110827450000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 147154305213 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 147154305213 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32559356000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32559356000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28426038502 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28426038502 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4117736500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4117736500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 291500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 291500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286407793715 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 286407793715 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318967149715 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 318967149715 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225596500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225596500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225596500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225596500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035306 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035306 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016882 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016882 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.812301 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.812301 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787574 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787574 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053048 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053048 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028048 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028048 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031790 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031790 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16579.764890 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16579.764890 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38716.339311 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38716.339311 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20387.380892 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20387.380892 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41341.672589 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41341.672589 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14079.334860 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14079.334860 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46562.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46562.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25523.522371 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25523.522371 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24895.575834 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24895.575834 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183860.561791 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183860.561791 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.720308 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.720308 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 15134592 # number of replacements -system.cpu.icache.tags.tagsinuse 511.928988 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 340756209 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15135104 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.514296 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.928988 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029708 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029708 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15715.921135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15715.921135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47895.243884 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47895.243884 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16002.144802 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16002.144802 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22495.058787 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22495.058787 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14531.666096 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14531.666096 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32388.888889 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32388.888889 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25149.966532 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25149.966532 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23763.287744 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23763.287744 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184779.665796 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184779.665796 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92374.753320 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92374.753320 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 16891256 # number of replacements +system.cpu.icache.tags.tagsinuse 511.956016 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 444441322 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16891768 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26.311119 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13164566500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.956016 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999914 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999914 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 112 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 371779021 # Number of tag accesses -system.cpu.icache.tags.data_accesses 371779021 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 340756209 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 340756209 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 340756209 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 340756209 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 340756209 # number of overall hits -system.cpu.icache.overall_hits::total 340756209 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15887482 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15887482 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15887482 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15887482 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15887482 # number of overall misses -system.cpu.icache.overall_misses::total 15887482 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 214918228873 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 214918228873 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 214918228873 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 214918228873 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 214918228873 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 214918228873 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 356643691 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 356643691 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 356643691 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 356643691 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 356643691 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 356643691 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044547 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044547 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044547 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044547 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044547 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044547 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13527.519897 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13527.519897 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13527.519897 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13527.519897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13527.519897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13527.519897 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 24649 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 479012658 # Number of tag accesses +system.cpu.icache.tags.data_accesses 479012658 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 444441322 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 444441322 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 444441322 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 444441322 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 444441322 # number of overall hits +system.cpu.icache.overall_hits::total 444441322 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17679342 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17679342 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17679342 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17679342 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17679342 # 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mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.076921 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030044 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128624.275131 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68019.072693 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68019.072693 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129347.114780 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129347.114780 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124865.765533 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124865.765533 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129442.828646 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129442.828646 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69894.144460 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69894.144460 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171356.256310 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148979.471367 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85655.237926 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.643028 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 50407203 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 25570213 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2115 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2115 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.094837 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.094837 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.444444 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437822 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437822 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005741 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045756 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045756 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.466977 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.466977 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060787 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060787 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79519.552688 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19090.240314 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19090.240314 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82894.958867 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82894.958867 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75598.356935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75598.356935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80471.401186 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80471.401186 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.901693 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.901693 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172274.946575 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130011.912123 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86123.414200 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 80605.655718 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 62084255 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 31529230 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3455 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1618708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23266675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8573574 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 15134592 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2391693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43548 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1963232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1963232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15135331 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6520715 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1333247 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1226583 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45447628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29327152 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 726647 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1928826 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 77430253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1937602080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1022907422 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2405600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6328296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2969243398 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1852603 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 72285944 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 27912596 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.024958 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.155996 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 2242102 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28488845 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 12415627 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16891256 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3619797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43003 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3045422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3045422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 16891994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 9356331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1295806 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1263657 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50717623 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41210208 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 777423 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3005376 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 95710630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2162455328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1454268658 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2489712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10275752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3629489450 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2999840 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 138927432 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 35281285 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.026592 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.160887 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 27215961 97.50% 97.50% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 696635 2.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 34343098 97.34% 97.34% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 938187 2.66% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 27912596 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 48339894491 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 35281285 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 58941748976 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1459384 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1470395 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22733591738 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25369728010 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13401353655 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 19308156079 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 426266814 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 466604190 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1138134788 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1721722349 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40293 # Transaction distribution -system.iobus.trans_dist::ReadResp 40293 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40300 # Transaction distribution +system.iobus.trans_dist::ReadResp 40300 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1618,11 +1612,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353742 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1637,16 +1631,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41884500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492184 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41887500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 345000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 337000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1654,85 +1648,85 @@ system.iobus.reqLayer4.occupancy 9500 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25117000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25106500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567323274 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568968673 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147704000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147718000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115453 # number of replacements -system.iocache.tags.tagsinuse 10.423128 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115465 # number of replacements +system.iocache.tags.tagsinuse 10.450543 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13098782503000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544201 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.878927 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651446 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13091229344000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.877255 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.573288 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.367328 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.285830 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653159 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039605 # Number of tag accesses -system.iocache.tags.data_accesses 1039605 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039668 # Number of tag accesses +system.iocache.tags.data_accesses 1039668 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8808 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8845 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115472 # number of demand (read+write) misses -system.iocache.demand_misses::total 115512 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115479 # number of demand (read+write) misses +system.iocache.demand_misses::total 115519 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115472 # number of overall misses -system.iocache.overall_misses::total 115512 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5076000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1670063987 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1675139987 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115479 # number of overall misses +system.iocache.overall_misses::total 115519 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1629675592 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1634761592 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13414774287 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13414774287 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5427000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15084838274 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15090265274 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5427000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15084838274 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15090265274 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12811525081 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12811525081 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14441200673 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14446637673 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14441200673 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14446637673 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8808 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8845 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115472 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115512 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115479 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115519 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115472 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115512 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115479 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115519 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1746,53 +1740,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137189.189189 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 189607.627952 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 189388.353533 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184875.279864 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 184677.089019 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125766.653107 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125766.653107 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135675 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130638.074607 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135675 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130638.074607 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33964 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120111.050411 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120111.050411 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125058.541651 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125058.541651 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32070 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3510 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.676353 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.390922 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8808 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8845 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115472 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115512 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115479 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115519 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115472 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115512 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3226000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1229663987 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1232889987 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115479 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115519 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1188925592 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1192161592 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8076516803 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8076516803 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3427000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9306180790 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9309607790 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3427000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9306180790 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9309607790 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7471582182 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7471582182 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8660507774 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8663944774 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8660507774 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8663944774 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1806,89 +1800,95 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87189.189189 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139607.627952 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 139388.353533 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134875.279864 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 134677.089019 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75719.238009 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75719.238009 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 54972 # Transaction distribution -system.membus.trans_dist::ReadResp 411033 # Transaction distribution -system.membus.trans_dist::WriteReq 33696 # Transaction distribution -system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1069454 # Transaction distribution -system.membus.trans_dist::CleanEvict 193565 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34895 # Transaction distribution +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70047.834152 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70047.834152 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 5074419 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2524015 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3002 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 54986 # Transaction distribution +system.membus.trans_dist::ReadResp 608005 # Transaction distribution +system.membus.trans_dist::WriteReq 33703 # Transaction distribution +system.membus.trans_dist::WriteResp 33703 # Transaction distribution +system.membus.trans_dist::WritebackDirty 2202455 # Transaction distribution +system.membus.trans_dist::CleanEvict 284620 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4643 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 394310 # Transaction distribution -system.membus.trans_dist::ReadExResp 394310 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 356061 # Transaction distribution -system.membus.trans_dist::InvalidateReq 606112 # Transaction distribution +system.membus.trans_dist::ReadExReq 1332798 # Transaction distribution +system.membus.trans_dist::ReadExResp 1332798 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 553019 # Transaction distribution +system.membus.trans_dist::InvalidateReq 696755 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3212019 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3341639 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237917 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237917 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3579556 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6767333 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6896995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7134688 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109397260 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109567230 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7269248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7269248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 116836478 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2560 # Total snoops (count) -system.membus.snoopTraffic 163328 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2743103 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254577484 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254747538 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7253696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 262001234 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2809 # Total snoops (count) +system.membus.snoopTraffic 179264 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2675908 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013150 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.113918 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2743103 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2640719 98.68% 98.68% # Request fanout histogram +system.membus.snoop_fanout::1 35189 1.32% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2743103 # Request fanout histogram -system.membus.reqLayer0.occupancy 103939500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2675908 # Request fanout histogram +system.membus.reqLayer0.occupancy 103923000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5573000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5620000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7172212711 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 14223305475 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4075256665 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 10050154677 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44789891 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44814659 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1898,11 +1898,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1931,30 +1931,30 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 17131 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |