diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-09-16 09:14:31 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-09-16 09:14:31 +0100 |
| commit | ada0e2f02fb3a30d01f62eb124a1d374be0b8ed5 (patch) | |
| tree | 82c5b4db42b6ade0e4eeed758be629c57e2f5f60 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt | |
| parent | 1ecc3628a8fe24d8ed189ee23ca41f2b385b3d8e (diff) | |
| download | gem5-ada0e2f02fb3a30d01f62eb124a1d374be0b8ed5.tar.xz | |
tests, arm: Make switcheroo and checkpoint tests functional
Switcheroo and checkpoint tests should generally be considered to be
successful if they run to completion. Remove all reference output
files from the switcheroo and checkopint tests to make them purely
functional.
Change-Id: I70b47853bd662b7a33716d9e0d2154b16077f9dc
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt | 874 |
1 files changed, 0 insertions, 874 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt deleted file mode 100644 index a22c43be0..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ /dev/null @@ -1,874 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 51.111167 # Number of seconds simulated -sim_ticks 51111167268500 # Number of ticks simulated -final_tick 51111167268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 926682 # Simulator instruction rate (inst/s) -host_op_rate 1089052 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48222226969 # Simulator tick rate (ticks/s) -host_mem_usage 681368 # Number of bytes of host memory used -host_seconds 1059.91 # Real time elapsed on the host -sim_insts 982198023 # Number of instructions simulated -sim_ops 1154295627 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5483444 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 74913992 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory -system.physmem.bytes_read::total 81622268 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5483444 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5483444 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103278528 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103299108 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 126086 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1170544 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315768 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613727 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616300 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 107285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1465707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1596956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1466110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3618023 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 266581 # Table walker walks requested -system.cpu.dtb.walker.walksLong 266581 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walkWaitTime::samples 266581 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 266581 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 266581 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 204774 89.35% 89.35% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 24411 10.65% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 229185 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266581 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266581 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229185 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229185 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 495766 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183543984 # DTB read hits -system.cpu.dtb.read_misses 195343 # DTB read misses -system.cpu.dtb.write_hits 167774645 # DTB write hits -system.cpu.dtb.write_misses 71238 # DTB write misses -system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 82439 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9074 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183739327 # DTB read accesses -system.cpu.dtb.write_accesses 167845883 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 351318629 # DTB hits -system.cpu.dtb.misses 266581 # DTB misses -system.cpu.dtb.accesses 351585210 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 126834 # Table walker walks requested -system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 126834 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 126834 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 113574 99.02% 99.02% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 114696 # Table walker page sizes translated -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126834 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 126834 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 982674869 # ITB inst hits -system.cpu.itb.inst_misses 126834 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 58009 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 982801703 # ITB inst accesses -system.cpu.itb.hits 982674869 # DTB hits -system.cpu.itb.misses 126834 # DTB misses -system.cpu.itb.accesses 982801703 # DTB accesses -system.cpu.numPwrStateTransitions 33550 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3012440908.824083 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59942517661.771744 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988782931704 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 577471022976 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50533696245524 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 102222351313 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu.committedInsts 982198023 # Number of instructions committed -system.cpu.committedOps 1154295627 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1057877135 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses -system.cpu.num_func_calls 56833843 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 151622640 # number of instructions that are conditional controls -system.cpu.num_int_insts 1057877135 # number of integer instructions -system.cpu.num_fp_insts 881349 # number of float instructions -system.cpu.num_int_register_reads 1560753668 # number of times the integer registers were read -system.cpu.num_int_register_writes 840513151 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read -system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written -system.cpu.num_cc_register_reads 264017457 # number of times the CC registers were read -system.cpu.num_cc_register_writes 263439679 # number of times the CC registers were written -system.cpu.num_mem_refs 351538055 # number of memory refs -system.cpu.num_load_insts 183711282 # Number of load instructions -system.cpu.num_store_insts 167826773 # Number of store instructions -system.cpu.num_idle_cycles 101067409077.505173 # Number of idle cycles -system.cpu.num_busy_cycles 1154942235.494823 # Number of busy cycles -system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.988702 # Percentage of idle cycles -system.cpu.Branches 219532189 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 800829443 69.34% 69.34% # Class of executed instruction -system.cpu.op_class::IntMult 2354388 0.20% 69.54% # Class of executed instruction -system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::MemRead 183711282 15.91% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 167826773 14.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1154930294 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11606056 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 339854782 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11606568 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.281247 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1417452033 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1417452033 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 171110167 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 171110167 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 159090000 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 159090000 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 424478 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 424478 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336283 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303639 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4303639 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4555644 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4555644 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 330536450 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 330536450 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 330960928 # number of overall hits -system.cpu.dcache.overall_hits::total 330960928 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6002834 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6002834 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2551547 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2551547 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1586190 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1586190 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1246772 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 253808 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 253808 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 9801153 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9801153 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11387343 # number of overall misses -system.cpu.dcache.overall_misses::total 11387343 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 177113001 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177113001 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 161641547 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 161641547 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010668 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2010668 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557447 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4557447 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555645 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4555645 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 340337603 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 340337603 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 342348271 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 342348271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033893 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033893 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015785 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015785 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788887 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788887 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787573 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.028798 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.028798 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.033262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.033262 # miss rate for overall accesses -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8918956 # number of writebacks -system.cpu.dcache.writebacks::total 8918956 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 14265255 # number of replacements -system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 968523793 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14265767 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.891463 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 997055337 # Number of tag accesses -system.cpu.icache.tags.data_accesses 997055337 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 968523793 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 968523793 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 968523793 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 968523793 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 968523793 # number of overall hits -system.cpu.icache.overall_hits::total 968523793 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14265772 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14265772 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14265772 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14265772 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14265772 # number of overall misses -system.cpu.icache.overall_misses::total 14265772 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 982789565 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 982789565 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 982789565 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 982789565 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 982789565 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 982789565 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014516 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 14265255 # number of writebacks -system.cpu.icache.writebacks::total 14265255 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1725823 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65403.901916 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 49389938 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1788899 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.609126 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9615.361386 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 436.090806 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 495.840367 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.388739 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48781.220619 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.146719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006654 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007566 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092703 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.744342 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997984 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 373 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62703 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 373 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55698 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005692 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956772 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 422564531 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 422564531 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 480106 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 237369 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 717475 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8918956 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8918956 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 14263678 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 14263678 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 30692 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 30692 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1689371 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1689371 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182774 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 14182774 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7498712 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7498712 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 694558 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 694558 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 480106 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 237369 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14182774 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9188083 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24088332 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 480106 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 237369 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14182774 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9188083 # number of overall hits -system.cpu.l2cache.overall_hits::total 24088332 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5837 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 12313 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3878 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3878 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 827606 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 827606 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 82998 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 82998 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344120 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 344120 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 552214 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 552214 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 82998 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1171726 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1267037 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 82998 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1171726 # number of overall misses -system.cpu.l2cache.overall_misses::total 1267037 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 486582 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 243206 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 729788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 8918956 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 8918956 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 14263678 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 14263678 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34570 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 34570 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516977 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2516977 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265772 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 14265772 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842832 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7842832 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246772 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 486582 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 243206 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 14265772 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10359809 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25355369 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 486582 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 243206 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14265772 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10359809 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25355369 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013309 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.024000 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016872 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.112178 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.112178 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328810 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.328810 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005818 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442915 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442915 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013309 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.024000 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005818 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.113103 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.049971 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013309 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.024000 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005818 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.113103 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.049971 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1507096 # number of writebacks -system.cpu.l2cache.writebacks::total 1507096 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 52368206 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 26495860 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2694 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2694 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1229979 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23338583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8918956 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14265255 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2687100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 34570 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 34571 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2516977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2516977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35022680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548392 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80212329 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826158228 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234030630 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3069415258 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1762518 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 96494656 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 54803543 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010878 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103729 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54207383 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 596160 1.09% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 54803543 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40242 # Transaction distribution -system.iobus.trans_dist::ReadResp 40242 # Transaction distribution -system.iobus.trans_dist::WriteReq 136515 # Transaction distribution -system.iobus.trans_dist::WriteResp 136515 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353514 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115459 # number of replacements -system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use -system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039650 # Number of tag accesses -system.iocache.tags.data_accesses 1039650 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses -system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses -system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses -system.iocache.demand_misses::total 115517 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115477 # number of overall misses -system.iocache.overall_misses::total 115517 # number of overall misses -system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks -system.membus.snoop_filter.tot_requests 3778694 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1875355 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 524960 # Transaction distribution -system.membus.trans_dist::WriteReq 33606 # Transaction distribution -system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1613727 # Transaction distribution -system.membus.trans_dist::CleanEvict 226320 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4445 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4446 # Transaction distribution -system.membus.trans_dist::ReadExReq 827049 # Transaction distribution -system.membus.trans_dist::ReadExResp 827049 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448281 # Transaction distribution -system.membus.trans_dist::InvalidateReq 658871 # Transaction distribution -system.membus.trans_dist::InvalidateResp 658871 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5462226 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5591418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5937911 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177871034 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 185261818 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3888979 # Request fanout histogram -system.membus.snoop_fanout::mean 0.009406 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.096529 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3852398 99.06% 99.06% # Request fanout histogram -system.membus.snoop_fanout::1 36581 0.94% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3888979 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks -system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks -system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks -system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks -system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks -system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks -system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks -system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- |