diff options
author | Joel Hestness <jthestness@gmail.com> | 2015-10-10 16:45:41 -0500 |
---|---|---|
committer | Joel Hestness <jthestness@gmail.com> | 2015-10-10 16:45:41 -0500 |
commit | 735c4a87665119a33443cf8d191d329c66191c6e (patch) | |
tree | 619a6c346beb6f7972acfa41a737b065f6c701c5 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual | |
parent | 1f2e7c1aaa17e55b06504264e40bde1a000f2214 (diff) | |
download | gem5-735c4a87665119a33443cf8d191d329c66191c6e.tar.xz |
stats: Update for UDelayEvent quiesce change
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual')
3 files changed, 54 insertions, 29 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini index 51a633a32..7d0d1367b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 +boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 +kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -38,11 +38,12 @@ mem_ranges=2147483648:2415919103 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true +multi_thread=false num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/home/joel/research/gem5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img +image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -383,12 +384,13 @@ size=1048576 [system.cpu0.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -396,6 +398,13 @@ width=32 master=system.cpu0.l2cache.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port +[system.cpu0.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu0.tracer] type=ExeTracer eventq_index=0 @@ -687,12 +696,13 @@ size=1048576 [system.cpu1.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -700,6 +710,13 @@ width=32 master=system.cpu1.l2cache.cpu_side slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port +[system.cpu1.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu1.tracer] type=ExeTracer eventq_index=0 @@ -1630,12 +1647,13 @@ port=3456 [system.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 response_latency=1 -snoop_filter=Null +snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -1643,6 +1661,13 @@ width=32 master=system.l2c.cpu_side slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side +[system.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.vncserver] type=VncServer eventq_index=0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout index 30f75cd41..e2743ea4d 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout @@ -1,16 +1,16 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 11:11:51 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual +gem5 compiled Oct 1 2015 05:39:21 +gem5 started Oct 2 2015 05:11:30 +gem5 executing on artery +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 47216814145000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index e3c32f3fb..3e7b5ca50 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.216814 # Nu sim_ticks 47216814145000 # Number of ticks simulated final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1096625 # Simulator instruction rate (inst/s) -host_op_rate 1290081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53081906922 # Simulator tick rate (ticks/s) -host_mem_usage 734248 # Number of bytes of host memory used -host_seconds 889.51 # Real time elapsed on the host +host_inst_rate 645560 # Simulator instruction rate (inst/s) +host_op_rate 759443 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31248192864 # Simulator tick rate (ticks/s) +host_mem_usage 683532 # Number of bytes of host memory used +host_seconds 1511.03 # Real time elapsed on the host sim_insts 975457230 # Number of instructions simulated sim_ops 1147538415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -241,9 +241,11 @@ system.cpu0.itb.inst_accesses 497757770 # IT system.cpu0.itb.hits 497696393 # DTB hits system.cpu0.itb.misses 61377 # DTB misses system.cpu0.itb.accesses 497757770 # DTB accesses -system.cpu0.numCycles 94433643486 # number of cpu cycles simulated +system.cpu0.numCycles 94433641544 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed system.cpu0.committedInsts 497466384 # Number of instructions committed system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses @@ -261,8 +263,8 @@ system.cpu0.num_cc_register_writes 133531045 # nu system.cpu0.num_mem_refs 178459396 # number of memory refs system.cpu0.num_load_insts 92737001 # Number of load instructions system.cpu0.num_store_insts 85722395 # Number of store instructions -system.cpu0.num_idle_cycles 93848339121.288452 # Number of idle cycles -system.cpu0.num_busy_cycles 585304364.711543 # Number of busy cycles +system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles +system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles system.cpu0.Branches 111287587 # Number of branches fetched @@ -301,8 +303,6 @@ system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 585300003 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 15195 # number of quiesce instructions executed system.cpu0.dcache.tags.replacements 6272771 # number of replacements system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 172015771 # Total number of references to valid blocks. @@ -773,9 +773,11 @@ system.cpu1.itb.inst_accesses 478309003 # IT system.cpu1.itb.hits 478248118 # DTB hits system.cpu1.itb.misses 60885 # DTB misses system.cpu1.itb.accesses 478309003 # DTB accesses -system.cpu1.numCycles 94433635490 # number of cpu cycles simulated +system.cpu1.numCycles 94433634550 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed system.cpu1.committedInsts 477990846 # Number of instructions committed system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses @@ -793,8 +795,8 @@ system.cpu1.num_cc_register_writes 126112608 # nu system.cpu1.num_mem_refs 171406825 # number of memory refs system.cpu1.num_load_insts 90251973 # Number of load instructions system.cpu1.num_store_insts 81154852 # Number of store instructions -system.cpu1.num_idle_cycles 93870751219.397461 # Number of idle cycles -system.cpu1.num_busy_cycles 562884270.602548 # Number of busy cycles +system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles +system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles system.cpu1.Branches 106497601 # Number of branches fetched @@ -833,8 +835,6 @@ system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 562879339 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 7199 # number of quiesce instructions executed system.cpu1.dcache.tags.replacements 5945049 # number of replacements system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks. |