diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-19 04:06:21 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-19 04:06:21 -0400 |
| commit | f1c3fda965dd4b28ab6b2e99f5f3210fa2089a17 (patch) | |
| tree | aac69ab2cec4c10204cfc44af082722a3ed98792 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt | |
| parent | 877435950ca2dfb7213dc502e7d9e8374e55e16b (diff) | |
| download | gem5-f1c3fda965dd4b28ab6b2e99f5f3210fa2089a17.tar.xz | |
tests: Recategorise regressions based on run time
This patch takes a first stab at recategorising the regression tests
based on actual run times. The simple-atomic and simple-timing runs of
vortex and twolf all finish in less than 180 s, and they are
consequently moved from long to quick. All realview64 linux-boot
regressions take more than 700 s, and they are therefore moved to
long.
Later patches will rename quick to short, and further divide the
regressions into short, medium and long.
--HG--
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simerr
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/system.terminal
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg => tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out => tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout => tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg => tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out => tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr => tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr
rename : tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout => tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout
rename : tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out => tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/smred.out
rename : tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt => tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini => tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini
rename : tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr => tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr
rename : tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout => tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout
rename : tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out => tests/quick/se/50.vortex/ref/arm/linux/simple-timing/smred.out
rename : tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt => tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout => tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg => tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out => tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr => tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout => tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg => tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out => tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/smred.out
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/se/50.vortex/test.py => tests/quick/se/50.vortex/test.py
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr => tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout => tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout
rename : tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out => tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/smred.out
rename : tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt => tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini => tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr => tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr
rename : tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout => tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout
rename : tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out => tests/quick/se/70.twolf/ref/arm/linux/simple-timing/smred.out
rename : tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt => tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.out
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.out => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.out
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.out => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.out
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pin => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pin
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1 => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2 => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sav => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sav
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2 => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.twf => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.twf
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/se/70.twolf/test.py => tests/quick/se/70.twolf/test.py
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt | 3203 |
1 files changed, 3203 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt new file mode 100644 index 000000000..fb0fbc4a7 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -0,0 +1,3203 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 47.367818 # Number of seconds simulated +sim_ticks 47367817574000 # Number of ticks simulated +final_tick 47367817574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 678056 # Simulator instruction rate (inst/s) +host_op_rate 798173 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38043399524 # Simulator tick rate (ticks/s) +host_mem_usage 751768 # Number of bytes of host memory used +host_seconds 1245.10 # Real time elapsed on the host +sim_insts 844246943 # Number of instructions simulated +sim_ops 993804803 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu0.dtb.walker 36928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 40576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2794548 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9993048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 9568064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 72256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 86016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2509048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 8105888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 7582272 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 437184 # Number of bytes read from this memory +system.physmem.bytes_read::total 41225828 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2794548 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2509048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5303596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 61292480 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory +system.physmem.bytes_written::total 61313296 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 577 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 634 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 84072 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 156163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 149501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1129 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1344 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39292 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 126669 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 118473 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6831 # Number of read requests responded to by this memory +system.physmem.num_reads::total 684685 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 957695 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory +system.physmem.num_writes::total 960298 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 58997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 210967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 201995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 171126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 160072 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 870334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 58997 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 111966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1293969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1294408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1293969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 58997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 211406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 201995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 171127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 160072 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2164742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 684685 # Number of read requests accepted +system.physmem.writeReqs 1596629 # Number of write requests accepted +system.physmem.readBursts 684685 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1596629 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 43802304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17536 # Total number of bytes read from write queue +system.physmem.bytesWritten 99044160 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 41225828 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 102038480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 274 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49035 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 111704 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 42136 # Per bank write bursts +system.physmem.perBankRdBursts::1 44080 # Per bank write bursts +system.physmem.perBankRdBursts::2 34958 # Per bank write bursts +system.physmem.perBankRdBursts::3 41288 # Per bank write bursts +system.physmem.perBankRdBursts::4 39326 # Per bank write bursts +system.physmem.perBankRdBursts::5 49165 # Per bank write bursts +system.physmem.perBankRdBursts::6 40428 # Per bank write bursts +system.physmem.perBankRdBursts::7 47118 # Per bank write bursts +system.physmem.perBankRdBursts::8 36254 # Per bank write bursts +system.physmem.perBankRdBursts::9 81044 # Per bank write bursts +system.physmem.perBankRdBursts::10 36070 # Per bank write bursts +system.physmem.perBankRdBursts::11 40557 # Per bank write bursts +system.physmem.perBankRdBursts::12 34453 # Per bank write bursts +system.physmem.perBankRdBursts::13 38158 # Per bank write bursts +system.physmem.perBankRdBursts::14 37145 # Per bank write bursts +system.physmem.perBankRdBursts::15 42231 # Per bank write bursts +system.physmem.perBankWrBursts::0 97165 # Per bank write bursts +system.physmem.perBankWrBursts::1 99476 # Per bank write bursts +system.physmem.perBankWrBursts::2 95543 # Per bank write bursts +system.physmem.perBankWrBursts::3 98326 # Per bank write bursts +system.physmem.perBankWrBursts::4 92692 # Per bank write bursts +system.physmem.perBankWrBursts::5 102230 # Per bank write bursts +system.physmem.perBankWrBursts::6 96747 # Per bank write bursts +system.physmem.perBankWrBursts::7 98806 # Per bank write bursts +system.physmem.perBankWrBursts::8 93672 # Per bank write bursts +system.physmem.perBankWrBursts::9 100275 # Per bank write bursts +system.physmem.perBankWrBursts::10 92352 # Per bank write bursts +system.physmem.perBankWrBursts::11 96579 # Per bank write bursts +system.physmem.perBankWrBursts::12 94667 # Per bank write bursts +system.physmem.perBankWrBursts::13 97213 # Per bank write bursts +system.physmem.perBankWrBursts::14 92658 # Per bank write bursts +system.physmem.perBankWrBursts::15 99164 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 352 # Number of times write queue was full causing retry +system.physmem.totGap 47367814519500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 43195 # Read request sizes (log2) +system.physmem.readPktSize::3 37 # Read request sizes (log2) +system.physmem.readPktSize::4 5 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 641448 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1324 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 813055 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.690629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 106.318755 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 249.924527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 526198 64.72% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 156067 19.20% 83.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 35208 4.33% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17256 2.12% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12096 1.49% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8107 1.00% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6222 0.77% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5625 0.69% 94.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 46276 5.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 813055 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 73772 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 9.277314 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 118.735455 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 73768 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 73772 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 73772 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.977674 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.369218 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.656514 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 71961 97.55% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 712 0.97% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 29 0.04% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 36 0.05% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 132 0.18% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 174 0.24% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 342 0.46% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 135 0.18% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 19 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 12 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 64 0.09% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 33 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 12 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 4 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 7 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 6 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 10 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 9 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 10 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 15 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 7 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::592-607 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 73772 # Writes before turning the bus around for reads +system.physmem.totQLat 20326500723 # Total ticks spent queuing +system.physmem.totMemAccLat 33159206973 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3422055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29699.26 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 48449.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.87 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.15 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing +system.physmem.readRowHits 509481 # Number of row buffer hits during reads +system.physmem.writeRowHits 909439 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes +system.physmem.avgGap 20763390.98 # Average gap between requests +system.physmem.pageHitRate 63.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3169991160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1729657875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2640253200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5060782800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1178038765890 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27387322041000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31671796931685 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.635370 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45560807372172 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581715460000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 225294290828 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 2976704640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1624194000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2698113600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4967438400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1169320459140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27394969678500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31670392028040 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.605711 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45573545582628 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581715460000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 212554603622 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 95467 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 95467 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8616 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72889 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 95458 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.225230 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 69.587670 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 95457 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::20480-22527 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 95458 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 81514 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 17324.683490 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15769.335506 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 10694.107977 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 81100 99.49% 99.49% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 359 0.44% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 15 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 81514 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1873275212 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.115454 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -216276296 -11.55% -11.55% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 2089551508 111.55% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1873275212 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 72890 89.43% 89.43% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8616 10.57% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 81506 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 95467 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 95467 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81506 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81506 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 176973 # Table walker requests started/completed, data/inst +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 81219280 # DTB read hits +system.cpu0.dtb.read_misses 71070 # DTB read misses +system.cpu0.dtb.write_hits 73504932 # DTB write hits +system.cpu0.dtb.write_misses 24397 # DTB write misses +system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 38298 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 4007 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 10240 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 81290350 # DTB read accesses +system.cpu0.dtb.write_accesses 73529329 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 154724212 # DTB hits +system.cpu0.dtb.misses 95467 # DTB misses +system.cpu0.dtb.accesses 154819679 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 56383 # Table walker walks requested +system.cpu0.itb.walker.walksLong 56383 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 751 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50468 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 56383 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 56383 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 56383 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 51219 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 19351.129327 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17618.924664 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 12629.312385 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 47792 93.31% 93.31% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2988 5.83% 99.14% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 157 0.31% 99.45% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 221 0.43% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 4 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 51219 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 50468 98.53% 98.53% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 751 1.47% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 51219 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56383 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56383 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51219 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51219 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 107602 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 434853798 # ITB inst hits +system.cpu0.itb.inst_misses 56383 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26912 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 434910181 # ITB inst accesses +system.cpu0.itb.hits 434853798 # DTB hits +system.cpu0.itb.misses 56383 # DTB misses +system.cpu0.itb.accesses 434910181 # DTB accesses +system.cpu0.numCycles 94735635148 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 434594659 # Number of instructions committed +system.cpu0.committedOps 509819268 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 468245604 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 368958 # Number of float alu accesses +system.cpu0.num_func_calls 25685063 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 65742912 # number of instructions that are conditional controls +system.cpu0.num_int_insts 468245604 # number of integer instructions +system.cpu0.num_fp_insts 368958 # number of float instructions +system.cpu0.num_int_register_reads 681605000 # number of times the integer registers were read +system.cpu0.num_int_register_writes 371986080 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 629019 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 237888 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 113785122 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 113402508 # number of times the CC registers were written +system.cpu0.num_mem_refs 154715442 # number of memory refs +system.cpu0.num_load_insts 81215665 # Number of load instructions +system.cpu0.num_store_insts 73499777 # Number of store instructions +system.cpu0.num_idle_cycles 93677942540.842026 # Number of idle cycles +system.cpu0.num_busy_cycles 1057692607.157978 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011165 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988835 # Percentage of idle cycles +system.cpu0.Branches 96525602 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 354149041 69.42% 69.42% # Class of executed instruction +system.cpu0.op_class::IntMult 1173113 0.23% 69.65% # Class of executed instruction +system.cpu0.op_class::IntDiv 59997 0.01% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 23937 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::MemRead 81215665 15.92% 85.59% # Class of executed instruction +system.cpu0.op_class::MemWrite 73499777 14.41% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 510121531 # Class of executed instruction +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 13974 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 5284481 # number of replacements +system.cpu0.dcache.tags.tagsinuse 474.292500 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 149186915 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5284993 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.228404 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4077089500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 474.292500 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.926353 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.926353 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 314708854 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 314708854 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75740068 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75740068 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69444390 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69444390 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177454 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 177454 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 143100 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 143100 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1662300 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1662300 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1634095 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1634095 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 145184458 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 145184458 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 145361912 # number of overall hits +system.cpu0.dcache.overall_hits::total 145361912 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2820396 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 2820396 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1320543 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1320543 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 635767 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 635767 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 746024 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 746024 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156072 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 182947 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 182947 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4140939 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4140939 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4776706 # number of overall misses +system.cpu0.dcache.overall_misses::total 4776706 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39561901741 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39561901741 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24338572363 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24338572363 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30943018074 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30943018074 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2147538753 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2147538753 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3961701456 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3961701456 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1248500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1248500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 63900474104 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 63900474104 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 63900474104 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 63900474104 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78560464 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78560464 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 70764933 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 70764933 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 813221 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 813221 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 889124 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 889124 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1818372 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1818372 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1817042 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1817042 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 149325397 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 149325397 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 150138618 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 150138618 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.035901 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.035901 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018661 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018661 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781789 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781789 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839055 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839055 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085831 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085831 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100684 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100684 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027731 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027731 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14027.073411 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14027.073411 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18430.730664 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18430.730664 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41477.242118 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41477.242118 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13759.923324 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13759.923324 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21654.913478 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21654.913478 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15431.397107 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15431.397107 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13377.518755 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13377.518755 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 3634622 # number of writebacks +system.cpu0.dcache.writebacks::total 3634622 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28612 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 28612 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21357 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21357 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 38145 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 38145 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 49969 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 49969 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 49969 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 49969 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2791784 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2791784 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1299186 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1299186 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 630147 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 630147 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 746024 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 746024 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117927 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 117927 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 182947 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 182947 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4090970 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4090970 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4721117 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4721117 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34314944268 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 34314944268 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 21777665637 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21777665637 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12432309289 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12432309289 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29820271426 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 29820271426 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1422971246 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1422971246 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3676791544 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3676791544 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1208000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1208000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 56092609905 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 56092609905 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 68524919194 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 68524919194 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4525228998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4525228998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4129291250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4129291250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8654520248 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8654520248 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035537 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035537 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774878 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774878 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839055 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839055 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064853 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064853 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100684 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100684 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027396 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027396 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031445 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031445 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12291.403729 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12291.403729 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16762.546423 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16762.546423 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19729.220783 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19729.220783 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39972.268219 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39972.268219 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12066.543251 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12066.543251 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20097.577681 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20097.577681 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13711.322719 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13711.322719 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14514.556448 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14514.556448 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 4499955 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.899412 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 430353331 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4500467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 95.624150 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 33435593250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.899412 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999804 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 874208063 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 874208063 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 430353331 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 430353331 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 430353331 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 430353331 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 430353331 # number of overall hits +system.cpu0.icache.overall_hits::total 430353331 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4500467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4500467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4500467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4500467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4500467 # number of overall misses +system.cpu0.icache.overall_misses::total 4500467 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47768563979 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 47768563979 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 47768563979 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 47768563979 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 47768563979 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 47768563979 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 434853798 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 434853798 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 434853798 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 434853798 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 434853798 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 434853798 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010349 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010349 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010349 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010349 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010349 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010349 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10614.134928 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10614.134928 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10614.134928 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10614.134928 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4500467 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4500467 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4500467 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4500467 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4500467 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4500467 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 43254050535 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 43254050535 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 43254050535 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 43254050535 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 43254050535 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 43254050535 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3811870500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 3811870500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010349 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010349 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010349 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9611.013820 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7625512 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7625539 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 975949 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2276475 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16164.000425 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 9930056 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2292579 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.331391 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5342662500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 7643.384526 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.376858 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 75.669060 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3718.900652 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3598.062438 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1070.606892 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.466515 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003502 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004618 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.226984 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.219608 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.065345 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.986572 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1394 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14660 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 18 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 592 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 515 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 17 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 69 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 157112514 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11720586224 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 30250591936 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 42306600924 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 157112514 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11720586224 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 30250591936 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 65337441291 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4307274002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7775525002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3933705500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3933705500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 8240979502 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11709230502 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.248646 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.168188 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.766299 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.766299 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.553879 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.553879 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.832725 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.832725 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205169 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205169 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.172480 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.239706 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 24493.654964 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23901.499212 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 36215.315810 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42441.441675 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42441.441675 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20873.741897 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20873.741897 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15129.520789 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15129.520789 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 335166.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 335166.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38586.013882 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38586.013882 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25928.818372 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28813.655266 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.toL2Bus.trans_dist::ReadReq 10272423 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 8656546 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26078 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26078 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3634622 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 896357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1072966 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 744713 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 432357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330872 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 471310 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1218200 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1108311 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9087184 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15490281 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 297199 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 469779 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 25344443 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 288202388 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 584369767 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1031640 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1541304 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 875145099 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 3727007 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 17787477 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.192426 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.394206 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 14364709 80.76% 80.76% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 3422768 19.24% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 17787477 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 11622970748 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 201159488 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 6810939722 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 7629819592 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 168326514 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 277196500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 92509 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 92509 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6608 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 71644 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 92500 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.081081 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 24.659848 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 92499 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 92500 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 78261 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 18926.409693 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17150.140934 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13619.258696 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 77412 98.92% 98.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 724 0.93% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.04% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 50 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 78261 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2425306712 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.143168 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 2078081352 85.68% 85.68% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 347225360 14.32% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2425306712 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 71644 91.56% 91.56% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 6608 8.44% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 78252 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92509 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92509 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 78252 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 78252 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 170761 # Table walker requests started/completed, data/inst +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 78277454 # DTB read hits +system.cpu1.dtb.read_misses 68245 # DTB read misses +system.cpu1.dtb.write_hits 71517077 # DTB write hits +system.cpu1.dtb.write_misses 24264 # DTB write misses +system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 32777 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 3876 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 8314 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 78345699 # DTB read accesses +system.cpu1.dtb.write_accesses 71541341 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 149794531 # DTB hits +system.cpu1.dtb.misses 92509 # DTB misses +system.cpu1.dtb.accesses 149887040 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 60524 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60524 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 415 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54985 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60524 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60524 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60524 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 55400 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21598.519856 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19393.747052 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17485.706336 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 51757 93.42% 93.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2619 4.73% 98.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 338 0.61% 98.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 537 0.97% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 37 0.07% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 28 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 55400 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 2054805852 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2054805852 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 2054805852 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54985 99.25% 99.25% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 415 0.75% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55400 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60524 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60524 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 115924 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 409921957 # ITB inst hits +system.cpu1.itb.inst_misses 60524 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 23091 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 409982481 # ITB inst accesses +system.cpu1.itb.hits 409921957 # DTB hits +system.cpu1.itb.misses 60524 # DTB misses +system.cpu1.itb.accesses 409982481 # DTB accesses +system.cpu1.numCycles 94735635148 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 409652284 # Number of instructions committed +system.cpu1.committedOps 483985535 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 446181756 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 565626 # Number of float alu accesses +system.cpu1.num_func_calls 25682090 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 61510479 # number of instructions that are conditional controls +system.cpu1.num_int_insts 446181756 # number of integer instructions +system.cpu1.num_fp_insts 565626 # number of float instructions +system.cpu1.num_int_register_reads 638057436 # number of times the integer registers were read +system.cpu1.num_int_register_writes 352717621 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 886208 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 535956 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 102771786 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 102542500 # number of times the CC registers were written +system.cpu1.num_mem_refs 149782083 # number of memory refs +system.cpu1.num_load_insts 78271508 # Number of load instructions +system.cpu1.num_store_insts 71510575 # Number of store instructions +system.cpu1.num_idle_cycles 93767065494.048019 # Number of idle cycles +system.cpu1.num_busy_cycles 968569653.951980 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010224 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989776 # Percentage of idle cycles +system.cpu1.Branches 91673037 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 333338821 68.84% 68.84% # Class of executed instruction +system.cpu1.op_class::IntMult 986884 0.20% 69.04% # Class of executed instruction +system.cpu1.op_class::IntDiv 58271 0.01% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 89216 0.02% 69.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.07% # Class of executed instruction +system.cpu1.op_class::MemRead 78271508 16.16% 85.23% # Class of executed instruction +system.cpu1.op_class::MemWrite 71510575 14.77% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 484255317 # Class of executed instruction +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 5204 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 4752540 # number of replacements +system.cpu1.dcache.tags.tagsinuse 455.880794 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 144856637 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4753051 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.476559 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8382286333500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.880794 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890392 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.890392 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 304369060 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 304369060 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 73044937 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 73044937 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 67886662 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 67886662 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184038 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 184038 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 188938 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 188938 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1611925 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1611925 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1592857 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1592857 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 140931599 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 140931599 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 141115637 # number of overall hits +system.cpu1.dcache.overall_hits::total 141115637 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2767627 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2767627 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1154762 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1154762 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 498783 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 498783 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 496292 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 496292 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158321 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 158321 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 176268 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 176268 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 3922389 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 3922389 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4421172 # number of overall misses +system.cpu1.dcache.overall_misses::total 4421172 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 37645623046 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 37645623046 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19534966036 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 19534966036 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11881656902 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11881656902 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2306877268 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2306877268 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3770896575 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3770896575 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1887000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1887000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 57180589082 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 57180589082 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 57180589082 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 57180589082 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 75812564 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 75812564 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 69041424 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 69041424 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 682821 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 682821 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685230 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 685230 # 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miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016726 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.016726 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.730474 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.730474 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.724271 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.724271 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089434 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089434 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099636 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099636 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027078 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027078 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030378 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.030378 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13602.130289 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13602.130289 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16916.876409 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16916.876409 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 23940.859216 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 23940.859216 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14570.886162 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14570.886162 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21392.973058 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21392.973058 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14578.000571 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14578.000571 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12933.355473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12933.355473 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 3063492 # number of writebacks +system.cpu1.dcache.writebacks::total 3063492 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11545 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 11545 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 352 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 352 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46682 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46682 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 11897 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 11897 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 11897 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 11897 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2756082 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2756082 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1154410 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1154410 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 498783 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 498783 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 496292 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 496292 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 111639 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 111639 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 176268 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 176268 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 3910492 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 3910492 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4409275 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4409275 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 32859790378 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 32859790378 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 17743172214 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 17743172214 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9770846491 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 9770846491 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11134079098 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11134079098 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1396307998 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1396307998 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3498646925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498646925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1819500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1819500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 50602962592 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 50602962592 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60373809083 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 60373809083 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1936116751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1936116751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2164016499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2164016499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4100133250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4100133250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036354 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036354 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016721 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016721 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.730474 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.730474 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.724271 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.724271 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063064 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063064 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099636 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099636 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026996 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026996 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030297 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030297 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11922.646125 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11922.646125 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15369.905158 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15369.905158 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19589.373517 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19589.373517 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22434.532690 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22434.532690 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12507.349564 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12507.349564 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19848.451931 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19848.451931 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12940.305873 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12940.305873 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13692.457169 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13692.457169 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 5523110 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.341944 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 404398330 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5523622 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 73.212528 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8382258847250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.341944 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969418 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969418 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 825367541 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 825367541 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 404398330 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 404398330 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 404398330 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 404398330 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 404398330 # number of overall hits +system.cpu1.icache.overall_hits::total 404398330 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5523627 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5523627 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5523627 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5523627 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5523627 # number of overall misses +system.cpu1.icache.overall_misses::total 5523627 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54612807078 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 54612807078 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 54612807078 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 54612807078 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 54612807078 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 54612807078 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 409921957 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 409921957 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 409921957 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 409921957 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 409921957 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 409921957 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013475 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013475 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013475 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013475 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013475 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013475 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9887.127983 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9887.127983 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9887.127983 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9887.127983 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 49075741422 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49075741422 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 49075741422 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9805750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9805750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9805750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9805750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013475 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013475 # 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Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 821.871120 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.316573 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004311 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005424 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.231268 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.210756 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050163 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.818494 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1616 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14027 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 744 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 601 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 43 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6290 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5121 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.098633 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.856140 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 229858181 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 229858181 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 196843 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 146711 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5082589 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 2590406 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 8016549 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3063492 # 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number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 205973 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 154312 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5523627 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3366504 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 9250416 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3063492 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3063492 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 494732 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 494732 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 171283 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 171283 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 176263 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 176263 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 984957 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 984957 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 205973 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 154312 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5523627 # 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miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.133385 # miss rate for ReadReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.464080 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.464080 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.703753 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.703753 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.839473 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.839473 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210721 # 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miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36132.285094 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30056.060185 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 30693.930732 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30505.347555 # average ReadReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 913.073525 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 913.073525 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21316.346587 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21316.346587 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20792.295909 # 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average number of cycles each access was blocked +system.cpu1.l2cache.fast_writes 0 # number of fast writes performed +system.cpu1.l2cache.cache_copies 0 # number of cache copies performed +system.cpu1.l2cache.writebacks::writebacks 764216 # number of writebacks +system.cpu1.l2cache.writebacks::total 764216 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 323 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 2534 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 2534 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 2857 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 2857 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 2857 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 2857 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9130 # 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number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 17727784992 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7402905507 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7402905507 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2380480811 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2380480811 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2176947075 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2176947075 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1480998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1480998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6436785468 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6436785468 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 224849501 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 10375497328 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 25150532637 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 35978720718 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 224849501 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 10375497328 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 25150532637 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 53706505710 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8938250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1841380999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1850319249 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2067303001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2067303001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8938250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3908684000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3917622250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.230439 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.133350 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.464080 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.464080 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.703753 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.703753 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.839473 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.839473 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.208148 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.208148 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140548 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191832 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24122.647893 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23948.829754 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33772.870485 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32243.321967 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32243.321967 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19748.308136 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19748.308136 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14712.282892 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14712.282892 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296199.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296199.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31396.349903 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31396.349903 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25010.215568 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27352.810917 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.trans_dist::ReadReq 11346555 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9442060 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 12895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 12895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3063492 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 747367 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1164315 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 494732 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 387368 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 328581 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 412328 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1123330 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 992188 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11047474 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13661084 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 335346 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 476365 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 25520269 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353512568 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 512414548 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1234496 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1647784 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 868809396 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4168573 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 18149089 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.215812 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.411385 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 14232289 78.42% 78.42% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 3916800 21.58% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 18149089 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 10693279996 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 176128990 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 8292291078 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 7012668647 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 181227501 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 270567252 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40336 # Transaction distribution +system.iobus.trans_dist::ReadResp 40336 # Transaction distribution +system.iobus.trans_dist::WriteReq 136623 # Transaction distribution +system.iobus.trans_dist::WriteResp 29895 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122628 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155735 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7496677 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36212000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 607542087 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 92736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 148516061 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115606 # number of replacements +system.iocache.tags.tagsinuse 11.280528 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115622 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 9179145722000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.421794 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.858734 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463862 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.241171 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705033 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 1040802 # Number of tag accesses +system.iocache.tags.data_accesses 1040802 # Number of data accesses +system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses +system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses +system.iocache.WriteReq_misses::total 3 # number of WriteReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses +system.iocache.demand_misses::total 8917 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ethernet 40 # number of overall misses +system.iocache.overall_misses::realview.ide 8877 # number of overall misses +system.iocache.overall_misses::total 8917 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1629440754 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1634636254 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19888935272 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19888935272 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1629440754 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1635005254 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1629440754 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1635005254 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183557.593106 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183378.534216 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186351.615996 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186351.615996 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183358.220702 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183358.220702 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110662 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16220 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.822565 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106699 # number of writebacks +system.iocache.writebacks::total 106699 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1166654804 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1169925304 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14339007344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14339007344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1166654804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1170138304 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1166654804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1170138304 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131424.445646 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 131245.827238 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134350.942058 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134350.942058 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 1063912 # number of replacements +system.l2c.tags.tagsinuse 64178.177670 # Cycle average of tags in use +system.l2c.tags.total_refs 3766892 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1123413 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.353079 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 11093199000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 24092.358885 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 75.949373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 107.097830 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4212.805606 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 7550.293396 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7226.795277 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 149.211397 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 222.509709 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4405.039325 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 7865.744621 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8270.372252 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.367620 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001159 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.001634 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.064282 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.115208 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.110272 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002277 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003395 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.067216 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.120022 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.126196 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.979281 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172689 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.182588 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759197 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.477347 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.679626 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.605334 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.632275 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.617082 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.621773 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.611004 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.617104 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573401 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486396 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.534643 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.205409 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.205409 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 77325.734556 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75217.333798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 91240.104337 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32418.974964 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31451.308706 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32227.094697 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17780.279250 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17794.118065 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.462483 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17815.791525 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17872.145516 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.981482 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74622.680148 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69151.437191 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72405.364770 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 622157 # Transaction distribution +system.membus.trans_dist::ReadResp 622157 # Transaction distribution +system.membus.trans_dist::WriteReq 38973 # Transaction distribution +system.membus.trans_dist::WriteResp 38973 # Transaction distribution +system.membus.trans_dist::Writeback 957695 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 636331 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 636331 # Transaction distribution +system.membus.trans_dist::UpgradeReq 382471 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 288753 # Transaction distribution +system.membus.trans_dist::UpgradeResp 111723 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution +system.membus.trans_dist::ReadExReq 123220 # Transaction distribution +system.membus.trans_dist::ReadExResp 104410 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122628 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28184 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4073596 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4224500 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4560403 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155735 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129167796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 129380103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14096512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 143476615 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 581158 # Total snoops (count) +system.membus.snoop_fanout::samples 2928688 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 2928688 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2928688 # Request fanout histogram +system.membus.reqLayer0.occupancy 100579500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 24544499 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 9168550783 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 4323654540 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 151928439 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 3783137 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3775909 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38973 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38973 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2047649 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 890925 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 784014 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 429633 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 300246 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 729879 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258637 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258637 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 6917142 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4903000 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 11820142 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229102843 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 151634764 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 380737607 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1518303 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7628101 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.015184 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.122286 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 7512273 98.48% 98.48% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115828 1.52% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7628101 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 6924291534 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 2530500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 3796276244 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 3095093071 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |