diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
| commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
| tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual | |
| parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
| download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual')
5 files changed, 3264 insertions, 2902 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini index 2e70349df..2a00a6a90 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -24,12 +25,12 @@ exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -59,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -87,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -105,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -122,6 +135,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -140,12 +157,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -164,8 +186,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -188,9 +215,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -204,9 +236,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[3] @@ -217,12 +254,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -241,8 +283,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -300,9 +347,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -316,9 +368,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[2] @@ -329,12 +386,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu0.l2cache.prefetcher response_latency=12 @@ -352,6 +414,7 @@ mem_side=system.toL2Bus.slave[0] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -362,6 +425,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -378,8 +445,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -387,10 +459,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 @@ -418,6 +495,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -435,6 +513,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -453,12 +535,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -477,8 +564,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -501,9 +593,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -517,9 +614,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[3] @@ -530,12 +632,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -554,8 +661,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -613,9 +725,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -629,9 +746,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[2] @@ -642,12 +764,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu1.l2cache.prefetcher response_latency=12 @@ -665,6 +792,7 @@ mem_side=system.toL2Bus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -675,6 +803,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -691,8 +823,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -700,10 +837,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 @@ -748,9 +890,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -764,12 +911,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -788,8 +940,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -800,12 +957,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -824,21 +986,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -850,11 +1022,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -865,6 +1042,13 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl IDD0=0.075000 @@ -899,6 +1083,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -910,7 +1095,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -953,10 +1142,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1037,14 +1231,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1053,13 +1252,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1069,6 +1273,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1139,10 +1344,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1222,17 +1432,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1258,12 +1473,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1271,14 +1492,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1364,14 +1590,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1380,13 +1611,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1395,13 +1631,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1409,11 +1650,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1427,11 +1673,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1445,19 +1696,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1503,14 +1760,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1519,11 +1791,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1533,21 +1810,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1557,12 +1844,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1571,10 +1863,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1584,12 +1881,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1599,26 +1901,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1627,10 +1939,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1638,10 +1955,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1649,21 +1971,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1677,11 +2009,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1692,11 +2029,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1704,10 +2046,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -1723,10 +2070,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr index 3c2cf37c0..8786c1b6c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr @@ -3,6 +3,8 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout index f29d24301..c648cad5f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout @@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 21:26:42 -gem5 started Mar 15 2016 21:52:28 -gem5 executing on phenom, pid 15986 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:41:50 +gem5 executing on e108600-lin, pid 23131 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47460623015500 because m5_exit instruction encountered +Exiting @ tick 47403574916500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 7576c0a8a..815a8f351 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.522770 # Number of seconds simulated -sim_ticks 47522770414500 # Number of ticks simulated -final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.403575 # Number of seconds simulated +sim_ticks 47403574916500 # Number of ticks simulated +final_tick 47403574916500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 594104 # Simulator instruction rate (inst/s) -host_op_rate 698838 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32027606991 # Simulator tick rate (ticks/s) -host_mem_usage 752504 # Number of bytes of host memory used -host_seconds 1483.81 # Real time elapsed on the host -sim_insts 881535802 # Number of instructions simulated -sim_ops 1036940641 # Number of ops (including micro ops) simulated +host_inst_rate 473223 # Simulator instruction rate (inst/s) +host_op_rate 556671 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25492174892 # Simulator tick rate (ticks/s) +host_mem_usage 749540 # Number of bytes of host memory used +host_seconds 1859.53 # Real time elapsed on the host +sim_insts 879974755 # Number of instructions simulated +sim_ops 1035148021 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 93760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 96448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3323828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13811400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 14713664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 137344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 135424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2499960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9313680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12080896 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 425472 # Number of bytes read from this memory -system.physmem.bytes_read::total 56631876 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3323828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2499960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5823788 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75221696 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 121792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 126720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3082292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13718664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15413504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 111872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 105344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2806840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9358928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 11301824 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428736 # Number of bytes read from this memory +system.physmem.bytes_read::total 56576516 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3082292 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2806840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5889132 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75184384 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 75242280 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1465 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1507 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 92342 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 215816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 229901 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2146 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2116 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 39150 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 145539 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 188764 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6648 # Number of read requests responded to by this memory -system.physmem.num_reads::total 925394 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1175339 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 75204968 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1903 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 88568 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 214367 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 240836 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1748 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 43945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 146246 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 176591 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6699 # Number of read requests responded to by this memory +system.physmem.num_reads::total 924529 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1174756 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1177913 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 69942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 290627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 309613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 195984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 254213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1191679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69942 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52606 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 122547 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1582856 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1177330 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 65022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 289401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 325155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 197431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 238417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1193507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 65022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59212 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 124234 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1586049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1583289 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1582856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2030 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 291060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 309613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 195984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 254213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2774968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 925394 # Number of read requests accepted -system.physmem.writeReqs 1177913 # Number of write requests accepted -system.physmem.readBursts 925394 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1177913 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59200512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 24704 # Total number of bytes read from write queue -system.physmem.bytesWritten 75241664 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56631876 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 75242280 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 386 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1586483 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1586049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 65022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 289836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 325155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 197431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 238417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2779990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 924529 # Number of read requests accepted +system.physmem.writeReqs 1177330 # Number of write requests accepted +system.physmem.readBursts 924529 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1177330 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59142848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 27008 # Total number of bytes read from write queue +system.physmem.bytesWritten 75203008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56576516 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 75204968 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 422 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2259 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 52385 # Per bank write bursts -system.physmem.perBankRdBursts::1 62471 # Per bank write bursts -system.physmem.perBankRdBursts::2 52469 # Per bank write bursts -system.physmem.perBankRdBursts::3 57006 # Per bank write bursts -system.physmem.perBankRdBursts::4 52192 # Per bank write bursts -system.physmem.perBankRdBursts::5 61065 # Per bank write bursts -system.physmem.perBankRdBursts::6 52770 # Per bank write bursts -system.physmem.perBankRdBursts::7 53841 # Per bank write bursts -system.physmem.perBankRdBursts::8 49119 # Per bank write bursts -system.physmem.perBankRdBursts::9 95933 # Per bank write bursts -system.physmem.perBankRdBursts::10 50791 # Per bank write bursts -system.physmem.perBankRdBursts::11 57135 # Per bank write bursts -system.physmem.perBankRdBursts::12 57588 # Per bank write bursts -system.physmem.perBankRdBursts::13 62036 # Per bank write bursts -system.physmem.perBankRdBursts::14 54549 # Per bank write bursts -system.physmem.perBankRdBursts::15 53658 # Per bank write bursts -system.physmem.perBankWrBursts::0 70290 # Per bank write bursts -system.physmem.perBankWrBursts::1 77699 # Per bank write bursts -system.physmem.perBankWrBursts::2 70837 # Per bank write bursts -system.physmem.perBankWrBursts::3 75524 # Per bank write bursts -system.physmem.perBankWrBursts::4 70767 # Per bank write bursts -system.physmem.perBankWrBursts::5 75365 # Per bank write bursts -system.physmem.perBankWrBursts::6 70544 # Per bank write bursts -system.physmem.perBankWrBursts::7 72537 # Per bank write bursts -system.physmem.perBankWrBursts::8 71114 # Per bank write bursts -system.physmem.perBankWrBursts::9 74364 # Per bank write bursts -system.physmem.perBankWrBursts::10 70757 # Per bank write bursts -system.physmem.perBankWrBursts::11 75591 # Per bank write bursts -system.physmem.perBankWrBursts::12 74466 # Per bank write bursts -system.physmem.perBankWrBursts::13 78806 # Per bank write bursts -system.physmem.perBankWrBursts::14 73579 # Per bank write bursts -system.physmem.perBankWrBursts::15 73411 # Per bank write bursts +system.physmem.perBankRdBursts::0 51848 # Per bank write bursts +system.physmem.perBankRdBursts::1 60547 # Per bank write bursts +system.physmem.perBankRdBursts::2 52943 # Per bank write bursts +system.physmem.perBankRdBursts::3 59873 # Per bank write bursts +system.physmem.perBankRdBursts::4 53995 # Per bank write bursts +system.physmem.perBankRdBursts::5 59394 # Per bank write bursts +system.physmem.perBankRdBursts::6 55656 # Per bank write bursts +system.physmem.perBankRdBursts::7 56350 # Per bank write bursts +system.physmem.perBankRdBursts::8 47470 # Per bank write bursts +system.physmem.perBankRdBursts::9 98045 # Per bank write bursts +system.physmem.perBankRdBursts::10 51346 # Per bank write bursts +system.physmem.perBankRdBursts::11 58216 # Per bank write bursts +system.physmem.perBankRdBursts::12 52575 # Per bank write bursts +system.physmem.perBankRdBursts::13 60842 # Per bank write bursts +system.physmem.perBankRdBursts::14 50185 # Per bank write bursts +system.physmem.perBankRdBursts::15 54822 # Per bank write bursts +system.physmem.perBankWrBursts::0 69717 # Per bank write bursts +system.physmem.perBankWrBursts::1 76530 # Per bank write bursts +system.physmem.perBankWrBursts::2 71410 # Per bank write bursts +system.physmem.perBankWrBursts::3 77292 # Per bank write bursts +system.physmem.perBankWrBursts::4 71372 # Per bank write bursts +system.physmem.perBankWrBursts::5 75019 # Per bank write bursts +system.physmem.perBankWrBursts::6 75211 # Per bank write bursts +system.physmem.perBankWrBursts::7 75617 # Per bank write bursts +system.physmem.perBankWrBursts::8 67898 # Per bank write bursts +system.physmem.perBankWrBursts::9 76939 # Per bank write bursts +system.physmem.perBankWrBursts::10 70016 # Per bank write bursts +system.physmem.perBankWrBursts::11 75357 # Per bank write bursts +system.physmem.perBankWrBursts::12 71664 # Per bank write bursts +system.physmem.perBankWrBursts::13 78615 # Per bank write bursts +system.physmem.perBankWrBursts::14 70257 # Per bank write bursts +system.physmem.perBankWrBursts::15 72133 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 43 # Number of times write queue was full causing retry -system.physmem.totGap 47522767065000 # Total gap between requests +system.physmem.numWrRetry 33 # Number of times write queue was full causing retry +system.physmem.totGap 47403571626000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 882169 # Read request sizes (log2) +system.physmem.readPktSize::6 881304 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1175339 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 655692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 79783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38713 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28749 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 22122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2679 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1174756 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 659566 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 77579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 24996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 21849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -189,171 +189,169 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 50193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 64392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 71615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 71812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 75238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 77530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 73364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 73677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 78266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 71127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 65923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 126 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 971842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 138.337154 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 95.235739 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 185.809364 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 667325 68.67% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 188611 19.41% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 42123 4.33% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 19056 1.96% 94.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13469 1.39% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8562 0.88% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6056 0.62% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5131 0.53% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21509 2.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 971842 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.162244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 130.580515 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61004 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 31459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 50403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 64323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 68725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 71220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 71835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 75432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 77625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 73262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 73463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 77885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 70974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 65826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 63695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 970623 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 138.411655 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 95.318742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 185.703174 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 665453 68.56% 68.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 189210 19.49% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 42199 4.35% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 19114 1.97% 94.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13470 1.39% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8660 0.89% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6031 0.62% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4990 0.51% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21496 2.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 970623 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60964 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.158028 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 130.577791 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60961 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61007 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.270756 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.528593 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.773323 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49057 80.41% 80.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4844 7.94% 88.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 2913 4.77% 93.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1752 2.87% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 961 1.58% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 299 0.49% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 177 0.29% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 148 0.24% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 74 0.12% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 52 0.09% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 27 0.04% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 55 0.09% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 405 0.66% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 51 0.08% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 50 0.08% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 40 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 25 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60964 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60964 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.274441 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.533375 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.742081 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49066 80.48% 80.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4709 7.72% 88.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2977 4.88% 93.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1753 2.88% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 988 1.62% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 316 0.52% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 174 0.29% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 124 0.20% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 67 0.11% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 44 0.07% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 37 0.06% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 48 0.08% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 425 0.70% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 48 0.08% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 48 0.08% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 40 0.07% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 26 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 8 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 8 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61007 # Writes before turning the bus around for reads -system.physmem.totQLat 29196891613 # Total ticks spent queuing -system.physmem.totMemAccLat 46540791613 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4625040000 # Total ticks spent in databus transfers -system.physmem.avgQLat 31563.93 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 10 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 27 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60964 # Writes before turning the bus around for reads +system.physmem.totQLat 29056215697 # Total ticks spent queuing +system.physmem.totMemAccLat 46383221947 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4620535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 31442.48 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 50313.93 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 50192.48 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing -system.physmem.readRowHits 690198 # Number of row buffer hits during reads -system.physmem.writeRowHits 438618 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.31 # Row buffer hit rate for writes -system.physmem.avgGap 22594308.42 # Average gap between requests -system.physmem.pageHitRate 53.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3631876920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1981678875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3464752200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3781488240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3103956292320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1186873055955 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27472545160500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31776234305010 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.652826 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45702691627494 # Time in different power states -system.physmem_0.memoryStateTime::REF 1586889720000 # Time in different power states +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.95 # Average write queue length when enqueuing +system.physmem.readRowHits 688543 # Number of row buffer hits during reads +system.physmem.writeRowHits 439987 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 37.44 # Row buffer hit rate for writes +system.physmem.avgGap 22553164.43 # Average gap between requests +system.physmem.pageHitRate 53.76 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3707333280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2022850500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3514687800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3837248640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1188225117900 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27399839328750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31697317314150 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.669411 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45581711195731 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582909380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 233188460006 # Time in different power states +system.physmem_0.memoryStateTime::ACT 238953890769 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3715248600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2027169375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3750271200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3836730240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3103956292320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1194406095015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27465937231500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31777629038250 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.682174 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45691606890492 # Time in different power states -system.physmem_1.memoryStateTime::REF 1586889720000 # Time in different power states +system.physmem_1.actEnergy 3630576600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1980969375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3693307800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3777055920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1193695955100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27395040340500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31697988952575 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.683580 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45573641620138 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582909380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 244273354008 # Time in different power states +system.physmem_1.memoryStateTime::ACT 247019106112 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -380,9 +378,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -390,7 +388,7 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -420,75 +418,75 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 111522 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 111522 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12043 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84023 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 24 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 111498 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.224219 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 74.869765 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 111497 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 114038 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 114038 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12642 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85549 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 114019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.228032 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 76.998938 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 114018 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 111498 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 96090 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22204.527006 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 20954.891968 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 12694.708371 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 91679 95.41% 95.41% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3478 3.62% 99.03% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 141 0.15% 99.18% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 658 0.68% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 17 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 14 0.01% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 32 0.03% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 16 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 20 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 23 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 114019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 98210 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22487.465635 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21018.091466 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14315.982425 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 93486 95.19% 95.19% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3452 3.51% 98.70% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 155 0.16% 98.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 934 0.95% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 20 0.02% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 48 0.05% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 12 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 37 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 30 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 96090 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 2194735056 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.089935 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -197382796 -8.99% -8.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 2392117852 108.99% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 2194735056 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 84024 87.46% 87.46% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 12043 12.54% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 96067 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 111522 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 98210 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 3576910072 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.522403 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -1868589580 -52.24% -52.24% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 5445499652 152.24% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 3576910072 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 85549 87.13% 87.13% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 12642 12.87% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 98191 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 114038 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 111522 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96067 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 114038 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 98191 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96067 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 207589 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 98191 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 212229 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 86856517 # DTB read hits -system.cpu0.dtb.read_misses 84644 # DTB read misses -system.cpu0.dtb.write_hits 78666499 # DTB write hits -system.cpu0.dtb.write_misses 26878 # DTB write misses +system.cpu0.dtb.read_hits 86092375 # DTB read hits +system.cpu0.dtb.read_misses 87013 # DTB read misses +system.cpu0.dtb.write_hits 77928513 # DTB write hits +system.cpu0.dtb.write_misses 27025 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37412 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 38112 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4693 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4351 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9143 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 86941161 # DTB read accesses -system.cpu0.dtb.write_accesses 78693377 # DTB write accesses +system.cpu0.dtb.perms_faults 9561 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 86179388 # DTB read accesses +system.cpu0.dtb.write_accesses 77955538 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 165523016 # DTB hits -system.cpu0.dtb.misses 111522 # DTB misses -system.cpu0.dtb.accesses 165634538 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 164020888 # DTB hits +system.cpu0.dtb.misses 114038 # DTB misses +system.cpu0.dtb.accesses 164134926 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -518,886 +516,891 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 57441 # Table walker walks requested -system.cpu0.itb.walker.walksLong 57441 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 633 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51280 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 57441 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 57441 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 57441 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 51913 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 24992.593377 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23133.831517 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17289.167601 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 50947 98.14% 98.14% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 829 1.60% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 33 0.06% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 47 0.09% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 45 0.09% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 51913 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 57747 # Table walker walks requested +system.cpu0.itb.walker.walksLong 57747 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51498 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 57747 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 57747 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 57747 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 52059 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25570.833093 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23301.899076 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19704.068320 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 48075 92.35% 92.35% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2753 5.29% 97.64% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 34 0.07% 97.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 1024 1.97% 99.67% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 15 0.03% 99.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 43 0.08% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 19 0.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 37 0.07% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 21 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 6 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 52059 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 51280 98.78% 98.78% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 633 1.22% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 51913 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 51498 98.92% 98.92% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 561 1.08% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 52059 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57441 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57441 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57747 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57747 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51913 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51913 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 109354 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 461199865 # ITB inst hits -system.cpu0.itb.inst_misses 57441 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52059 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52059 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 109806 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 458544228 # ITB inst hits +system.cpu0.itb.inst_misses 57747 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26562 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 26949 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 461257306 # ITB inst accesses -system.cpu0.itb.hits 461199865 # DTB hits -system.cpu0.itb.misses 57441 # DTB misses -system.cpu0.itb.accesses 461257306 # DTB accesses -system.cpu0.numPwrStateTransitions 27854 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13927 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3371332712.012135 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 65010943687.031532 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3873 27.81% 27.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 10023 71.97% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.80% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 18 0.13% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1988778348716 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13927 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 570219734307 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46952550680193 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 95045540829 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 458601975 # ITB inst accesses +system.cpu0.itb.hits 458544228 # DTB hits +system.cpu0.itb.misses 57747 # DTB misses +system.cpu0.itb.accesses 458601975 # DTB accesses +system.cpu0.numPwrStateTransitions 27516 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13758 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3404463734.886103 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 97180881292.374130 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3759 27.32% 27.32% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 9972 72.48% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 12 0.09% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 7033293879000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13758 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 564962851937 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46838612064563 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94807149833 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13927 # number of quiesce instructions executed -system.cpu0.committedInsts 460929213 # Number of instructions committed -system.cpu0.committedOps 541179982 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 497492129 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 434558 # Number of float alu accesses -system.cpu0.num_func_calls 27781850 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 69589132 # number of instructions that are conditional controls -system.cpu0.num_int_insts 497492129 # number of integer instructions -system.cpu0.num_fp_insts 434558 # number of float instructions -system.cpu0.num_int_register_reads 719293830 # number of times the integer registers were read -system.cpu0.num_int_register_writes 394367415 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 718787 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 331792 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 119457726 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 119087316 # number of times the CC registers were written -system.cpu0.num_mem_refs 165514046 # number of memory refs -system.cpu0.num_load_insts 86852092 # Number of load instructions -system.cpu0.num_store_insts 78661954 # Number of store instructions -system.cpu0.num_idle_cycles 93905101360.384018 # Number of idle cycles -system.cpu0.num_busy_cycles 1140439468.615976 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011999 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988001 # Percentage of idle cycles -system.cpu0.Branches 102755128 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 374676211 69.19% 69.19% # Class of executed instruction -system.cpu0.op_class::IntMult 1194745 0.22% 69.41% # Class of executed instruction -system.cpu0.op_class::IntDiv 63344 0.01% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 45411 0.01% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::MemRead 86852092 16.04% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 78661954 14.53% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 13758 # number of quiesce instructions executed +system.cpu0.committedInsts 458270897 # Number of instructions committed +system.cpu0.committedOps 538093671 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 494447989 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 420942 # Number of float alu accesses +system.cpu0.num_func_calls 27507374 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 69395953 # number of instructions that are conditional controls +system.cpu0.num_int_insts 494447989 # number of integer instructions +system.cpu0.num_fp_insts 420942 # number of float instructions +system.cpu0.num_int_register_reads 717601691 # number of times the integer registers were read +system.cpu0.num_int_register_writes 392303230 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 699105 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 312628 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 119518995 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 119177994 # number of times the CC registers were written +system.cpu0.num_mem_refs 164010919 # number of memory refs +system.cpu0.num_load_insts 86087147 # Number of load instructions +system.cpu0.num_store_insts 77923772 # Number of store instructions +system.cpu0.num_idle_cycles 93677224129.124023 # Number of idle cycles +system.cpu0.num_busy_cycles 1129925703.875976 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011918 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988082 # Percentage of idle cycles +system.cpu0.Branches 102213618 # Number of branches fetched +system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 373117768 69.30% 69.30% # Class of executed instruction +system.cpu0.op_class::IntMult 1177948 0.22% 69.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 60910 0.01% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 42581 0.01% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::MemRead 86087147 15.99% 85.53% # Class of executed instruction +system.cpu0.op_class::MemWrite 77923772 14.47% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 541493758 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5689621 # number of replacements -system.cpu0.dcache.tags.tagsinuse 508.423656 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 159582136 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5690133 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.045414 # Average number of references to valid blocks. +system.cpu0.op_class::total 538410126 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5755741 # number of replacements +system.cpu0.dcache.tags.tagsinuse 471.832715 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 158017240 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5756252 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.451411 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.423656 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993015 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.993015 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 336711039 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 336711039 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 80892970 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80892970 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 74279623 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 74279623 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199389 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 199389 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 162229 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 162229 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1824290 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1824290 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1791894 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1791894 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 155334822 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 155334822 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 155534211 # number of overall hits -system.cpu0.dcache.overall_hits::total 155534211 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3104051 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3104051 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1401631 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1401631 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 634089 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 634089 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 792659 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 792659 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 174131 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 174131 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 205146 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 205146 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5298341 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5298341 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5932430 # number of overall misses -system.cpu0.dcache.overall_misses::total 5932430 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46355544000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 46355544000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29179707500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 29179707500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25804948000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 25804948000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2634324500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2634324500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5093103500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5093103500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3129500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3129500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 101340199500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 101340199500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 101340199500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 101340199500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83997021 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83997021 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 75681254 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 75681254 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 833478 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 833478 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 954888 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 954888 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1998421 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1998421 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1997040 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1997040 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 160633163 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 160633163 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 161466641 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 161466641 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036954 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036954 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018520 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018520 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760775 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760775 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.830107 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.830107 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087134 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087134 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102725 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102725 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032984 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.032984 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036741 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.036741 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14933.886073 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14933.886073 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20818.394784 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20818.394784 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32554.917058 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32554.917058 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15128.406200 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15128.406200 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24826.725844 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24826.725844 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.832715 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.921548 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.921548 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 333769183 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 333769183 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 80089936 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 80089936 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73524451 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73524451 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 195750 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 195750 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 158273 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 158273 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1825906 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1825906 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1807959 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1807959 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 153772660 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 153772660 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 153968410 # number of overall hits +system.cpu0.dcache.overall_hits::total 153968410 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3122111 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3122111 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1430717 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1430717 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 657703 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 657703 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 783281 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 783281 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173414 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 173414 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 190134 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 190134 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5336109 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5336109 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5993812 # number of overall misses +system.cpu0.dcache.overall_misses::total 5993812 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46238724000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 46238724000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29544894000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 29544894000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25637315000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 25637315000 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2487014500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2487014500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4740803500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4740803500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2810500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2810500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 101420933000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 101420933000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 101420933000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 101420933000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 83212047 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 83212047 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74955168 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74955168 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853453 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 853453 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 941554 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 941554 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1999320 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1999320 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1998093 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1998093 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 159108769 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 159108769 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 159962222 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 159962222 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037520 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037520 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019088 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.019088 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770638 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770638 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.831902 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.831902 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086736 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086736 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095158 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095158 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033537 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.033537 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037470 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.037470 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14810.083306 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14810.083306 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20650.410948 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20650.410948 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32730.673922 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32730.673922 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14341.486270 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14341.486270 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24934.012328 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24934.012328 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19126.779401 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19126.779401 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17082.409653 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17082.409653 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19006.533225 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19006.533225 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16920.939963 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16920.939963 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5689621 # number of writebacks -system.cpu0.dcache.writebacks::total 5689621 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25484 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25484 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21272 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21272 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45280 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45280 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 46756 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 46756 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 46756 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 46756 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3078567 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3078567 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1380359 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1380359 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 632927 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 632927 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792659 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 792659 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128851 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128851 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 205146 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 205146 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5251585 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5251585 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5884512 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5884512 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27617 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27617 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26565 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26565 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 54182 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 54182 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42188847000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42188847000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27459987000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27459987000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13648405000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13648405000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25012289000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25012289000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1718421000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1718421000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4888014500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4888014500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3072500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3072500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 94661123000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 94661123000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108309528000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 108309528000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5072174500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5072174500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5072174500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5072174500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036651 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036651 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018239 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018239 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759381 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759381 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.830107 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.830107 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064476 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064476 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102725 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102725 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032693 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032693 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036444 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.036444 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13704.053542 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13704.053542 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19893.366146 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19893.366146 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21563.948133 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21563.948133 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31554.917058 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31554.917058 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13336.497194 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.497194 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23827.003695 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23827.003695 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5755741 # number of writebacks +system.cpu0.dcache.writebacks::total 5755741 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25545 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25545 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21233 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21233 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44607 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44607 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 46778 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 46778 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 46778 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 46778 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3096566 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3096566 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1409484 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1409484 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 656541 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 656541 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 783281 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 783281 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128807 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128807 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 190134 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 190134 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5289331 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5289331 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5945872 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5945872 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27575 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27575 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26540 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26540 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 54115 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 54115 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42074729000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42074729000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27794776000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27794776000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13747691500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13747691500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24854034000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24854034000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1645535500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1645535500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4550721500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4550721500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2758500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2758500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 94723539000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 94723539000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108471230500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 108471230500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5071681500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5071681500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5071681500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5071681500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037213 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037213 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018804 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018804 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.769276 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.769276 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.831902 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.831902 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064425 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064425 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095158 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095158 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033243 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033243 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037170 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.037170 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13587.544719 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13587.544719 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.823709 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.823709 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20939.578031 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20939.578031 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31730.673922 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31730.673922 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12775.202435 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12775.202435 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23934.285819 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23934.285819 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18025.248187 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18025.248187 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18405.864072 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18405.864072 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183661.313684 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183661.313684 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93613.644753 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93613.644753 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 5142905 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.908178 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 456056448 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5143417 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.667990 # Average number of references to valid blocks. +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17908.415828 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.415828 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18243.115644 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18243.115644 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183923.173164 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183923.173164 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93720.437956 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93720.437956 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 4916262 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.907947 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 453627454 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4916774 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 92.261197 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 29905343000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.908178 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999821 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999821 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907947 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999820 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999820 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 927543147 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 927543147 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 456056448 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 456056448 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 456056448 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 456056448 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 456056448 # number of overall hits -system.cpu0.icache.overall_hits::total 456056448 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5143417 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5143417 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5143417 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5143417 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5143417 # number of overall misses -system.cpu0.icache.overall_misses::total 5143417 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54463305000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 54463305000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 54463305000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 54463305000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 54463305000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 54463305000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 461199865 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 461199865 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 461199865 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 461199865 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 461199865 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 461199865 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011152 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011152 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011152 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011152 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011152 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10588.934360 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10588.934360 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10588.934360 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10588.934360 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10588.934360 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10588.934360 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 922005230 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 922005230 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 453627454 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 453627454 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 453627454 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 453627454 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 453627454 # number of overall hits +system.cpu0.icache.overall_hits::total 453627454 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4916774 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4916774 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4916774 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4916774 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4916774 # number of overall misses +system.cpu0.icache.overall_misses::total 4916774 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52276659500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 52276659500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 52276659500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 52276659500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 52276659500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 52276659500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 458544228 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 458544228 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 458544228 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 458544228 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 458544228 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 458544228 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010723 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010723 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010723 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010723 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010723 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010723 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10632.308807 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10632.308807 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10632.308807 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10632.308807 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10632.308807 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10632.308807 # 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average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10132.308807 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10132.308807 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10132.308807 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7619798 # 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Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1310 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14708 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 179 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 589 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 529 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 22 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 970 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4517 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5300 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3841 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079956 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897705 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 367708056 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 367708056 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 263860 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148030 # 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number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 290630500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 12910083500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37525239999 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 33693542276 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 84736237775 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4850886500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8346919000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4850748500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8346781000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4850886500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8346919000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.039214 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4850748500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8346781000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042089 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998390 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998390 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997739 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997739 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212561 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212561 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089571 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.244101 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.244101 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.730498 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.730498 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.236805 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157133 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.236805 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.208334 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.208334 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092312 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.237547 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.237547 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.734749 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.734749 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157547 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.225203 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30740.646006 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45077.596675 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20773.248301 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20773.248301 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16322.336666 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16322.336666 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 330625 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 330625 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43135.713443 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43135.713443 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28827.661168 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29046.893485 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29046.893485 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32766.637985 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32766.637985 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31972.336095 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31087.443131 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31972.336095 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35316.144748 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229341 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33277.010739 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45043.939327 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20758.397340 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20758.397340 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16429.331447 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16429.331447 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338357.142857 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338357.142857 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43354.855932 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43354.855932 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28444.013466 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29072.329738 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29072.329738 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32819.905779 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32819.905779 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31096.120257 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35462.445877 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175648.567911 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117990.995448 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175911.097008 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118059.137199 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89529.483961 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85779.224516 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 22441141 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11511110 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 870 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1820685 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1820422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 263 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 564136 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9642625 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26565 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26565 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5274768 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7068022 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2298392 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 883953 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 441648 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 374962 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 517397 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1188175 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1165072 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5143417 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4741538 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 839102 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 790706 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15515989 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18442402 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 326965 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 595128 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 34880484 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 658497108 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 690726071 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1243360 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2186248 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1352652787 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6279047 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 18012222 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.113865 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.317693 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89637.780652 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85836.908680 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 22110497 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11343995 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 879 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1795730 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1795410 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 320 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 572087 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9462372 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26540 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26540 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5352908 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 6850414 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2268094 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 917561 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 438813 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 347856 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 497865 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1218452 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1195725 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4916774 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4752404 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 832834 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 781464 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14836060 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18594952 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327877 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 607160 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 34366049 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 629486804 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 699379029 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1242688 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2226528 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1332335049 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6259200 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 105003768 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 17822799 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.114255 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.318177 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 15961520 88.61% 88.61% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2050439 11.38% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 263 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 15786774 88.58% 88.58% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2035705 11.42% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 320 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 18012222 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 22247152499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 17822799 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 21920125505 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 190413774 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 184217084 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7758250500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7418286000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8155256101 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8250668056 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 171545000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 172541000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 321847000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 328844000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1427,69 +1430,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 105013 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 105013 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10670 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 79078 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 105006 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.076186 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 24.687831 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 105005 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 105006 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 89755 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22913.865523 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21179.498457 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15867.258739 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 88364 98.45% 98.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1205 1.34% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 34 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 69 0.08% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 59 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 89755 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -3159480544 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.804201 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.396815 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -618623648 19.58% 19.58% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -2540856896 80.42% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -3159480544 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 79078 88.11% 88.11% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10670 11.89% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 89748 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105013 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 102344 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 102344 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10188 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 77277 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 10 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 102334 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.244298 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 78.150189 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 102333 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 102334 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 87475 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22637.736496 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21131.866681 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13933.012219 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 86378 98.75% 98.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 960 1.10% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 39 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 87475 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -5328755248 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.736470 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.440547 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1404285148 26.35% 26.35% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -3924470100 73.65% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -5328755248 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 77278 88.35% 88.35% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10188 11.65% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 87466 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 102344 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105013 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89748 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 102344 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87466 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89748 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 194761 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87466 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 189810 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 79229823 # DTB read hits -system.cpu1.dtb.read_misses 76992 # DTB read misses -system.cpu1.dtb.write_hits 72255246 # DTB write hits -system.cpu1.dtb.write_misses 28021 # DTB write misses +system.cpu1.dtb.read_hits 79660508 # DTB read hits +system.cpu1.dtb.read_misses 74735 # DTB read misses +system.cpu1.dtb.write_hits 72705787 # DTB write hits +system.cpu1.dtb.write_misses 27609 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37114 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 36374 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4820 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4588 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10425 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 79306815 # DTB read accesses -system.cpu1.dtb.write_accesses 72283267 # DTB write accesses +system.cpu1.dtb.perms_faults 10004 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 79735243 # DTB read accesses +system.cpu1.dtb.write_accesses 72733396 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 151485069 # DTB hits -system.cpu1.dtb.misses 105013 # DTB misses -system.cpu1.dtb.accesses 151590082 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 152366295 # DTB hits +system.cpu1.dtb.misses 102344 # DTB misses +system.cpu1.dtb.accesses 152468639 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1519,895 +1522,897 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 58945 # Table walker walks requested -system.cpu1.itb.walker.walksLong 58945 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53052 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 58945 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 58945 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 58945 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 53613 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26471.741928 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23919.780193 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 20610.282304 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 48130 89.77% 89.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 4065 7.58% 97.36% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 53 0.10% 97.45% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 1140 2.13% 99.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.06% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 18 0.03% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 57 0.11% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 23 0.04% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 51 0.10% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 22 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 16 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 58593 # Table walker walks requested +system.cpu1.itb.walker.walksLong 58593 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 620 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52801 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 58593 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 58593 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 58593 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 53421 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25912.740308 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23776.245370 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18077.529945 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 47948 89.75% 89.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 4330 8.11% 97.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 49 0.09% 97.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 923 1.73% 99.68% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.06% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 25 0.05% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 42 0.08% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 27 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 53613 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1503172148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1503172148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1503172148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 53052 98.95% 98.95% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 561 1.05% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 53613 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 53421 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1503171148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1503171148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1503171148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 52801 98.84% 98.84% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 620 1.16% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 53421 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58945 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58945 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58593 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58593 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53613 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53613 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 112558 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 420888418 # ITB inst hits -system.cpu1.itb.inst_misses 58945 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53421 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53421 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 112014 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 421982441 # ITB inst hits +system.cpu1.itb.inst_misses 58593 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25811 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 25297 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 420947363 # ITB inst accesses -system.cpu1.itb.hits 420888418 # DTB hits -system.cpu1.itb.misses 58945 # DTB misses -system.cpu1.itb.accesses 420947363 # DTB accesses -system.cpu1.numPwrStateTransitions 9975 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 4987 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 9429340547.425106 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 186307084392.504211 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3401 68.20% 68.20% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1566 31.40% 99.60% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.14% 99.74% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.78% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 8 0.16% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7390880609428 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 4987 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 498649104491 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47024121310009 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 95045540824 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 422041034 # ITB inst accesses +system.cpu1.itb.hits 421982441 # DTB hits +system.cpu1.itb.misses 58593 # DTB misses +system.cpu1.itb.accesses 422041034 # DTB accesses +system.cpu1.numPwrStateTransitions 9904 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 4952 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 9471329494.171041 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 145765994017.543427 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3395 68.56% 68.56% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1531 30.92% 99.47% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.50% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.54% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.06% 99.60% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.72% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.28% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 7470352176392 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 4952 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 501551261365 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46902023655135 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94807149833 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 4988 # number of quiesce instructions executed -system.cpu1.committedInsts 420606589 # Number of instructions committed -system.cpu1.committedOps 495760659 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 455422102 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 465343 # Number of float alu accesses -system.cpu1.num_func_calls 25050170 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 64233743 # number of instructions that are conditional controls -system.cpu1.num_int_insts 455422102 # number of integer instructions -system.cpu1.num_fp_insts 465343 # number of float instructions -system.cpu1.num_int_register_reads 665130045 # number of times the integer registers were read -system.cpu1.num_int_register_writes 361560137 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 742394 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 410584 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 110025684 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 109785328 # number of times the CC registers were written -system.cpu1.num_mem_refs 151477231 # number of memory refs -system.cpu1.num_load_insts 79227868 # Number of load instructions -system.cpu1.num_store_insts 72249363 # Number of store instructions -system.cpu1.num_idle_cycles 94048242615.068481 # Number of idle cycles -system.cpu1.num_busy_cycles 997298208.931515 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010493 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989507 # Percentage of idle cycles -system.cpu1.Branches 93889993 # Number of branches fetched -system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 343412693 69.23% 69.23% # Class of executed instruction -system.cpu1.op_class::IntMult 1029907 0.21% 69.44% # Class of executed instruction -system.cpu1.op_class::IntDiv 56328 0.01% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 66396 0.01% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::MemRead 79227868 15.97% 85.43% # Class of executed instruction -system.cpu1.op_class::MemWrite 72249363 14.57% 100.00% # Class of executed instruction +system.cpu1.kern.inst.quiesce 4952 # number of quiesce instructions executed +system.cpu1.committedInsts 421703858 # Number of instructions committed +system.cpu1.committedOps 497054350 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 456781482 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 475663 # Number of float alu accesses +system.cpu1.num_func_calls 25188507 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 64210733 # number of instructions that are conditional controls +system.cpu1.num_int_insts 456781482 # number of integer instructions +system.cpu1.num_fp_insts 475663 # number of float instructions +system.cpu1.num_int_register_reads 664763727 # number of times the integer registers were read +system.cpu1.num_int_register_writes 362355133 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 757340 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 426036 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 109701618 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 109432507 # number of times the CC registers were written +system.cpu1.num_mem_refs 152358964 # number of memory refs +system.cpu1.num_load_insts 79658830 # Number of load instructions +system.cpu1.num_store_insts 72700134 # Number of store instructions +system.cpu1.num_idle_cycles 93804047310.268021 # Number of idle cycles +system.cpu1.num_busy_cycles 1003102522.731979 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010580 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989420 # Percentage of idle cycles +system.cpu1.Branches 94064671 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 343802607 69.13% 69.13% # Class of executed instruction +system.cpu1.op_class::IntMult 1044362 0.21% 69.34% # Class of executed instruction +system.cpu1.op_class::IntDiv 57840 0.01% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 69226 0.01% 69.36% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction +system.cpu1.op_class::MemRead 79658830 16.02% 85.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 72700134 14.62% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 496042597 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5018466 # number of replacements -system.cpu1.dcache.tags.tagsinuse 434.493139 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 146277741 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5018977 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.144932 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8378732349000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 434.493139 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.848619 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.848619 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 308017993 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 308017993 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 73753622 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 73753622 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 68485479 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 68485479 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 174561 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 174561 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 162110 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 162110 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1665176 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1665176 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1621987 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1621987 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 142401211 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 142401211 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 142575772 # number of overall hits -system.cpu1.dcache.overall_hits::total 142575772 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2838030 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2838030 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1310627 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1310627 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 624714 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 624714 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 447850 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 447850 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162703 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 162703 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 204676 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 204676 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4596507 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4596507 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5221221 # number of overall misses -system.cpu1.dcache.overall_misses::total 5221221 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40862074000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 40862074000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24688918000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 24688918000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10778682000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 10778682000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2442456000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2442456000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5069864000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5069864000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3108000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3108000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 76329674000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 76329674000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 76329674000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 76329674000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 76591652 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 76591652 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 69796106 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 69796106 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 799275 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 799275 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 609960 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 609960 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1827879 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1827879 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1826663 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1826663 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 146997718 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 146997718 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 147796993 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 147796993 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037054 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037054 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018778 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018778 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.781601 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.781601 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.734228 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.734228 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089012 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089012 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112049 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112049 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031269 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031269 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035327 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035327 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14398.041599 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14398.041599 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18837.486180 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18837.486180 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24067.616389 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24067.616389 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15011.745327 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15011.745327 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24770.192890 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24770.192890 # average StoreCondReq miss latency +system.cpu1.op_class::total 497333042 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5003393 # number of replacements +system.cpu1.dcache.tags.tagsinuse 453.941998 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 147178696 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5003905 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.412768 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8378733231000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 453.941998 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.886605 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.886605 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 309758535 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 309758535 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 74209320 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 74209320 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68941180 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 68941180 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 175621 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 175621 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 163479 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 163479 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1660182 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1660182 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1630108 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1630108 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 143313979 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 143313979 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 143489600 # number of overall hits +system.cpu1.dcache.overall_hits::total 143489600 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2836392 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2836392 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1297238 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1297238 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 605603 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 605603 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 460373 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 460373 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162387 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 162387 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 191354 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 191354 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4594003 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4594003 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5199606 # number of overall misses +system.cpu1.dcache.overall_misses::total 5199606 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40714366500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 40714366500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24361465000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 24361465000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11037691000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 11037691000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2429522000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2429522000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4779056000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4779056000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2991500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2991500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 76113522500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 76113522500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 76113522500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 76113522500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 77045712 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 77045712 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 70238418 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 70238418 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 781224 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 781224 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 623852 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 623852 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1822569 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1822569 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1821462 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1821462 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 147907982 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 147907982 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 148689206 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 148689206 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036814 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036814 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018469 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018469 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.775198 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.775198 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.737952 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.737952 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089098 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089098 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105055 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105055 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031060 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031060 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034970 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034970 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14354.280544 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14354.280544 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18779.487650 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18779.487650 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23975.539400 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23975.539400 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14961.308479 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14961.308479 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24974.946957 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24974.946957 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16606.017134 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16606.017134 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14619.123381 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14619.123381 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16568.017587 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16568.017587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14638.325000 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14638.325000 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5018466 # number of writebacks -system.cpu1.dcache.writebacks::total 5018466 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16365 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 16365 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 405 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 405 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42163 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42163 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 16770 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 16770 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 16770 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 16770 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2821665 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2821665 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1310222 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1310222 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 624714 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 624714 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 447850 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 447850 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120540 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120540 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 204676 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 204676 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4579737 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4579737 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5204451 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5204451 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11035 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11035 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11949 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11949 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22984 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22984 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 37160053500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 37160053500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23356658000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23356658000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12967475000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12967475000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10330832000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10330832000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1654542500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1654542500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4865246000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4865246000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3050000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3050000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 70847543500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 70847543500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83815018500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 83815018500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1894238000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1894238000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1894238000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1894238000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036840 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036840 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018772 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018772 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.781601 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.781601 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.734228 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.734228 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065945 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065945 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112049 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112049 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031155 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031155 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035214 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035214 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13169.548299 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13169.548299 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17826.488946 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17826.488946 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20757.458613 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20757.458613 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23067.616389 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23067.616389 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13726.086776 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13726.086776 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23770.476265 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23770.476265 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5003393 # number of writebacks +system.cpu1.dcache.writebacks::total 5003393 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17753 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 17753 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 420 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 420 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44380 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44380 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 18173 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 18173 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 18173 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 18173 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2818639 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2818639 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1296818 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1296818 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 605603 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 605603 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 460373 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 460373 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 118007 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 118007 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 191354 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 191354 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4575830 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4575830 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5181433 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5181433 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11021 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11021 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11924 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11924 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22945 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22945 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36912397500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36912397500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23044975500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23044975500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12992134000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12992134000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10577318000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10577318000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1572635000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1572635000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4587759000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4587759000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2934500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2934500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 70534691000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 70534691000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83526825000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 83526825000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1888408000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1888408000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1888408000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1888408000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036584 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036584 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018463 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018463 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.775198 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.775198 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.737952 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.737952 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064748 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064748 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105055 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105055 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030937 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030937 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034847 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034847 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13095.823020 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13095.823020 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17770.400704 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17770.400704 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21453.219353 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21453.219353 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22975.539400 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22975.539400 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13326.624692 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13326.624692 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23975.244834 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23975.244834 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15469.784291 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15469.784291 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16104.487966 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16104.487966 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171657.272315 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171657.272315 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82415.506439 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82415.506439 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 4797887 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.259979 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 416090013 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4798399 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 86.714342 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8378704245000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.259979 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969258 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969258 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15414.622265 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15414.622265 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16120.410126 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16120.410126 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171346.338808 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171346.338808 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82301.503596 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82301.503596 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 5018955 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.221127 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 416962969 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5019467 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 83.069172 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8378705112000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.221127 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969182 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969182 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 277 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 846575240 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 846575240 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 416090013 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 416090013 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 416090013 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 416090013 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 416090013 # number of overall hits -system.cpu1.icache.overall_hits::total 416090013 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4798405 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4798405 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4798405 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4798405 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4798405 # number of overall misses -system.cpu1.icache.overall_misses::total 4798405 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50998473000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 50998473000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 50998473000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 50998473000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 50998473000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 50998473000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 420888418 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 420888418 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 420888418 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 420888418 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 420888418 # 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average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10628.213542 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10628.213542 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 848984354 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 848984354 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 416962969 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 416962969 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 416962969 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 416962969 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 416962969 # number of overall hits +system.cpu1.icache.overall_hits::total 416962969 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5019472 # 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number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5019472 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5019472 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5019472 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5019472 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 48599271000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 48599271000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 48599271000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 48599271000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 48599271000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 48599271000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10226500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10226500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10226500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10226500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011401 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011401 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011401 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10128.213646 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92968.181818 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92968.181818 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6995617 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6995617 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50676607000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 50676607000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50676607000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 50676607000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50676607000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 50676607000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10226000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10226000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10226000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10226000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011895 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011895 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011895 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10096.003524 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92963.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92963.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6881080 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6881096 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 854583 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 1970256 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13301.448664 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 14231615 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1985806 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.166669 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10058718427000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12287.437490 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 44.190300 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 64.411311 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 905.409563 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.749966 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002697 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003931 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055262 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.811856 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1582 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13889 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 228 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 690 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 664 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 38 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2519 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5802 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5375 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.096558 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.847717 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 333785497 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 333785497 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 241732 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150683 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 392415 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3174179 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3174179 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6641283 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6641283 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 549 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 848093 # 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mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.048696 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 22945 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 23055 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 320463500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 286584000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 607047500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 26432385766 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 26432385766 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4355093500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4355093500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3151504000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3151504000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2506499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2506499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8136910999 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8136910999 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12995030000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12995030000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 23494652500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 23494652500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6984949000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6984949000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 320463500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 286584000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12995030000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 31631563499 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 45233640999 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 320463500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 286584000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12995030000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 31631563499 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 26432385766 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 71666026765 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9401000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1799706000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1809107000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9401000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1799706000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1809107000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.048387 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997389 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997389 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998054 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998054 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226104 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226104 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095639 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.251611 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251611 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.565082 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.565082 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245591 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.164542 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245591 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.227317 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.227317 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092400 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.247304 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247304 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.559345 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.559345 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242597 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159812 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242597 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.234134 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 34156.170658 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40544.234544 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20963.093200 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20963.093200 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16265.559497 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16265.559497 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261449.900000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261449.900000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33154.607626 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33154.607626 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27413.278436 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26323.631135 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26323.631135 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27139.318892 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27139.318892 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27807.991174 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27775.004552 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27807.991174 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31570.422456 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163610.104214 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162838.851503 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78551.927428 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78584.870529 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 20384822 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10471744 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 887 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760623 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 174 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 491097 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 8950741 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11949 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11949 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4279928 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6642170 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2284917 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 836860 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 390891 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 375101 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 483493 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1131381 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1109621 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4798405 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4426002 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 496716 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 445955 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14394916 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16294669 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 336160 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 556294 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 31582039 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 614163064 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 626579614 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1280144 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2019872 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1244042694 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5755928 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 16349135 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.122449 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.327837 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.226443 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30905.584971 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39436.606887 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21015.139744 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21015.139744 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16470.098826 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16470.098826 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 358071.285714 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 358071.285714 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32795.710752 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32795.710752 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28018.546747 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26819.950937 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26819.950937 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27249.405073 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27249.405073 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28137.968207 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31462.605744 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163297.885854 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162528.703621 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78435.650469 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78469.182390 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 20762161 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10650842 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1727817 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1727605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 212 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 482395 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9130479 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11924 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11924 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4254476 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6851297 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2274133 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 818827 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 384823 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 346834 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 460171 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1120311 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1099104 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5019472 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4398430 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 506547 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 458275 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15058119 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16186537 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 334443 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 542756 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 32121855 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 642459768 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 622853650 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1275376 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1972104 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1268560898 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5663025 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 75880456 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 16447181 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.119069 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.323910 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 14347367 87.76% 87.76% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2001594 12.24% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 174 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 14489040 88.09% 88.09% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1957929 11.90% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 212 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 16349135 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 20146131499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 16447181 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 20541870997 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 187574309 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 171936035 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7197716000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7529318000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7451139989 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7396555908 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 176142000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 175021499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 303810499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 296243499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40346 # Transaction distribution system.iobus.trans_dist::ReadResp 40346 # Transaction distribution -system.iobus.trans_dist::WriteReq 136634 # Transaction distribution -system.iobus.trans_dist::WriteResp 136634 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47740 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 136621 # Transaction distribution +system.iobus.trans_dist::WriteResp 136621 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2420,13 +2425,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122674 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231206 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122616 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231238 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231238 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47760 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2439,21 +2444,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155781 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338840 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155723 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338968 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496707 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36949503 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496777 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36887001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2465,77 +2470,77 @@ system.iobus.reqLayer15.occupancy 8500 # La system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26494000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26455501 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37417500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37419000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569020926 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569241095 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92771000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92726000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147902000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147934000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115585 # number of replacements -system.iocache.tags.tagsinuse 11.243817 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115616 # number of replacements +system.iocache.tags.tagsinuse 11.233110 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115632 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9095565849000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.827817 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.416000 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239239 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.463500 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.702739 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9095552544000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.412176 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.820935 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463261 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.238808 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.702069 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040784 # Number of tag accesses -system.iocache.tags.data_accesses 1040784 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040928 # Number of tag accesses +system.iocache.tags.data_accesses 1040928 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8912 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8891 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8928 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115603 # number of demand (read+write) misses -system.iocache.demand_misses::total 115643 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115619 # number of demand (read+write) misses +system.iocache.demand_misses::total 115659 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115603 # number of overall misses -system.iocache.overall_misses::total 115643 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1623231612 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1628431112 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115619 # number of overall misses +system.iocache.overall_misses::total 115659 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1628324544 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1633522544 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12905416814 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12905416814 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14528648426 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14534216926 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14528648426 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14534216926 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12891433551 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12891433551 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14519758095 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14525325095 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14519758095 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14525325095 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8875 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8891 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8928 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115603 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115643 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115619 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115659 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115603 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115643 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115619 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115659 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2549,53 +2554,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182899.336563 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182723.419210 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183143.014734 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182966.234767 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120918.754348 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120918.754348 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125677.088190 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125681.769982 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125677.088190 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125681.769982 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31595 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120787.736592 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120787.736592 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125587.503739 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125587.503739 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31812 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3437 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3498 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.192610 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.094340 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106695 # number of writebacks system.iocache.writebacks::total 106695 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8875 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8891 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8928 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115603 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115643 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115619 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115659 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115603 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115643 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1179481612 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1182831112 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115619 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115659 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1183774544 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1187122544 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7559977711 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7559977711 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8739459323 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8743027823 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8739459323 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8743027823 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7546042407 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7546042407 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8729816951 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8733383951 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8729816951 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8733383951 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2609,657 +2614,659 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132899.336563 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 132723.419210 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133143.014734 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 132966.234767 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70834.061455 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70834.061455 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1336257 # number of replacements -system.l2c.tags.tagsinuse 63239.486009 # Cycle average of tags in use -system.l2c.tags.total_refs 5390392 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1394864 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.864457 # Average number of references to valid blocks. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70703.493057 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70703.493057 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1334376 # number of replacements +system.l2c.tags.tagsinuse 63294.471519 # Cycle average of tags in use +system.l2c.tags.total_refs 5390543 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1393372 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.868703 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 9808893500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 23096.089917 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 135.068224 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 220.083460 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4065.866850 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8220.853874 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8325.282047 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 163.986041 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 269.420690 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2932.882407 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5116.369986 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10693.582513 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.352418 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003358 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062040 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.125440 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.127034 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002502 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004111 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.044752 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.078070 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.163171 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.964958 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10513 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 227 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 47867 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 208 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 519 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9786 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1623 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 40883 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.160416 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003464 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.730392 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2618.991189 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.339099 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003990 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.006964 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.053434 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.159135 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.255156 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000638 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000757 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.048699 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.057964 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5501 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 41094 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.158112 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004181 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.737915 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 69824789 # Number of tag accesses +system.l2c.tags.data_accesses 69824789 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2605015 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2605015 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 157240 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 131498 # 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mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.150063 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.231467 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.789622 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.483301 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.699157 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.271982 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.198571 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.254149 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.271982 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.198571 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.254149 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21804.686224 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21789.373306 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21797.121392 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24741.881127 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24821.487996 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24781.010243 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77565.508997 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73518.653872 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 75964.793177 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78972.962237 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81122.516121 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96202.092831 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19963.677770 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20378.857088 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20048.436388 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78452.136670 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78418.732639 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 93138.115636 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78452.136670 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78418.732639 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 93138.115636 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.281261 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.315767 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.297398 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.256383 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.267881 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.262106 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.636223 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.466619 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.558420 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.282554 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.350195 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.100203 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.199992 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461188 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.225694 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.230468 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.094547 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.156065 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.391065 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.231890 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.791527 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.489286 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.701201 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.282554 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.350195 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100203 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.269664 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461188 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.225694 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.230468 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.094547 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.201857 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.391065 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.254259 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.282554 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.350195 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100203 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.269664 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461188 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.225694 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.230468 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.094547 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.201857 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.391065 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.254259 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21760.189820 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21827.206064 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21793.465721 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24758.927154 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24820.062840 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24790.027679 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77420.562538 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73582.192289 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75949.234159 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78536.396441 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81766.937359 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96011.218611 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19970.157087 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20362.317730 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20051.936203 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78115.935572 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78977.140746 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 92992.813894 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78115.935572 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78977.140746 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 92992.813894 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157644.476482 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145634.098069 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106095.762484 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157908.812439 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145322.987748 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106109.716665 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80352.654147 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69914.759551 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 72157.173324 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3697678 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2246661 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3188 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80464.483101 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69795.318921 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 72180.858446 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3668271 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2217535 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3152 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 81885 # Transaction distribution -system.membus.trans_dist::ReadResp 837971 # Transaction distribution -system.membus.trans_dist::WriteReq 38514 # Transaction distribution -system.membus.trans_dist::WriteResp 38514 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1175339 # Transaction distribution -system.membus.trans_dist::CleanEvict 216465 # Transaction distribution -system.membus.trans_dist::UpgradeReq 402269 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 335845 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 81829 # Transaction distribution +system.membus.trans_dist::ReadResp 838129 # Transaction distribution +system.membus.trans_dist::WriteReq 38464 # Transaction distribution +system.membus.trans_dist::WriteResp 38464 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1174756 # Transaction distribution +system.membus.trans_dist::CleanEvict 216961 # Transaction distribution +system.membus.trans_dist::UpgradeReq 398327 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 309165 # Transaction distribution system.membus.trans_dist::UpgradeResp 22 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 147056 # Transaction distribution -system.membus.trans_dist::ReadExResp 129063 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 756086 # Transaction distribution -system.membus.trans_dist::InvalidateReq 664574 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122674 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 145872 # Transaction distribution +system.membus.trans_dist::ReadExResp 127949 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 756300 # Transaction distribution +system.membus.trans_dist::InvalidateReq 666856 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122616 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26434 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4433526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4582726 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237876 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237876 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4820602 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155781 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26280 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4403166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4552154 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237974 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237974 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4790128 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155723 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52868 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124620204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 124829057 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7253952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 132083009 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 605187 # Total snoops (count) -system.membus.snoop_fanout::samples 2426230 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013777 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.116566 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124524268 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 124732755 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7257216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 131989971 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 572885 # Total snoops (count) +system.membus.snoopTraffic 188480 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2396814 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013654 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.116050 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2392803 98.62% 98.62% # Request fanout histogram -system.membus.snoop_fanout::1 33427 1.38% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2364088 98.63% 98.63% # Request fanout histogram +system.membus.snoop_fanout::1 32726 1.37% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2426230 # Request fanout histogram -system.membus.reqLayer0.occupancy 101268497 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2396814 # Request fanout histogram +system.membus.reqLayer0.occupancy 101168498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21861496 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21745999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8209418227 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8211058586 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4835085635 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4830240380 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45398182 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45484396 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3302,77 +3309,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 10840157 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5896724 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1754214 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 132701 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 121224 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11477 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 81887 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4082535 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38514 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38514 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3675345 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2314292 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 683405 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 409707 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1093112 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 292338 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 292338 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4001459 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 832376 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 802179 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8623692 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7234411 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15858103 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 210145531 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 178915910 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 389061441 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2781791 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7676067 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.360389 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.483218 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 10770571 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5860830 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1720391 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 132185 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 120739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 11446 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 81831 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4048119 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38464 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38464 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3673076 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2310912 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 679438 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 381379 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1060817 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 109 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 291982 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 291982 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3967045 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 832947 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 803400 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8640930 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144066 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15784996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 212830169 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175839034 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 388669203 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2716758 # Total snoops (count) +system.toL2Bus.snoopTraffic 119453392 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7607581 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.354994 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.481646 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4921172 64.11% 64.11% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2743418 35.74% 99.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11477 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4918380 64.65% 64.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2677755 35.20% 99.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 11446 0.15% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7676067 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8520913919 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7607581 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8483488339 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2554437 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2591888 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3920667694 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3918166834 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3580148330 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3514899349 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal index ac6936025..8a6e02412 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000032] Console: colour dummy device 80x25
-[ 0.000036] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000037] pid_max: default: 32768 minimum: 301
-[ 0.000053] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000054] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000245] hw perfevents: no hardware support available
-[ 0.060065] CPU1: Booted secondary processor
-[ 1.080104] CPU2: failed to come online
-[ 2.100199] CPU3: failed to come online
-[ 2.100203] Brought up 2 CPUs
-[ 2.100204] SMP: Total of 2 processors activated.
-[ 2.100286] devtmpfs: initialized
-[ 2.100949] atomic64_test: passed
-[ 2.101011] regulator-dummy: no parameters
-[ 2.101476] NET: Registered protocol family 16
-[ 2.101658] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 2.101666] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 2.103275] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 2.103279] Serial: AMBA PL011 UART driver
-[ 2.103525] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 2.103576] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 2.104152] console [ttyAMA0] enabled
-[ 2.104323] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 2.104394] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 2.104465] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 2.104535] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 2.150406] 3V3: 3300 mV
-[ 2.150465] vgaarb: loaded
-[ 2.150535] SCSI subsystem initialized
-[ 2.150576] libata version 3.00 loaded.
-[ 2.150646] usbcore: registered new interface driver usbfs
-[ 2.150667] usbcore: registered new interface driver hub
-[ 2.150693] usbcore: registered new device driver usb
-[ 2.150726] pps_core: LinuxPPS API ver. 1 registered
-[ 2.150736] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 2.150757] PTP clock support registered
-[ 2.150931] Switched to clocksource arch_sys_counter
-[ 2.152285] NET: Registered protocol family 2
-[ 2.152391] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 2.152411] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 2.152431] TCP: Hash tables configured (established 2048 bind 2048)
-[ 2.152471] TCP: reno registered
-[ 2.152479] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.152493] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.152538] NET: Registered protocol family 1
-[ 2.152603] RPC: Registered named UNIX socket transport module.
-[ 2.152613] RPC: Registered udp transport module.
-[ 2.152622] RPC: Registered tcp transport module.
-[ 2.152630] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 2.152643] PCI: CLS 0 bytes, default 64
-[ 2.152855] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 2.152973] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 2.155121] fuse init (API version 7.23)
-[ 2.155231] msgmni has been set to 469
-[ 2.157249] io scheduler noop registered
-[ 2.157315] io scheduler cfq registered (default)
-[ 2.158049] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 2.158063] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 2.158075] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.158088] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 2.158099] pci_bus 0000:00: scanning bus
-[ 2.158111] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 2.158125] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 2.158141] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.158181] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 2.158194] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 2.158205] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 2.158216] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.158227] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 2.158239] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 2.158251] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.158291] pci_bus 0000:00: fixups for bus
-[ 2.158300] pci_bus 0000:00: bus scan returning with max=00
-[ 2.158312] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 2.158334] pci 0000:00:00.0: fixup irq: got 33
-[ 2.158343] pci 0000:00:00.0: assigning IRQ 33
-[ 2.158355] pci 0000:00:01.0: fixup irq: got 34
-[ 2.158364] pci 0000:00:01.0: assigning IRQ 34
-[ 2.158377] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 2.158390] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.158404] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 2.158417] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 2.158429] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.158441] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 2.158453] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 2.158465] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 2.159060] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.159386] ata_piix 0000:00:01.0: version 2.13
-[ 2.159397] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.159432] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.159775] scsi0 : ata_piix
-[ 2.159868] scsi1 : ata_piix
-[ 2.159904] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.159917] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.160058] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 2.160070] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 2.160086] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.160098] e1000 0000:00:00.0: enabling bus mastering
-[ 2.300957] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.300967] ata1.00: 2096640 sectors, multi 0: LBA
-[ 2.300998] ata1.00: configured for UDMA/33
-[ 2.301069] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.301206] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 2.301211] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.301241] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.301251] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.301279] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.301443] sda: sda1
-[ 2.301585] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 2.421256] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 2.421269] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 2.421295] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 2.421306] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 2.421330] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 2.421342] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 2.421439] usbcore: registered new interface driver usb-storage
-[ 2.421506] mousedev: PS/2 mouse device common for all mice
-[ 2.421699] usbcore: registered new interface driver usbhid
-[ 2.421709] usbhid: USB HID core driver
-[ 2.421746] TCP: cubic registered
-[ 2.421755] NET: Registered protocol family 17
- -[ 2.422264] devtmpfs: mounted
-[ 2.422355] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000027] Console: colour dummy device 80x25
+[ 0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000032] pid_max: default: 32768 minimum: 301
+[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000047] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000186] hw perfevents: no hardware support available
+[ 0.060051] CPU1: Booted secondary processor
+[ 1.080095] CPU2: failed to come online
+[ 2.100183] CPU3: failed to come online
+[ 2.100186] Brought up 2 CPUs
+[ 2.100188] SMP: Total of 2 processors activated.
+[ 2.100259] devtmpfs: initialized
+[ 2.100898] atomic64_test: passed
+[ 2.100952] regulator-dummy: no parameters
+[ 2.101389] NET: Registered protocol family 16
+[ 2.101557] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.101563] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.102363] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.102366] Serial: AMBA PL011 UART driver
+[ 2.102592] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.102637] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.103214] console [ttyAMA0] enabled
+[ 2.103383] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.103459] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.103535] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.103603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.130362] 3V3: 3300 mV
+[ 2.130420] vgaarb: loaded
+[ 2.130477] SCSI subsystem initialized
+[ 2.130513] libata version 3.00 loaded.
+[ 2.130567] usbcore: registered new interface driver usbfs
+[ 2.130587] usbcore: registered new interface driver hub
+[ 2.130614] usbcore: registered new device driver usb
+[ 2.130645] pps_core: LinuxPPS API ver. 1 registered
+[ 2.130654] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.130674] PTP clock support registered
+[ 2.130822] Switched to clocksource arch_sys_counter
+[ 2.132478] NET: Registered protocol family 2
+[ 2.132574] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.132593] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.132613] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.132642] TCP: reno registered
+[ 2.132649] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.132663] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.132704] NET: Registered protocol family 1
+[ 2.132763] RPC: Registered named UNIX socket transport module.
+[ 2.132774] RPC: Registered udp transport module.
+[ 2.132782] RPC: Registered tcp transport module.
+[ 2.132791] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.132804] PCI: CLS 0 bytes, default 64
+[ 2.133012] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.133128] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.135205] fuse init (API version 7.23)
+[ 2.135350] msgmni has been set to 469
+[ 2.135656] io scheduler noop registered
+[ 2.135718] io scheduler cfq registered (default)
+[ 2.136286] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.136300] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.136311] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.136324] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.136335] pci_bus 0000:00: scanning bus
+[ 2.136346] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.136360] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.136375] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.136416] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.136429] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.136440] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.136452] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.136463] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.136474] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.136486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.136527] pci_bus 0000:00: fixups for bus
+[ 2.136536] pci_bus 0000:00: bus scan returning with max=00
+[ 2.136548] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.136569] pci 0000:00:00.0: fixup irq: got 33
+[ 2.136578] pci 0000:00:00.0: assigning IRQ 33
+[ 2.136589] pci 0000:00:01.0: fixup irq: got 34
+[ 2.136598] pci 0000:00:01.0: assigning IRQ 34
+[ 2.136609] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.136623] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.136636] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.136650] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.136662] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.136674] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.136686] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.136698] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.137491] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.137826] ata_piix 0000:00:01.0: version 2.13
+[ 2.137837] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.137864] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.138204] scsi0 : ata_piix
+[ 2.138329] scsi1 : ata_piix
+[ 2.138380] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.138393] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.138543] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.138556] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.138573] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.138585] e1000 0000:00:00.0: enabling bus mastering
+[ 2.280852] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.280862] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.280892] ata1.00: configured for UDMA/33
+[ 2.280951] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.281082] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.281116] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.281160] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.281170] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.281192] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.281337] sda: sda1
+[ 2.281470] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.401164] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.401177] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.401211] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.401224] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.401253] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.401268] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.401414] usbcore: registered new interface driver usb-storage
+[ 2.401486] mousedev: PS/2 mouse device common for all mice
+[ 2.401677] usbcore: registered new interface driver usbhid
+[ 2.401687] usbhid: USB HID core driver
+[ 2.401726] TCP: cubic registered
+[ 2.401734] NET: Registered protocol family 17
+ +[ 2.402215] devtmpfs: mounted
+[ 2.402270] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.462786] udevd[609]: starting version 182
+[ 2.442337] udevd[608]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.544201] random: dd urandom read with 18 bits of entropy available
+[ 2.533997] random: dd urandom read with 18 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.681165] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.671053] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
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